CN113053757A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN113053757A
CN113053757A CN202010879929.1A CN202010879929A CN113053757A CN 113053757 A CN113053757 A CN 113053757A CN 202010879929 A CN202010879929 A CN 202010879929A CN 113053757 A CN113053757 A CN 113053757A
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China
Prior art keywords
package
patch
forming
reinforcing
redistribution structure
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CN202010879929.1A
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English (en)
Inventor
许佳桂
游明志
林柏尧
陈硕懋
许峯诚
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113053757A publication Critical patent/CN113053757A/zh
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Abstract

一种方法包括形成再分布结构，该形成工艺包括在载体上方形成多个介电层，形成延伸到多个介电层中的多条再分布线，以及在载体上方形成增强贴片。该方法还包括将封装组件接合至再分布结构，封装组件具有与增强贴片的部分重叠的外围区域。并且将再分布结构和第一封装组件从载体脱粘。本发明的实施例还涉及封装件及其形成方法。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，需要将更多功能集成到半导体管芯中。因此，半导体管芯需要将越来越多的I/O焊盘封装到较小的区域中，并且I/O焊盘的密度会随着时间的推移而迅速提高。结果，半导体管芯的封装变得更加困难，这不利地影响封装的良率。
在常规封装技术中，在管芯被封装之前，从晶圆切割出管芯。这种封装技术的一个有利特征是可以形成扇出封装件的可能性，这意味着管芯上的I/O焊盘可以再分布到比管芯更大的区域，因此，封装在管芯的表面上的I/O焊盘的数量也可以增加。该封装技术的另一个有利特征是，封装“已知良好管芯”，并且丢弃有缺陷的管芯，因此，不会在有缺陷的管芯上浪费成本和精力。在封装中，形成多个介电层和多条再分布线。再分布线电连接至管芯。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：形成再分布结构，包括：在载体上方形成多个介电层；形成延伸到所述多个介电层中的多条再分布线；和在所述载体上方形成增强贴片；将第一封装组件接合至所述再分布结构，其中，所述第一封装组件包括与所述增强贴片的部分重叠的外围区域；以及使所述再分布结构和所述第一封装组件从所述载体脱粘。
本发明的另一实施例提供了一种封装件，包括：再分布结构，包括：多个介电层；多条再分布线，延伸到所述多个介电层中；和增强贴片，与所述多个介电层重叠，其中，所述增强贴片包括金属材料；第一封装组件，位于所述再分布结构上方并且接合至所述再分布结构；以及底部填充物，位于所述再分布结构和所述第一封装组件之间，其中，所述底部填充物接触所述增强贴片。
本发明的又一实施例提供了一种封装件，包括：再分布结构，包括：多个介电层；多条再分布线，延伸到所述多个介电层中；和增强贴片，接触所述多个介电层中的一个，其中，所述增强贴片是电浮置的；以及封装组件，接合至所述再分布结构，其中，所述增强贴片包括与所述封装组件的拐角部分重叠的第一部分。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图14示出了根据一些实施例的在形成包括增强贴片的封装件中的中间阶段的截面图。
图15A和图15B分别示出了根据一些实施例的具有增强贴片的封装件的截面图和平面图，该增强贴片具有电功能。
图16A、图16B、图16C、图16D、图16E、图16F和图16G示出了根据一些实施例的示例增强贴片的图案。
图17至图19示出了根据一些实施例的一些增强贴片的布局。
图20和图21分别示出了根据一些实施例的具有通孔的封装件的截面图和平面图。
图22示出了根据一些实施例的具有多个封装组件和相应的增强贴片的封装件的截面图。
图23示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开提供了许多用于实现本发明的不同特征的不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然，这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的间距关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，间距关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的间距关系描述符可以同样地作相应地解释。
根据一些实施例，提供了包括增强贴片的封装件及其形成方法。根据本发明的一些实施例，增强贴片由金属形成，并且具有高密度。增强贴片位于遭受高应力的区域中，诸如在封装件中的管芯的外围正下方的区域中。本文讨论的实施例将提供示例，以使得能够进行或使用本发明的主题，并且本领域普通技术人员将容易理解可以进行的修改，同时保持在不同实施例的预期范围内。贯穿各种视图和说明性实施例，相同的参考标号用于指示相同的元件。尽管方法实施例可以被讨论为以特定顺序执行，但是其他方法实施例可以以任何逻辑顺序执行。
图1至图14示出了根据本发明的一些实施例的在封装件的形成中的中间阶段的截面图。相应的工艺也示意性地反映在图23所示的工艺流程中。
图1示出了载体20和形成在载体20上的释放膜22。根据一些实施例，载体20可以是玻璃载体。载体20可以具有圆形的顶视图形状。释放膜22可以由光热转换(LTHC)材料形成，该材料可以被分解，使得将在后续步骤中形成的上面的结构可以从载体20释放。根据本发明的一些实施例，释放膜22由基于环氧的热释放材料形成。可以将释放膜22涂布在载体20上。释放膜22的顶面是水平的并且是平坦的。
介电层24形成在释放膜22上。相应的工艺示出为如图23所示的工艺流程200中的工艺202。根据本发明的一些实施例，介电层24由聚合物形成，聚合物可以由聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等形成或包括聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等。介电层24也可以由非聚合物(无机材料)形成或包括非聚合物(无机材料)，该非聚合物可以是氧化硅、氮化硅、氮氧化硅等。
参考图2，在介电层24上方形成再分布线(RDL)26(以及可能的增强贴片27)。相应的工艺示出为如图23所示的工艺流程200中的工艺204。RDL 26的形成可以包括在介电层24上方形成晶种层(未示出)，在晶种层上方形成诸如光刻胶的图案化的掩模(未示出)，以及然后在暴露的晶种层上执行金属镀工艺以镀金属材料。然后去除图案化的掩模和由图案化的掩模覆盖的晶种层的部分，留下如图2中的RDL26。根据本发明的一些实施例，晶种层包括钛层和位于钛层上方的铜层。可以使用例如物理气相沉积(PVD)形成晶种层。可以使用例如电化学电镀来执行镀。镀的金属材料可以包括金属或金属合金，金属或金属合金包括铜、铝、钨等。RDL 26可以包括用于接合凸块下金属(UBM)的金属焊盘，以及用于路由电信号、电源等的金属迹线。
根据一些实施例，在形成RDL 26的同时，使用用于形成RDL 26的相同工艺来形成增强贴片27。在后续段落中讨论增强贴片27的细节。根据可选实施例，没有形成增强贴片27。
参考图3，在RDL 26上形成介电层28。相应的工艺示出为如图23所示的工艺流程200中的工艺206。介电层28的底面与RDL 26、增强贴片27和介电层24的顶面接触。根据本发明的一些实施例，介电层28由聚合物形成，该聚合物可以是聚酰亚胺、PBO、BCB等。根据本发明的可选实施例，介电层28由非聚合物(无机)材料形成，非聚合物(无机)材料可以包括氧化硅、氮化硅等。然后图案化介电层28以在其中形成开口30。因此，RDL 26的一些部分通过介电层28中的开口30暴露。
接下来，参考图4，形成RDL 32(以及可能的增强贴片33)以连接至RDL26。相应的工艺示出为如图23所示的工艺流程200中的工艺208。RDL32包括位于介电层28上方的金属迹线(金属线)。RDL32还包括延伸到介电层28的开口30中的通孔。RDL32也以镀工艺形成，其中每个RDL32包括晶种层(未示出)和位于晶种层上方的镀金属材料。晶种层的材料和镀金属材料可以分别选自RDL 26中的晶种层和镀金属材料的相同候选材料。
根据一些实施例，在形成RDL 32的同时，以用于形成RDL 32的相同工艺形成增强贴片33。在后续段落中讨论增强贴片33的细节。根据可选实施例，没有形成增强贴片33。
参考图5，在RDL 32和介电层28上方形成介电层34。相应的工艺示出为如图23所示的工艺流程200中的工艺210。根据本发明的一些实施例，介电层34由聚合物形成，该聚合物可以是聚酰亚胺、PBO、BCB等。根据本发明的可选实施例，介电层34可以由无机材料形成，该无机材料可以选自氧化硅、氮化硅、碳氮化硅、氮氧化硅等。
图6示出了RDL 36(电连接至RDL 32)和相应的增强贴片37的形成。相应的工艺示出为如图23所示的工艺流程200中的工艺212。RDL 36的形成可以采用与用于形成RDL 32的方法和材料相似的方法和材料。可以理解，尽管在说明性示例实施例中，讨论了三个介电层24、28和34以及在其中形成的相应的RDL 26、32和36，但是根据布线要求和使用聚合物缓冲应力的要求，可以采用更少或更多的介电层和RDL层。例如，可以存在两个介电层或四个、五个或更多介电层以及相应的RDL层。
根据一些实施例，在形成RDL 36的同时，以用于形成RDL 32的相同工艺来形成增强贴片37。根据可选实施例，不形成增强贴片37。在后续段落中讨论增强贴片37的细节。特征之一示出为36/37，以指示它可用于电气路由和机械增强中的一个或两个。例如，RDL/增强贴片36/37可以用于路由而不是用于增强，用于增强而不是用于路由，或者用于路由和增强，这将在后续段落中讨论。
参考图7，在RDL 36和介电层34上方形成介电层38。相应的工艺示出为如图23所示的工艺流程200中的工艺214。根据本发明的一些实施例，介电层38由聚合物形成，该聚合物可以是聚酰亚胺、PBO、BCB等。根据本发明的可选实施例，介电层38由无机材料形成，该无机材料可以选自氧化硅、氮化硅、碳氮化硅、氮氧化硅等。
参考图8，在介电层38中形成开口40以露出下面的RDL36。可以或可以不露出增强贴片37(如果形成)。根据本发明的一些实施例，介电层38由诸如聚酰亚胺或PBO的光敏材料形成。因此，开口40的形成可以包括使用光刻掩模对介电层38执行曝光工艺，该光刻掩模包括不透明和透明图案。然后使介电层38显影以形成开口40。
参考图9，形成UBM 42和增强贴片44。UBM 42还可以具有路由功能，因此也被称为RDL42。相应的工艺示出为如图23所示的工艺流程200中的工艺216。UBM42和增强贴片44的形成工艺可以包括在介电层38上形成毯式金属晶种层(未单独示出)，在金属晶种层上形成诸如光刻胶的图案化的掩模(未示出)，然后在暴露的金属晶种层上执行金属镀工艺。然后去除图案化的掩模和由图案化的掩模覆盖的金属晶种层的部分，留下UBM 42和增强贴片44。根据本发明的一些实施例，金属晶种层包括钛层和位于钛层上方的铜层，其中钛晶种层和铜晶种层形成为共形层，该共形层包括延伸到开口40中的第一部分和位于介电层38上方的第二部分。可以使用例如PVD形成金属晶种层。可以使用例如电化学镀来执行镀。由于UBM42和增强贴片44可以在共同的工艺中形成，因此UBM 42和增强贴片44可以具有相同的结构并且由相同的材料形成。根据可选实施例，UBM 42和增强贴片44可以在单独的工艺中形成，并且因此可以由选自钛、铜、镍、钯等的不同材料或相同材料形成。
根据一些实施例，所有的增强贴片44都位于介电层38上方，并且在介电层38中没有将增强贴片44连接至介电层38中的下面的导电部件的通孔。根据本发明的可选实施例，一些或全部的增强贴片44通过通孔46电连接并物理连接至下面的RDL 36和/或增强贴片37。通孔46因此以虚线示出以指示可以形成或可以不形成通孔46。增强贴片44和通孔46(如果形成)以共同的形成工艺形成。在整个说明书中，释放膜22上方的部件(包括RDL、增强贴片和介电层)统称为再分布结构48。
接下来，封装组件52A和52B接合至再分布结构48，如图10所示。相应的工艺示出为如图23所示的工艺流程200中的工艺218。根据本发明的一些实施例，封装组件52A和52B包括逻辑管芯、存储器管芯、输入输出(IO)管芯、管芯堆叠件、封装件等的任意组合。还应当理解，尽管示出了两个封装组件，但是可以存在多组封装组件，其中每组包括接合至再分布结构48的一个、三个、四个、五个或更多封装组件。根据一些实施例，逻辑管芯可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、基带(BB)管芯、应用处理器(AP)管芯等。存储器管芯可以包括动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等。管芯堆叠件可以包括存储器管芯堆叠件，存储器管芯堆叠件可以是高带宽存储器(HBM)堆叠件。封装组件52A和52B可以彼此相同或彼此不同。封装组件52A和52B也统称为封装组件52。
封装组件52A和52B的接合可以通过焊料接合，其中焊料区域53将UBM 42连接至封装组件52A和52B中的金属焊盘(或微凸块)50。根据可选实施例，可以使用其他类型的接合方法，诸如混合接合、直接金属至金属接合等。
图11示出了分配底部填充物54和密封剂56进行密封。相应的工艺示出为如图23所示的工艺流程200中的工艺220。根据一些实施例，首先将底部填充物54分配到封装组件52和再分布结构48之间的间隙中。在相邻的封装组件52之间可以或可以不分配底部填充物54。密封剂56可以由模塑料、模制底部填充物、环氧树脂、树脂等形成或包括模塑料、模制底部填充物、环氧树脂、树脂等。底部填充物54和密封剂56以可流动形式分配，然后固化。当由模塑料形成时，密封剂56可以包括基底材料(可以是聚合物、树脂、环氧树脂等)以及该基底材料中的填料颗粒。填料颗粒可以是SiO2、Al2O3、二氧化硅等的介电颗粒，并且可以具有球形。而且，球形填料颗粒可以具有多个不同的直径。可以执行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺，以使封装组件52的顶面与密封剂56的顶面齐平。在整个说明书中，释放膜22上方的部件(包括再分布结构48、封装组件52、底部填充物54和密封剂56)统称为重建晶圆100。
接下来，将重建晶圆100从载体20脱粘，相应的工艺示出为如图23所示的工艺流程200中的工艺222。根据一些实施例，激光束扫描穿过载体20以投射到释放膜22上。释放膜22吸收激光束的能量并分解。因此可以从释放膜22上提起载体20，并且因此将重建晶圆100从载体20脱粘(拆卸)。在图12中示出了所得的重建晶圆100，并且与图11相比颠倒示出。
进一步参考图12，在介电层24中形成开口58。根据本发明的一些实施例，开口58的形成包括激光钻孔工艺、蚀刻工艺等。RDL 26中的金属焊盘暴露于开口58。
参考图13，形成UBM 60和增强贴片62。相应的工艺示出为如图23所示的工艺流程200中的工艺224。UBM 60和增强贴片62的形成工艺可以包括在介电层24上方形成金属晶种层(未显示)，在金属晶种层上方形成诸如光刻胶的图案化的掩模(未示出)，以及然后在暴露的晶种层上执行金属镀工艺。然后去除图案化的掩模和由图案化的掩模覆盖的金属晶种层的部分，留下UBM 60和增强贴片62。根据本发明的一些实施例，金属晶种层包括钛层和位于钛层上方的铜层，其中钛晶种层形成为共形层，共形层包括延伸到开口58中的第一部分和位于介电层24上方的第二部分。可以使用例如PVD形成金属晶种层。可以使用例如电化学镀来执行镀。由于UBM 60和增强贴片62可以在共同的工艺中形成，所以UBM 60和增强贴片62可以具有相同的结构并且由相同的材料形成。根据可选实施例，UBM 60和增强贴片62可以在单独的工艺中形成，并且因此可以由不同的材料或相同的材料形成。
然后在UBM 60上形成焊料区域64。相应的工艺也示出为如图23所示的工艺流程200中的工艺224。根据一些实施例，焊料区域64的形成可以包括在UBM 60上放置焊球，然后回流放置的焊球。根据可选实施例，焊料区域64的形成工艺可以包括在UBM 60上镀焊料区域，然后回流镀的焊料区域。然后可以执行分割工艺以将重建晶圆100锯成彼此相同的多个封装件100’。
图14示出了封装件100’与封装组件66的接合，使得形成封装件70。根据本发明的一些实施例，封装组件66是或包括封装衬底、中介层、封装件等。底部填充物68可被分配到封装件100’和封装组件66之间的间隙中。因此，增强贴片62可以与底部填充物68接触。
图16A、图16B、图16C、图16D、图16E、图16F和图16G示出了一些示例增强贴片27、33、37、44和62的平面图。在后续段落中，增强贴片27、33、37、44和62单独或共同地表示为增强贴片74。因此，示出的增强贴片标记为74，以指示任何增强贴片27、33、37、44和62可以采用这些图案。图16A示出了矩形的增强贴片74，其是实心的并且在其中没有贯通孔。图16B示出了圆形的增强贴片，其是实心的并且在其中没有贯通孔。图16C示出了由蛇形线形成的增强贴片74。图16D示出了其中具有贯通孔72的矩形增强贴片。图16E示出了由网格形成的增强贴片，其包括水平线和与水平线相交的垂直线。网格也可以被视为其中具有多个贯通孔的金属板，贯通孔形成阵列。图16F示出了椭圆形的增强贴片，其是实心的并且在其中没有贯通孔。图16G示出了具有不规则形状的增强贴片。可以理解的是，所示的增强贴片是示例，并且可以通过组合这些示例中的特征来形成更多的增强贴片，只要这些特征是适用的即可。例如，贯通孔72(图16D)可以形成在图16B、16F和16G等所示的任何增强贴片74中。同样，具有网格图案的增强贴片也可以具有图16B、16F和16G所示的外部轮廓75。
为了保持增强贴片74具有足够的强度以增强结构，增强贴片74被设计成具有足够的尺寸。例如，图16A、图16C、图16D、图16E、图16F和图16G中的长度L和宽度W以及图16B中的直径D1可以大于约500μm，并且可以在约500μm和约10000μm之间的范围内。此外，在由虚线示出的轮廓75限定的区域中，金属的总密度足够高，其中金属密度是轮廓75中的金属总面积与轮廓75内的总面积之比。例如，金属密度可以大于约70％，并且可以在约70％和100％之间(当增强贴片为实心时)。否则，如果增强贴片74太薄和/或金属密度太低，则在应力下，增强贴片74将容易变形，并且没有足够的强度来增强封装件。
再次参考图14，增强贴片27、33、37、44和62用于增强封装件100’。例如，封装组件52接合至RDL结构48，并且封装组件52的热膨胀系数(CTE)和RDL结构48的CTE之间存在显著差异。这导致在靠近封装组件52的外围区域的区域以及靠近相邻封装组件52之间的间隙的区域中生成显著的应力。例如，在图14所示的示例中，存在位于封装组件52A和52B之间的间隙正下方的一些增强贴片27、33、37、44A和62A。这些增强贴片也可以在封装组件52A和/或52B的外围区域正下方延伸。而且，在封装组件52A和/或52B的外围区域的正下方存在一些增强贴片(诸如44B和62B)。
图17至图19示出了一些增强贴片74(包括增强贴片74A、74B和74C)的平面图，并且任何增强贴片74都可以表示增强贴片27、33、37、44和62的任意组合。如图17所示，增强贴片74A设置在封装组件52A和52B的拐角处(和下面)。为了具有足够的增强能力，增强贴片74A的长度L1和宽度W1可以大于约500μm，并且可以在约500μm至约10000μm的范围内。此外，封装组件52A和52B与增强贴片74重叠足够的面积。例如，重叠长度L2和重叠宽度W2可以大于约200μm。非交叠长度L2’和非交叠宽度W2’也可以大于约200μm，使得增强贴片74可以扩展得足够远以向应力最高的附近区域提供增强力。
增强贴片74B靠近封装组件52A和52B之间的间隙设置。根据一些实施例，增强贴片74B在封装组件52A和52B之间的间隙正下方的整个区域中扩展，并且可以在封装组件52A和52B之一或两者正下方延伸。因此，增强贴片74的宽度W3大于封装组件52A和52B之间的间隙G。此外，增强贴片74的重叠宽度W4可以大于约200μm，并且可以在约200μm和约500μm之间的范围内。增强贴片74的长度L3可以大于组件52A和52B的长度。可以从图17所示的参考截面14-14获得图14所示的参考截面。
图18示出了根据其他实施例的增强贴片74的平面图。增强贴片74可以在封装组件52A和52B中的每个的外围区域周围形成一个环或多个环。当封装组件52不止一个时，相邻的增强贴片环可以彼此连接，使得连接区域可跨越相邻的封装组件52之间的整个间隙。此外，每个增强贴片环可以包括位于相应封装组件52的外围区域正下方的内部部分以及不与相应封装组件52重叠的外部部分。因此，外部部分也可以是在平面中环绕相应封装组件52的环。根据一些实施例，重叠宽度W4(也是增强贴片环的内部部分的宽度)可以大于约200μm。
图19示出了根据其他实施例的包括增强贴片74的封装件70的平面图。封装件70包括与环绕较大的封装组件52A和52B的环对准的一些外部较小的封装组件52C。高应力更可能在较大的封装组件52A和52B的外围区域周围发生，而不太可能在较小的封装组件52C的外围区域周围发生。因此，增强贴片74可以形成为靠近较大的封装组件52A和52B的外围区域，并且可以或者可以不形成为靠近较小的封装组件52C的外围区域。例如，如图19所示，增强贴片74形成在封装组件52A和52B周围并且可以在封装组件52A和52B下方延伸。增强贴片74可以或可以不在较小的封装组件52C正下方延伸。
再次回到图14，增强贴片27、33、37、44和62可以是电浮置的。根据一些实施例，每个增强贴片27、33、37、44和62可以形成为离散且隔离的部件，而没有通孔连接至增强贴片。因此，每个相应的增强贴片27、33、37、44和62被完全封闭在介电材料中。根据可选实施例，一些相邻的增强贴片可以与(通过通孔)上面和/或下面的增强贴片连接以形成连接的结构，使得进一步改进增强能力。连接的结构可以仍然是电浮置的，并且可以完全封闭在介电材料中。例如，如图14所示，当形成通孔46时，增强贴片44A和44B可以与相应的下面的增强贴片37形成连接的结构。根据可选实施例，增强贴片27、33、37、44和62电接地，并且可以具有电屏蔽功能。根据可选实施例，增强贴片27、33、37、44和62连接至正电源电压Vdd。
图15A示出了根据可选实施例的封装件70。除了增强贴片27、33、37、44和/或62(除了具有机械增强功能之外)还可以具有电功能之外，这些实施例与图14所示的实施例相似。例如，增强贴片44A可以通过焊料区域53A互连封装组件52A和52B。在这些实施例中，增强贴片44A还用作相应的焊料区域53A的UBM。封装组件52A可以电连接至封装组件52B，其中电接地或电源电压Vdd由增强贴片44A承载。封装组件52A也可以信号连接至封装组件52B，信号通过增强贴片44A传递。类似于图14中的实施例，可以在增强贴片44A正下方形成或不形成通孔46，以连接至增强贴片37。
图15B示出了具有电功能的增强贴片44A的平面图。所示的增强贴片44A使用图16E所示的图案作为示例，但是可以使用具有其他图案的增强贴片。焊料区域53A形成为连接至增强贴片44A的相对端部。还示出了可以形成或可以不形成的通孔46。可以理解的是，尽管示出了两个，但是可以存在贯穿贴片44A的多个通孔46。下面的增强贴片37(如果形成并连接至增强贴片44A)可以具有与增强贴片44A相同的形状或不同的形状。
图15A还示出了增强贴片44C，其分布在除了靠近封装组件52的外围区域之外的位置。尽管未示出，但是类似的增强贴片44C可以形成在其他层中，例如，以与所示的增强贴片27、33和37相同的形成工艺形成。增强贴片44C可以形成在可以为其形成提供足够的空间的任何地方，使得它们具有足够的尺寸以执行增强功能。如图15A所示，一些增强贴片44C可以与封装组件52A和/或52B完全重叠，而一些其他增强贴片可以与封装组件52A和52B完全偏移。尽管未示出，但是可以在诸如图14、图20和图22所示的其他封装件70中形成增强贴片44C。
图20和图21分别示出了根据一些实施例的封装件70的截面图和顶视图。这些实施例与图14和图15A中所示的实施例相似，除了通孔78形成在密封剂56中并且用于将再分布结构48电连接至封装件80。根据本发明的一些实施例，通孔78的形成包括在介电层38中形成开口以暴露RDL 36中的一些金属焊盘，形成延伸到该开口中的金属晶种层，在再分布结构48上方形成诸如光刻胶的镀掩模，图案化镀掩模以形成附加开口，以及在附加开口中镀通孔78。在介电层38中形成通孔79，以将通孔78连接至RDL36。根据一些实施例，为了降低制造成本，用于通孔79的通孔开口可以与UBM 42的通孔开口同时形成。因此，用于形成通孔79和通孔78的金属晶种层可以是用于形成UBM 42和增强贴片44的相同金属晶种层。换句话说，通孔78和通孔79与UBM 42共享相同的通孔开口形成工艺和相同的金属晶种层形成工艺，但是具有与UBM 42不同的镀掩模和不同的镀工艺。根据一些实施例，在形成通孔78之后，封装组件52可以接合至再分布结构48。
在将通孔78和封装组件52密封在密封剂56中之后，封装件80通过焊料区域84接合至通孔78。根据一些实施例，封装件80包括接合至封装衬底的存储器管芯。可以分配底部填充物82以保护焊料区域84。然后将相应的重建晶圆锯成封装件100’。封装组件66与其中一个封装件100’接合。
图21示出了根据一些实施例的具有通孔78的封装件70的示例性平面图。通孔78可以与环绕封装组件52的环对准。根据一些实施例，还示出了增强贴片74。应当理解，所示的增强贴片74和封装组件52是示例，并且也可以采用诸如图18和图19所示的其他布局。
图22示出了根据一些实施例的封装件70的截面图。这些实施例类似于图14和图15A所示的实施例，除了封装组件52A和52B之外，可以存在多个封装组件52C。根据一些实施例，封装组件52A和52B是逻辑管芯，并且封装组件52C可以是存储器管芯、诸如HBM的存储器管芯堆叠件、存储器封装件等。图22可以从图19中所示的参考横截面22-22中获得。
在以上示例性实施例中，根据本发明的一些实施例讨论了一些工艺和部件，以形成三维(3D)封装件。也可以包括其他部件和工艺。例如，可以包括测试结构以帮助对3D封装或3DIC器件进行验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，该测试焊盘允许使用探针和/或探针卡等测试3D封装或3DIC。可以对中间结构以及最终结构执行验证测试。另外，本文公开的结构和方法可以与结合了已知良好管芯的中间验证的测试方法结合使用，以提高良率并降低成本。
本发明的实施例具有一些有利特征。通过在应力较高的封装件的一些位置形成增强贴片，增强贴片可以为封装件提供额外的机械支撑。可以形成与一些RDL的形成工艺共享共同的工艺的增强贴片，因此不会产生额外的成本。
根据本发明的一些实施例，一种方法包括：形成再分布结构，形成再分布结构包括在载体上方形成多个介电层；形成延伸到多个介电层中的多条再分布线；以及在载体上方形成增强贴片；将第一封装组件接合至再分布结构，其中，第一封装组件包括与增强贴片的部分重叠的外围区域；以及使再分布结构和第一封装组件从载体脱粘。根据实施例，该方法还包括在第一封装组件和再分布结构之间分配底部填充物，其中底部填充物接触增强贴片。根据实施例，该方法还包括：在脱粘之后，形成附加增强贴片，其中，该增强贴片和该附加增强贴片位于多个介电层的相对侧上。根据实施例，形成再分布结构还包括形成延伸到多个介电层的一个中的多个凸块下金属，其中，增强贴片和多个凸块下金属以共同的工艺形成，并且其中第一封装组件接合至多个凸块下金属。根据实施例，形成增强贴片包括镀。根据实施例，在脱粘之后，将增强贴片完全封闭在介电材料中。根据实施例，该方法还包括将第二封装组件接合至再分布结构，其中，增强贴片包括与所述第一封装组件重叠的第一部分；与第二封装组件重叠的第二部分；将第一部分连接至第二部分的第三部分。根据实施例，增强贴片具有网格图案。
根据本发明的一些实施例，封装件包括：再分布结构，该再分布结构包括多个介电层；多条再分布线，延伸到多个介电层中；以及增强贴片，与多个介电层重叠，其中，增强贴片包括金属材料；第一封装组件，位于再分布结构上方并且接合至再分布结构；以及底部填充物，位于再分布结构和第一封装组件之间，其中底部填充物接触增强贴片。根据实施例，增强贴片完全封闭在介电材料中。根据实施例，增强贴片具有大于约500μm的宽度。根据实施例，增强贴片与第一封装组件的边缘部分重叠，重叠宽度大于约200μm。根据实施例，增强贴片是电浮置的。根据实施例，增强贴片电连接至第一封装组件，并且增强贴片具有网格结构。根据实施例，增强贴片在第一封装组件的四个边缘附近形成环。
根据本发明的一些实施例，封装件包括：再分布结构，该再分布结构包括多个介电层；多条再分布线，延伸到多个介电层中；以及增强贴片，接触多个介电层中的一个，其中增强贴片是电浮置的；以及封装组件，接合至再分布结构，其中，增强贴片包括与封装组件的拐角部分重叠的第一部分。根据实施例，增强贴片还包括延伸超过封装组件的第二部分。根据实施例，增强贴片的第一部分的宽度大于约200μm。根据实施例，增强贴片形成环，该环包括：内部部分，与封装组件重叠；以及外部部分，延伸超过封装组件的边缘，其中内部部分和外部部分均具有环形形状。根据实施例，结构还包括位于再分布结构与封装组件之间的底部填充物，其中底部填充物接触增强贴片。
本发明概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基底来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同配置并且不面向远离本发明的精神和范围，并且在不面向远离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成封装件的方法，包括：
形成再分布结构，包括：
在载体上方形成多个介电层；
形成延伸到所述多个介电层中的多条再分布线；和
在所述载体上方形成增强贴片；
将第一封装组件接合至所述再分布结构，其中，所述第一封装组件包括与所述增强贴片的部分重叠的外围区域；以及
使所述再分布结构和所述第一封装组件从所述载体脱粘。
2.根据权利要求1所述的方法，还包括在所述第一封装组件和所述再分布结构之间分配底部填充物，其中，所述底部填充物接触所述增强贴片。
3.根据权利要求1所述的方法，还包括：在所述脱粘之后，形成附加增强贴片，其中，所述增强贴片和所述附加增强贴片位于所述多个介电层的相对侧上。
4.根据权利要求1所述的方法，其中，形成所述再分布结构还包括：
形成延伸到所述多个介电层的一个中的多个凸块下金属，其中，所述增强贴片和所述多个凸块下金属以共同工艺形成，并且其中，所述第一封装组件接合至所述多个凸块下金属。
5.根据权利要求1所述的方法，其中，形成所述增强贴片包括镀。
6.根据权利要求1所述的方法，其中，在所述脱粘之后，将所述增强贴片完全封闭在介电材料中。
7.根据权利要求1所述的方法，还包括将第二封装组件接合至所述再分布结构，其中，所述增强贴片包括：
第一部分，与所述第一封装组件重叠；
第二部分，与所述第二封装组件重叠；以及
第三部分，将所述第一部分连接至所述第二部分。
8.根据权利要求1所述的方法，其中，所述增强贴片具有网格图案。
9.一种封装件，包括：
再分布结构，包括：
多个介电层；
多条再分布线，延伸到所述多个介电层中；和
增强贴片，与所述多个介电层重叠，其中，所述增强贴片包括金属材料；
第一封装组件，位于所述再分布结构上方并且接合至所述再分布结构；以及
底部填充物，位于所述再分布结构和所述第一封装组件之间，其中，所述底部填充物接触所述增强贴片。
10.一种封装件，包括：
再分布结构，包括：
多个介电层；
多条再分布线，延伸到所述多个介电层中；和
增强贴片，接触所述多个介电层中的一个，其中，所述增强贴片是电浮置的；以及
封装组件，接合至所述再分布结构，其中，所述增强贴片包括与所述封装组件的拐角部分重叠的第一部分。
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