CN113594046A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN113594046A
CN113594046A CN202110284525.2A CN202110284525A CN113594046A CN 113594046 A CN113594046 A CN 113594046A CN 202110284525 A CN202110284525 A CN 202110284525A CN 113594046 A CN113594046 A CN 113594046A
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China
Prior art keywords
conductive
dielectric layer
conductive pad
center
conductive bump
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CN202110284525.2A
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English (en)
Inventor
叶书伸
杨哲嘉
汪金华
林柏尧
郑心圃
林嘉祥
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113594046A publication Critical patent/CN113594046A/zh
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Abstract

方法包括形成第一介电层；形成包括延伸至第一介电层中的第一通孔的第一再分布线，以及位于第一介电层上方的第一迹线；形成覆盖第一再分布线的第二介电层；以及图案化第二介电层以形成通孔开口。第一再分布线通过通孔开口露出。方法还包括在第二介电层中形成第二通孔，并且在第二通孔上方形成接触第二通孔的导电焊盘；以及在导电焊盘上方形成导电凸块。导电焊盘大于导电凸块，并且导电焊盘的第一中心从导电凸块的第二中心偏离。第二通孔从导电凸块的第二中心偏离更远。本申请的实施例还涉及半导体结构及其形成方法。

Description

半导体结构及其形成方法
技术领域
本申请的实施例涉及半导体结构及其形成方法。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，需要将更多功能集成至半导体管芯中。因此，半导体管芯需要将越来越大数量的I/O焊盘封装至较小的区域中，并且I/O焊盘的密度随着时间的推移而迅速增加。因此，半导体管芯的封装变得更加困难，这不利地影响了封装件的良率。
典型的接合结构可以包括作为金属焊盘的凸块下金属(UBM)和UBM上的金属柱。焊料区域可以用于将金属柱接合至另一封装组件的另一电连接件。
发明内容
本申请的一些实施例提供了一种形成半导体结构的方法，包括：形成第一介电层；形成第一再分布线，所述第一再分布线包括延伸至所述第一介电层中的第一通孔和位于所述第一介电层上方的第一迹线；形成覆盖所述第一再分布线的第二介电层；图案化所述第二介电层以形成通孔开口，其中，所述第一再分布线通过所述通孔开口露出；在所述第二介电层中形成第二通孔，并且在所述第二通孔上方形成接触所述第二通孔的导电焊盘；以及在所述导电焊盘上方形成导电凸块，其中，所述导电焊盘大于所述导电凸块，并且所述导电焊盘的第一中心从所述导电凸块的第二中心偏离，并且其中，所述第二通孔从所述导电凸块的第二中心偏离更远。
本申请的另一些实施例提供了一种半导体结构，包括：第一介电层；第一通孔，延伸至所述第一介电层中；导电迹线，位于所述第一介电层上方，其中，所述导电迹线位于所述第一通孔上方并结合至所述第一通孔；第二介电层，覆盖所述导电迹线；第二通孔，位于所述第二介电层中；导电焊盘，位于所述第二通孔上方并接触所述第二通孔；其中，所述导电焊盘具有第一中心；以及导电凸块，位于所述导电焊盘上方并接触所述导电焊盘，其中，所述导电凸块具有第二中心，并且其中，所述第二通孔和所述导电凸块的所述第二中心位于所述导电焊盘的所述第一中心的相对侧上。
本申请的又一些实施例提供了一种半导体结构，包括：多个介电层；多个再分布线，位于所述多个介电层中，其中，所述多个再分布线的每个包括通孔和位于所述通孔上方并接触所述通孔的迹线，并且将所述多个再分布线中的一些通孔堆叠以形成通孔堆叠件，其中，所述通孔垂直对准；顶部通孔，位于所述多个再分布线的顶部再分布线中的顶部迹线上方并接触所述顶部迹线；导电焊盘，位于所述顶部通孔上方并接触所述顶部通孔；以及导电凸块，位于所述导电焊盘上方并结合至所述导电焊盘，其中，所述导电凸块和所述顶部通孔是偏心的，并且其中，所述导电焊盘包括：第一部分，延伸超过所述导电凸块的第一边缘至第一距离，以及第二部分，延伸超过所述导电凸块的第二边缘至小于所述第一距离的第二距离，其中，所述第一部分比所述第二部分窄。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图12示出了根据一些实施例的形成包括偏心接合结构的互连组件的中间阶段的截面图。
图13示出了根据一些实施例的包括偏心接合结构的封装件。
图14示出了根据一些实施例的偏心接合结构的截面图。
图15示出了根据一些实施例的偏心接合结构的顶视图。
图16示出了根据一些实施例的具有较窄的中间部分的再分布线的顶视图。
图17示出了根据一些实施例的偏心接合结构的截面图。
图18示出了根据一些实施例的偏心接合结构的顶视图。
图19示出了根据一些实施例的具有较窄的中间部分的再分布线的顶视图。
图20和图21示出了根据一些实施例模拟的结构。
图22示出了根据一些实施例的用于形成包括偏心接合结构的互连组件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同部件的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。另外，本发明可以在各个实例中重复参考数字和/或字母。该重复是出于简化和清楚的目的，其本身并不指示所讨论的各个实施例和/或结构之间的关系。
进一步，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以容易地描述如图所示的一个元件或部件与另一个元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
提供了包括偏心接合结构的封装件及其形成方法。根据本发明的一些实施例，形成导电凸块(可以是金属柱)，并且在导电凸块之下形成导电焊盘，其中，导电焊盘大于导电凸块。导电焊盘是细长的，并且可以具有比另一侧窄的一侧。第一通孔位于导电焊盘下面并结合至导电焊盘。第一通孔从上面的导电凸块的中心垂直地偏离。位于第一通孔下面并结合至第一通孔的再分布线可以具有较窄的中心部分。位于第一通孔下面并电连接到第一通孔的多个第二通孔也从第一通孔偏移。导电焊盘和再分布线的偏移和特定形状可以防止具有高热膨胀系数(CTE)值的导电凸块、导电焊盘以及通孔垂直对准，并且因此可以减小应力。本文讨论的实施例将提供实例以使得能够进行或使用本发明的主题，并且本领域普通技术人员将容易理解可以进行的修改，同时保持在不同实施例的预期范围内。贯穿各个视图和示例性实施例，相同的参考标号用于指示相同的元件。尽管讨论的方法实施例可以以特定顺序执行，其他方法实施例可以以任何逻辑顺序执行。
图1至图12示出了根据本发明的一些实施例的形成包括偏心接合结构的互连组件中的中间阶段的截面图。相应的工艺也示意性地反映在图22所示的工艺流程中。可以理解的是，尽管包括偏心接合结构的互连组件是从载体开始形成的，它也可以从诸如器件管芯的扇出型互连结构、器件管芯的部分或中介层等其他组开始形成。
图1示出了载体20和形成在载体20上释放膜22。载体20可以是玻璃载体、硅晶圆、有机载体等。根据一些实施例，载体20可以具有圆形的顶视图形状。释放膜22可以由能够在诸如激光束的辐射下分解的聚合物基材料(诸如光热转换(LTHC)材料)形成，从而使得载体20可以从在随后的工艺中形成的上面的结构剥离。根据本发明的一些实施例，释放膜22包括涂覆至载体20上的环氧基热释放材料。
如图1至图4所示，在释放膜22上方形成多个介电层和多个RDL。相应工艺示为在图22所示的工艺流程200中的工艺202。参考图1，首先在释放膜22上形成介电层24。根据本发明的一些实施例，介电层24由聚合物形成，该聚合物也可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料，这可以使用光刻工艺容易地图案化。
根据一些实施例，在介电层24上方形成再分布线(RDL)26。RDL 26的形成可以包括在介电层24上方形成晶种层(未示出)，在晶种层上方形成诸如光刻胶的图案化的掩模(未示出)，并且然后在暴露的晶种层上执行金属镀工艺。然后去除图案化的掩模和由图案化的掩模覆盖的晶种层的部分，留下如图1中的RDL 26。根据本发明的一些实施例，晶种层包括钛层和位于钛层上方的铜层。可以使用例如物理气相沉积(PVD)或类似工艺来形成晶种层。可以使用例如化学镀来执行镀。
进一步参考图1，在RDL 26上形成介电层28。介电层28的底面接触RDL26和介电层24的顶面。根据本发明的一些实施例，介电层28由可以是诸如PBO、聚酰亚胺、BCB等的光敏材料的聚合物形成。可选地，介电层28可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等的非有机介电材料。然后图案化介电层28以在其中形成开口30。从而，RDL 26的一些部分通过介电层28中的开口30暴露。
接下来，参考图2，形成RDL 32以连接至RDL 26。RDL 32包括位于介电层28上方的金属迹线(金属线)。RDL 32也包括延伸至介电层28中的开口30中的通孔。也可以通过镀工艺形成RDL 32，其中，每个RDL 32包括晶种层(未示出)和位于晶种层上方的镀金属材料。根据一些实施例，RDL 32的形成可以包括：沉积延伸至通孔开口中的毯式金属晶种层；以及形成并图案化镀掩模(诸如光刻胶)，其中，开口直接形成在通孔开口上方。然后执行镀工艺以镀金属材料，该金属材料完全填充通孔开口30，并且具有比介电层28的顶面高的一些部分。然后去除镀掩模，随后进行蚀刻工艺以去除金属晶种层的先前由镀掩模覆盖的暴露部分。金属晶种层的剩余部分和镀金属材料为RDL32。
金属晶种层和镀材料可以由相同的材料或不同的材料形成。RDL 32中的金属材料可以包括金属或金属合金，金属或金属合金包含铜、铝、钨或其合金。RDL 32包括RDL线(也称为迹线或迹线部分)32L和通孔部分(也称为通孔)32V，其中，迹线部分32L位于介电层28上方，并且通孔部分32V位于介电层28中。因为迹线部分32L和通孔部分(也称为通孔)32V是在相同的镀工艺中形成，通孔32V和相应的上面的迹线部分32L之间没有可区分的界面。而且，每个通孔32V可以具有锥形轮廓，其中，上部比相应的下部宽。
参考图3，在RDL 32和介电层28上方形成介电层34。可以使用聚合物形成介电层34，该聚合物可以选自与介电层28的那些相同的候选材料组。例如，介电层34可以由PBO、聚酰亚胺、BCB等形成。可选地，介电层34可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等的非有机介电材料。
图3还示出了电连接至RDL 32的RDL36的形成。RDL36的形成可以采用与用于形成RDL 32相似的方法和材料。RDL36包括迹线部分(RDL线)36L和通孔部分(通孔)36V，其中迹线部分36L位于介电层34上方，并且通孔36V延伸至介电层34中。而且，每个通孔36V可以具有锥形轮廓，其中，上部比相应的下部宽。
图4示出了介电层38和42以及RDL40和44的形成。根据本发明的一些实施例，介电层38和42由选自用于形成介电层34和38的相同的候选材料组的材料形成，并且可以包括如上所述的有机材料或无机材料。应当理解，尽管在所示的示例性实施例中，讨论的四个介电层28、34、38和42以及形成在其中的相应的RDL 32、36、40和44作为实例，取决于布线需求，可以采用更少或更多的介电层和RDL层。
图5至图10示出了根据一些实施例的通孔56、导电焊盘58和导电凸块60(图10)的形成。参考图5，形成介电层46。相应的工艺示为图22所示的工艺流程200中的工艺204。根据一些实施例，介电层46由可以是诸如PBO、聚酰亚胺、BCB等的光敏材料的聚合物形成。图案化介电层46以形成通孔开口48，从而使得下面的RDL线44L的焊盘部分暴露。相应的工艺示为图22所示的工艺流程200中的工艺206。根据一些实施例，通孔开口48从相应的下面的通孔44V横向偏离。如图5所示，相对于相应的上面的RDL线44L的中心线，一些通孔44V可以相比于相应的开口48偏离至相对侧。
参考图6，沉积金属晶种层51。相应的工艺示为图22所示的工艺流程200中的工艺208。根据一些实施例，金属晶种层51包括钛层和位于钛层上方的铜层。根据可选的实施例，金属晶种层51包括物理接触介电层46的单个铜层。然后形成并且图案化镀掩模50，其中，开口52形成在镀掩模50中。相应的工艺示为图22所示的工艺流程200中的工艺210。通孔开口48位于开口52下方并与结合至开口52。开口52的顶视图形状可以是不规则的，例如，具有如图15所示的导电焊盘58的形状。
参考图7，通过镀工艺沉积金属材料54。相应的工艺示为图22所示的工艺流程200中的工艺212。镀工艺可以包括电化学镀、化学镀等。根据一些实施例，金属材料54包括铜或铜合金。可以调节工艺条件，从而使得镀材料54的顶面可以是平坦的。根据可选的实施例，金属材料54的顶面部分可以具有凹槽，如虚线53所示，该凹槽是由于通孔开口48的填充而形成的(图7)。
在随后的工艺中，例如可以通过灰化工艺去除可以是光刻胶的镀掩模50。相应的工艺示为图22所示的工艺流程200中的工艺214。因此，下面的金属晶种层51的部分暴露。
参考图8，在不去除金属晶种层51的情况下，在金属晶种层51和镀材料54上形成镀掩模57。镀掩模57具有开口52’。相应的工艺示为图22所示的工艺流程200中的工艺216。接着，通过可以是例如电化学镀工艺或化学镀工艺的镀工艺形成导电凸块60。相应的工艺示为图22所示的工艺流程200中的工艺218。整个导电凸块60可以由诸如铜或铜合金的均质材料形成。导电凸块60和下面的镀材料54之间可以具有可区分的界面，或者导电凸块60和下面的镀材料54可以彼此合并(例如，当两者均由铜形成时)，而在两者之间没有可区分的界面。导电凸块60由于他们的形状也称为金属柱或金属棒。例如，图21示出了具有圆形的顶视图形状的示例性导电凸块60，同时，取决于开口52’的顶视图形状，也可以采用诸如六边形、八边形等的其他形状。
图9还示出了根据一些实施例的也通过镀沉积的焊料区域62的沉积。焊料区域62可以由AgSn、AgSnCu、SnPb等形成或包括AgSn、AgSnCu、SnPb等。根据可选的实施例，不形成焊料区域62。
在随后的工艺中，例如通过灰化去除镀掩模57。相应的工艺示为图22所示的工艺流程200中的工艺220。接着，执行可以是湿蚀刻工艺或干蚀刻工艺的蚀刻工艺以去除金属晶种层51的暴露部分。相应的工艺示为图22所示的工艺流程200中的工艺222。将直接位于镀金属材料54下方的金属晶种层51的部分保留。在整个说明书中，金属材料54和下面的金属晶种层51的剩余部分统称为通孔56(也称为顶部通孔)和导电焊盘58。图10中示出了所得的结构。通孔56是位于介电层46中的部分，同时导电焊盘58是位于介电层46上方的部分。每个通孔56和导电焊盘58可以包括金属晶种层51的剩余部分和镀材料54的部分。导电凸块60直接位于导电焊盘58的上方，并从导电焊盘58的边缘横向凹进。换句话说，导电焊盘58具有比导电凸块60大的顶视图尺寸。
在整个说明书中，位于释放膜22上方的结构称为互连组件64。在随后的工艺中，可以将互连组件64放置在框架(未显示)上，其中，焊料区域62粘附至框架中的带。然后，将互连组件64从载体20剥离，例如，通过将UV光或激光束投射在释放膜22上，从而使得释放膜22在UV光或激光束的热量下分解。相应的工艺示为图22所示的工艺流程200中的工艺224。因此，互连组件64从载体20剥离。所得的互连组件64在图11中示出。在所得结构中，可以暴露介电层24。如果形成焊料区域62，则可以将其回流以具有圆形表面。
进一步参考图11，形成电连接件66以电连接至RDL 26。根据一些实施例，电连接件66是UBM。UBM 66的形成工艺也可以包括：图案化介电层24以形成开口；沉积可以包括钛层和位于钛层上的铜层的金属晶种层；形成并图案化镀掩模；镀导电材料；去除镀掩模，以及蚀刻金属晶种层。根据其他实施例，电连接件66是焊料区域，并且形成工艺可以包括图案化介电层24(例如，通过激光钻孔)以形成开口，将焊料球放置到开口中并且执行回流工艺以回流焊料区域。
在随后的工艺中，在切割工艺中将互连组件64分割开以形成多个相同的互连组件64’(也称为封装组件64’)。可以通过沿着划线68分割互连组件64来执行切割工艺。
互连组件64’可以用于形成封装件。图12示出了包括将互连组件64’接合至封装组件70的示例性结构的部分。根据一些实施例，位于封装组件70的表面上的电连接件72可以通过焊料区域74接合至互连组件64’。焊料区域74可以包括如图11所示的焊料区域62。电连接件72可以是UBM、金属柱、接合焊盘等。根据可选的实施例，电连接件72是金属柱，并且通过直接的金属至金属接合而接合至导电凸块60。根据这些实施例，没有形成焊料区域62(图11)，并且导电凸块60通过直接的金属至金属接合而物理地结合至电连接件72。根据一些实施例，将底部填充物76分配至封装组件70和互连组件64’之间的间隙中。底部填充物76接触导电焊盘58的延伸部分的侧壁和顶面，并且延伸部分横向延伸超出上面的导电凸块60的边缘。分配可以由或包括模塑料形成的或包括模塑料的密封剂78。可以执行平坦化工艺以使封装组件70的顶面与密封剂78的顶面齐平。
图13示出了互连组件64’的应用。图12所示的结构也可以是图13所示的结构的部分。将每个互连组件64’接合至一个或多个封装组件70(包括70A和70B作为实例)。诸如偏心接合结构的一些结构的细节在图13没有详细示出，并且参考图11至图12以及图14至图18可以找到这些细节。根据一些实施例，封装组件70包括可以是中央处理器(CPU)管芯、图形处理器(GPU)管芯、移动应用管芯、微控制器(MCU)管芯、输入输出(IO)管芯、基带(BB)管芯、应用处理(AP)管芯等的逻辑管芯。封装组件70也可以包括诸如动态随机存取存储器(DRAM)管芯，静态随机存取存储器(SRAM)管芯等的存储器管芯。存储器管芯可以是分立的存储器管芯，或者可以是包括多个堆叠的存储器管芯的形式的管芯堆叠件。封装组件70也可以包括片上系统(SOC)管芯。
根据一些实施例，封装组件70包括可以是逻辑管芯或SOC管芯的封装组件70A。根据一些实施例，封装组件70A包括半导体衬底71和集成电路器件(未示出，例如包括晶体管)。封装组件70可以还包括可以是存储器管芯或存储器堆叠件的封装组件70B。还示出了底部填充物76和模塑料78。
互连组件64’还接合至封装组件80。根据一些实施例，封装组件80是或包括中介层、封装衬底、印刷电路板等。可以通过焊料区域82来实现接合。将底部填充物84分配在互连组件64’和封装组件80之间。
图14和图15分别示出了根据一些实施例的偏心结构的部分的截面图和顶视图。示出的部分在图12中的区域84A中。根据一些实施例，导电凸块60具有可以是诸如圆柱体的旋转对称的对称结构。例如，图15示出了导电凸块60可以具有圆形的顶视图形状。导电凸块60的中心(线)60C从导电焊盘58的中心(线)58C偏离。根据其他的实施例，导电凸块60可以具有另一对称的顶视图形状，选自包括但不限于也相对于中心线60C对称的六边形、八边形等形状。通孔56从导电焊盘58的中心线58C偏离，并且通孔56和导电凸块60从导电焊盘58的中心58C偏离至相对方向。例如，通孔56在图14和图15中向左偏移，同时，导电凸块60的中心60C向右偏移。另一方面，通孔44V从通孔56偏离。通孔40V、36V和32V可以与通孔44V垂直对准，或者可以从通孔44V偏离。在整个说明书中，由于通孔56和导电凸块60的中心线垂直未对准，将相应的接合结构称为偏心接合结构。
参照图15，导电焊盘58具有在X方向上测量的长度L1。在Y方向上，导电焊盘58具有可以等于或小于长度L1的最大宽度W1。导电焊盘58可以相对于在X方向上延伸并且穿过中心58C的线61对称，并且可以相对于在Y方向上延伸并且穿过中心58C的线61’不对称。例如，在中心58C的左侧上的导电焊盘58的左侧部分可以小于在中心58C的右侧上的右侧部分。例如，可以考虑将导电焊盘58的形状设计为从圆88A(以圆心为中心60C)开始，并且切出割线88B的外侧部分。割线88B彼此不平行。因此，导电焊盘58具有平整的顶面，平整的底面以及在顶面与底面之间的四个侧壁。侧壁中的两个是弧形侧壁，并且另外的两个侧壁是笔直侧壁(对应于割线88B)。弧形侧壁和笔直侧壁交替布置。导电焊盘58的顶视图具有水滴形状。导电焊盘58的边缘也可以具有一些具有圆形的曲线88A的边缘(弯曲的左边缘和弯曲的右边缘)。根据可选的实施例，也可以采用一侧比另一侧宽的其他形状。例如，代替具有笔直的割线88B作为导电焊盘58的边缘，可以将曲线88C用作导电焊盘58的边缘作为实例。
在传统的结构中，导电凸块60和导电焊盘58将是同心的，并且中心线58C与60C在相同的位置，并且通孔56将与中心线60C对准。然而，这产生了问题。例如，导电凸块60、导电焊盘58以及通孔44V、40V和36V由具有比诸如介电层46、42和38、底部填充物76等的周围材料的热膨胀系数(CTE)大得多的CTE值的金属形成。当通孔56、44V(以及可能的通孔40V和36V)也与中心线60C对准时，在所得结构中存在高应力，这可能导致分层和迹线断裂。为了减小应力，如果通孔44V侧向移动(同时通孔56与中心线60C对准)以从导电焊盘58偏离，则所得结构将占据较大的芯片面积。
根据本发明的实施例，通孔56从中心线58C偏离并且在与导电凸块60的偏离方向(向右)相对的方向(向左)偏离。相应的，衰减了从导电凸块60施加至通孔56应力。此外，通孔44V可以从通孔56偏离，从而使得可以进一步减小来自导电凸块60至通孔44V的应力。例如，当温度提高并且导电凸块60施加向下的应力，由于通孔56从导电凸块60偏离，通过导电焊盘58衰减了部分应力。由于RDL线44L的灵活性，在转移至通孔44V之前，进一步衰减了应力。
再次参考图14，根据一些实施例，通孔56从导电焊盘58的中心线58C偏离了间距S1。偏离间距S1可以等于或大于约8.5μm，并且可以在约8.5μm与约20μm之间的范围内。此外，通孔56与导电凸块60至少部分地重叠是期望的。例如，图14示出了通孔56的右侧部分与导电凸块60重叠，同时通孔56的左侧部分延伸超过导电凸块60的左侧边缘。导电凸块60的(至少部分)重叠有利于允许通孔56支撑导电焊盘58和导电凸块60两者，并且接收从导电凸块60传递的部分(但不是全部)力。这也允许RDL线44L吸收足够量的应力。
根据可选的实施例，如图15所示，可以将通孔56稍微向右偏移至如55所示的位置，从而使得整个通孔56与导电凸块60重叠。例如，根据一些实施例，通孔56的左侧边缘可以与导电凸块60的左侧边缘对准(或偏移至右侧)。根据可选的实施例，例如，当在如图15所示的位置55’形成通孔56时，通孔56从导电凸块60完全偏离。
此外，如图14和图15所示，通孔56从中心60C偏离，并且偏离至中心58C的左侧或与中心58C对准。从图15可以认识到，提高导电焊盘58的尺寸至大于导电凸块60的尺寸允许通孔56偏移期望的距离。另一方面，减小导电焊盘58的左侧部分的尺寸可以避免不必要地提高不需要的导电焊盘58的尺寸。
根据一些实施例，通孔56和44V在中心线58C的相对侧，并且通孔56和通孔44V都没有任何部分由中心线58C穿过。从中心线58C朝向相对方向的偏离通孔56和44可以产生通孔56和44V之间的距离的增加，并且RDL线44L的互连通孔56和44V的部分的长度的提高。这也可以提高RDL线44L吸收应力的能力。另一方面，通孔44V可以与导电凸块60完全重叠，从而使得通孔44V将不占用额外的芯片面积(除非需要用于信号重新布线的原因)，因为它占用了导电焊盘58和导电凸块60占用的相同的芯片面积。
根据一些实施例，通孔40V、36V和/或32V与通孔44V垂直对准。根据可选的实施例，通孔40V、36V和/或32V中的每个或全部可以从通孔44V向左或向右横向偏离。
再次参考图15，标记了一些尺寸。根据一些实施例，从顶视图看，中心线60C与通孔56的边缘之间的横向间距S2可以在约4μm和约12μm之间的范围内。导电焊盘58的直径Dia58可以在约30μm和50μm之间的范围内。导电凸块60的直径Dia60可以在约20μm和40μm之间的范围内。导电凸块60与导电焊盘58的右侧边缘之间的间距S3可以在约2μm和约4μm之间的范围内。
图16示出了根据一些实施例的RDL线44L的顶视图。RDL线44L具有长度L2，并且宽度W2和W3小于长度L2。宽度W3是RDL线44L的较窄的中间部分的宽度，并且宽度W3小于在较窄部分的相对侧上的较宽部分的宽度W2。根据一些实施例，宽度W3小于约0.9W2，并且可以在约0.6W2和约0.9W2之间的范围内。RDL线44L的形状有时候可以称为狗骨形。通孔56和44V可以分别与RDL线44L的左侧部分和右侧部分的中心对准。将宽度W3减小为小于宽度W2可以提高RDL线44L的灵活性，并因此提高其吸收应力的能力。
图17和图18分别示出了根据可选的实施例的偏心结构的部分的截面图和顶视图。所示的部分在图12中的区域84B中。这些实施例与图14和图15中所示的实施例相似，除了通孔44V与导电凸块60的中心线60C对准。通孔40V、36V和32V中的每个或全部可以与通孔44V垂直对准或从通孔44V向左或右横向偏离。当通孔56和44V之间的间距已经足够大以提供足够的应力吸收时，例如，当减小接近饱和时，并且间距的进一步提高不会产生应力的显着减小时，可以采用这些实施例。与图14所示的结构相比，在通孔44V(以及通孔40V和36V)向左侧偏移的情况下，可以在芯片面积的右侧提供用于其他的RDL(诸如RDL线44A、40A和36A等)的布线。
图19示出了与图17和图18中所示的结构相应的RDL线44L以及通孔56和44V的顶视图。为了与中心60C对齐，示出了通孔44V可以从RDL线44L的右侧部分的中心向左偏移。
图20和图21示出了在其上执行模拟的两个结构。图20中所示的结构代表具有垂直对准的导电凸块60’、通孔56’、RDL焊盘44L’和通孔44V’的传统的结构。图21中所示的结构代表根据本发明的一些实施例形成的具有导电凸块60、导电焊盘58、通孔56、RDL线44L和通孔44V的结构。通孔56从导电凸块60和导电焊盘58的中心线偏离。通孔44V从通孔56偏离。导电焊盘58具有比较宽的一侧和较窄的另一侧。模拟结果表明，当施加至RDL线40L’(图20)的应力具有1.0标准化量级时，施加至RDL线40L(图21)的应力具有0.87标准化量级，这意味着与传统的结构相比，本发明的实施例具有减小了13％的应力。
在以上提供的示例性实施例中，偏心接合结构形成在增层衬底中。根据可选的实施例，偏心接合结构可以形成在可以包括半导体衬底以及位于半导体衬底中贯通孔的中介层中。例如，当在背侧抛光用于露出贯通孔之后形成用于中介层的RDL时，偏心接合结构可以形成为中介层的RDL结构的部分。根据另一些可选的实施例，偏心接合结构可以形成在衬底上晶圆上芯片(CoWoS)封装件中，其中，偏心接合结构可以形成在晶圆和封装衬底的一个或两个中。根据另一些可选的实施例，偏心接合结构可以形成在扇出型封装件中，其中，偏心接合结构可以形成在扇出型RDL中，该扇出型RDL在器件管芯的模制之后形成的。
在以上示出的实施例中，根据本发明的一些实施例讨论了一些形成三维(3D)封装件的工艺和部件。也可以包括其他的部件和工艺。例如，可以包括测试结构以辅助3D封装或3DIC器件的验证测试。例如，测试结构可以包括形成在再分布层中或衬底上的测试焊盘，以允许使用探针和/或探针卡等来测试3D封装件或3DIC。可以在中间结构以及最终结构上执行验证测试。另外，本文所公开的结构和方法可以与测试方法结合使用，测试方法结合已知良好管芯的中间验证以增加良率并且降低成本。
本发明的实施例具有一些有利的特征。通过形成偏心接合结构和导电凸块，并且导电焊盘具有较窄的一侧和较宽的一侧，以及进一步通过形成偏心通孔，减小了接合结构和周围部件中的应力。应力的减小不会引起制造成本的提高，并且不会引起芯片区域的损失。
根据本发明的一些实施例，方法包括形成第一介电层；形成第一再分布线，第一再分布线包括延伸至第一介电层中的第一通孔和位于第一介电层上方的第一迹线；形成覆盖第一再分布线的第二介电层；图案化第二介电层以形成通孔开口，其中，第一再分布线通过通孔开口露出；在第二介电层中形成第二通孔，以及在第二通孔上方形成接触第二通孔的导电焊盘；以及在导电焊盘上方形成导电凸块，其中，导电焊盘大于导电凸块，并且导电焊盘的第一中心从导电凸块的第二中心偏离，并且其中，第二通孔从所述导电凸块的第二中心偏离更远。在实施例中，第二通孔和导电焊盘通过共同的镀工艺形成。在实施例中，第二通孔、导电焊盘和导电凸块使用相同的金属晶种层形成。在实施例中，方法还包括在导电凸块上方接合封装组件；以及分配底部填充物，其中，底部填充物接触导电凸块的第一侧壁，并且底部填充物还接触导电焊盘的顶面和第二侧壁。在实施例中，第二通孔包括与导电凸块重叠的第一部分和延伸超过导电凸块的相应边缘的第二部分。在实施例中，导电焊盘包括位于导电焊盘的第一中心的相对侧上的第一部分和第二部分，并且其中第一部分比第二部分窄。在一实施例中，第二通孔和导电凸块的第二中心位于导电焊盘的第一中心的相对侧上。在实施例中，第一通孔和第二通孔位于导电焊盘的第一中心的相对侧上。
根据本发明的一些实施例，结构包括第一介电层；延伸至第一介电层中的第一通孔；位于第一介电层上方的导电迹线，其中，导电迹线位于第一通孔上方并结合至第一通孔；覆盖导电迹线的第二介电层；位于第二介电层中的第二通孔；位于第二通孔上方并接触第二通孔的导电焊盘；其中，导电焊盘具有第一中心；以及位于导电焊盘上方并与接触导电焊盘的导电凸块，其中，导电凸块具有第二中心，并且其中，第二通孔和导电凸块的第二中心位于导电焊盘的第一中心的相对侧上。在实施例中，导电凸块具有圆形的顶视图形状，并且导电焊盘在第一方向上延伸超过导电凸块的第一边缘至第一距离，并且在第二方向上延伸超过导电凸块的第二边缘至小于第一距离的第二距离，其中第一方向和第二方向是从第二中心出发的相对的方向。在实施例中，第二通孔具有与导电凸块重叠的第一部分。在实施例中，第二通孔还包括延伸超过导电凸块的边缘的第二部分。在一实施例中，第一通孔与导电凸块的第二中心对准。在实施例中，第一通孔从导电凸块的第二中心偏离。在实施例中，导电迹线具有长度和小于长度的宽度，并且其中导电迹线的中间部分的宽度比导电迹线的位于中间部分的相对侧上的部分的宽度窄。
根据本发明的一些实施例，结构包括多个介电层；位于多个介电层中的多个再分布线，其中，多个再分布线的每个包括通孔和位于通孔上方并接触通孔的迹线，并且将多个再分布线中的一些通孔堆叠以形成通孔堆叠件，并且通孔垂直对准；位于多个再分布线的顶部再分布线中的顶部迹线上方并接触顶部迹线的顶部通孔；位于顶部通孔上方并接触顶部通孔的导电焊盘；以及位于导电焊盘上方并结合至导电焊盘的导电凸块，其中，导电凸块和顶部通孔是偏心的，并且其中，导电焊盘包括延伸超过导电凸块的第一边缘至第一距离的第一部分，以及延伸超过导电凸块的第二边缘至小于第一距离的第二距离的第二部分，其中，第一部分比第二部分窄。在实施例中，第一部分包括两个笔直边缘；以及位于两个笔直边缘之间并且连接至两个笔直边缘的弯曲边缘。在实施例中，顶部通孔和导电凸块朝向导电焊盘的中心的相对方向偏离。在实施例中，顶部通孔与导电凸块部分地重叠。在实施例中，结构还包括与导电凸块的第一侧壁以及导电焊盘的顶面和第二侧壁接触的底部填充物。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体结构的方法，包括：
形成第一介电层；
形成第一再分布线，所述第一再分布线包括延伸至所述第一介电层中的第一通孔和位于所述第一介电层上方的第一迹线；
形成覆盖所述第一再分布线的第二介电层；
图案化所述第二介电层以形成通孔开口，其中，所述第一再分布线通过所述通孔开口露出；
在所述第二介电层中形成第二通孔，并且在所述第二通孔上方形成接触所述第二通孔的导电焊盘；以及
在所述导电焊盘上方形成导电凸块，其中，所述导电焊盘大于所述导电凸块，并且所述导电焊盘的第一中心从所述导电凸块的第二中心偏离，并且其中，所述第二通孔从所述导电凸块的第二中心偏离更远。
2.根据权利要求1所述的方法，其中，所述第二通孔和所述导电焊盘通过共同的镀工艺形成。
3.根据权利要求1所述的方法，其中，所述第二通孔、所述导电焊盘和所述导电凸块使用相同的金属晶种层形成。
4.根据权利要求1所述的方法，还包括：
在所述导电凸块上方接合封装组件；以及
分配底部填充物，其中，所述底部填充物接触所述导电凸块的第一侧壁，并且所述底部填充物还接触所述导电焊盘的顶面和第二侧壁。
5.根据权利要求1所述的方法，其中，所述第二通孔包括与所述导电凸块重叠的第一部分和延伸超过所述导电凸块的相应边缘的第二部分。
6.根据权利要求1所述的方法，其中，所述导电焊盘包括位于所述导电焊盘的所述第一中心的相对侧上的第一部分和第二部分，并且其中，所述第一部分比所述第二部分窄。
7.根据权利要求6所述的方法，其中，所述第二通孔和所述导电凸块的所述第二中心位于所述导电焊盘的所述第一中心的相对侧上。
8.根据权利要求6所述的方法，其中，所述第一通孔和所述第二通孔位于所述导电焊盘的所述第一中心的相对侧上。
9.一种半导体结构，包括：
第一介电层；
第一通孔，延伸至所述第一介电层中；
导电迹线，位于所述第一介电层上方，其中，所述导电迹线位于所述第一通孔上方并结合至所述第一通孔；
第二介电层，覆盖所述导电迹线；
第二通孔，位于所述第二介电层中；
导电焊盘，位于所述第二通孔上方并接触所述第二通孔；其中，所述导电焊盘具有第一中心；以及
导电凸块，位于所述导电焊盘上方并接触所述导电焊盘，其中，所述导电凸块具有第二中心，并且其中，所述第二通孔和所述导电凸块的所述第二中心位于所述导电焊盘的所述第一中心的相对侧上。
10.一种半导体结构，包括：
多个介电层；
多个再分布线，位于所述多个介电层中，其中，所述多个再分布线的每个包括通孔和位于所述通孔上方并接触所述通孔的迹线，并且将所述多个再分布线中的一些通孔堆叠以形成通孔堆叠件，其中，所述通孔垂直对准；
顶部通孔，位于所述多个再分布线的顶部再分布线中的顶部迹线上方并接触所述顶部迹线；
导电焊盘，位于所述顶部通孔上方并接触所述顶部通孔；以及
导电凸块，位于所述导电焊盘上方并结合至所述导电焊盘，其中，所述导电凸块和所述顶部通孔是偏心的，并且其中，所述导电焊盘包括：
第一部分，延伸超过所述导电凸块的第一边缘至第一距离，以及
第二部分，延伸超过所述导电凸块的第二边缘至小于所述第一距离的第二距离，其中，所述第一部分比所述第二部分窄。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220139860A1 (en) * 2020-10-29 2022-05-05 Taiwan Semiconductor Manufacturing Co., Ltd Multi-Bump Connection to Interconnect Structure and Manufacturing Method Thereof
CN116169031A (zh) * 2023-04-24 2023-05-26 长电集成电路(绍兴)有限公司 一种芯片封装结构的制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11462403B2 (en) * 2020-09-04 2022-10-04 Sj Semiconductor (Jiangyin) Corporation Semiconductor structure and method for manufacturing same

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070182004A1 (en) * 2006-02-08 2007-08-09 Rinne Glenn A Methods of Forming Electronic Interconnections Including Compliant Dielectric Layers and Related Devices
CN101211914A (zh) * 2006-12-29 2008-07-02 东部高科股份有限公司 螺旋感应器
US20090278263A1 (en) * 2008-05-09 2009-11-12 Texas Instruments Incorporated Reliability wcsp layouts
US20150123266A1 (en) * 2013-11-06 2015-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-Trace Design for Enlarge Bump-to-Trace Distance
US20160141213A1 (en) * 2014-11-19 2016-05-19 Deca Technologies Inc. Automated optical inspection of unit specific patterning
US20170005054A1 (en) * 2015-06-30 2017-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
US20170250138A1 (en) * 2016-02-26 2017-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US20180233474A1 (en) * 2017-02-13 2018-08-16 Mediatek Inc. Semiconductor package with rigid under bump metallurgy (ubm) stack
CN109671694A (zh) * 2017-10-13 2019-04-23 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
US20190326241A1 (en) * 2013-11-18 2019-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for Forming Post-Passivation Interconnect Structure
CN110660753A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 半导体封装件和方法
US20200135677A1 (en) * 2018-10-31 2020-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-Bump Sidewall Protection
CN111128750A (zh) * 2018-10-31 2020-05-08 台湾积体电路制造股份有限公司 半导体器件及其形成方法

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1146976C (zh) 1997-10-30 2004-04-21 株式会社日产制作所 半导体装置及其制造方法
US7531898B2 (en) * 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
TWI221336B (en) 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
JP4748161B2 (ja) * 2005-07-12 2011-08-17 株式会社村田製作所 多層配線基板及びその製造方法
CN101221914A (zh) * 2007-01-08 2008-07-16 矽品精密工业股份有限公司 具导电凸块的半导体装置及其制法
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
CN102859691B (zh) 2010-04-07 2015-06-10 株式会社岛津制作所 放射线检测器及其制造方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US20120286416A1 (en) 2011-05-11 2012-11-15 Tessera Research Llc Semiconductor chip package assembly and method for making same
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8735273B2 (en) 2011-07-08 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Forming wafer-level chip scale package structures with reduced number of seed layers
US8441131B2 (en) * 2011-09-12 2013-05-14 Globalfoundries Inc. Strain-compensating fill patterns for controlling semiconductor chip package interactions
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
KR101867961B1 (ko) 2012-02-13 2018-06-15 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9202714B2 (en) 2012-04-24 2015-12-01 Micron Technology, Inc. Methods for forming semiconductor device packages
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8710656B2 (en) 2012-07-20 2014-04-29 International Business Machines Corporation Redistribution layer (RDL) with variable offset bumps
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9362236B2 (en) 2013-03-07 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
US9379041B2 (en) 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
TWI554174B (zh) 2014-11-04 2016-10-11 上海兆芯集成電路有限公司 線路基板和半導體封裝結構
US9899248B2 (en) 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
EP3038150B1 (en) 2014-12-23 2020-06-03 IMEC vzw Chip scale package with flexible interconnect
KR20160080965A (ko) * 2014-12-30 2016-07-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9640498B1 (en) 2015-10-20 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (InFO) package structures and methods of forming same
KR101933408B1 (ko) 2015-11-10 2018-12-28 삼성전기 주식회사 전자부품 패키지 및 이를 포함하는 전자기기
US10147682B2 (en) 2015-11-30 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for stacked logic performance improvement
US9812414B1 (en) 2016-06-17 2017-11-07 Nanya Technology Corporation Chip package and a manufacturing method thereof
US10141198B2 (en) 2016-07-08 2018-11-27 Dyi-chung Hu Electronic package and manufacturing method thereof
US9741690B1 (en) 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US10304801B2 (en) 2016-10-31 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US11158619B2 (en) 2016-10-31 2021-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US9773753B1 (en) 2016-11-18 2017-09-26 Advanced Semiconductor Engineering, Inc. Semiconductor devices and methods of manufacturing the same
US10181449B1 (en) 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
US11101209B2 (en) 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
US10157871B1 (en) 2017-10-12 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
US11004812B2 (en) 2018-09-18 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US10790162B2 (en) 2018-09-27 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US20210134750A1 (en) * 2019-10-30 2021-05-06 Texas Instruments Incorporated Conductive members for die attach in flip chip packages
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070182004A1 (en) * 2006-02-08 2007-08-09 Rinne Glenn A Methods of Forming Electronic Interconnections Including Compliant Dielectric Layers and Related Devices
CN101211914A (zh) * 2006-12-29 2008-07-02 东部高科股份有限公司 螺旋感应器
US20090278263A1 (en) * 2008-05-09 2009-11-12 Texas Instruments Incorporated Reliability wcsp layouts
US20150123266A1 (en) * 2013-11-06 2015-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-Trace Design for Enlarge Bump-to-Trace Distance
US20190326241A1 (en) * 2013-11-18 2019-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for Forming Post-Passivation Interconnect Structure
US20160141213A1 (en) * 2014-11-19 2016-05-19 Deca Technologies Inc. Automated optical inspection of unit specific patterning
US20170005054A1 (en) * 2015-06-30 2017-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
US20170250138A1 (en) * 2016-02-26 2017-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US20180233474A1 (en) * 2017-02-13 2018-08-16 Mediatek Inc. Semiconductor package with rigid under bump metallurgy (ubm) stack
CN109671694A (zh) * 2017-10-13 2019-04-23 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
CN110660753A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 半导体封装件和方法
US20200135677A1 (en) * 2018-10-31 2020-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-Bump Sidewall Protection
CN111128750A (zh) * 2018-10-31 2020-05-08 台湾积体电路制造股份有限公司 半导体器件及其形成方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220139860A1 (en) * 2020-10-29 2022-05-05 Taiwan Semiconductor Manufacturing Co., Ltd Multi-Bump Connection to Interconnect Structure and Manufacturing Method Thereof
US11705420B2 (en) * 2020-10-29 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-bump connection to interconnect structure and manufacturing method thereof
CN116169031A (zh) * 2023-04-24 2023-05-26 长电集成电路(绍兴)有限公司 一种芯片封装结构的制备方法

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