CN109671694A - 半导体封装装置及其制造方法 - Google Patents

半导体封装装置及其制造方法 Download PDF

Info

Publication number
CN109671694A
CN109671694A CN201810182192.0A CN201810182192A CN109671694A CN 109671694 A CN109671694 A CN 109671694A CN 201810182192 A CN201810182192 A CN 201810182192A CN 109671694 A CN109671694 A CN 109671694A
Authority
CN
China
Prior art keywords
metal layer
layer
semiconductor encapsulation
encapsulation device
patterned conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810182192.0A
Other languages
English (en)
Other versions
CN109671694B (zh
Inventor
吕文隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN109671694A publication Critical patent/CN109671694A/zh
Application granted granted Critical
Publication of CN109671694B publication Critical patent/CN109671694B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16014—Structure relative to the bonding area, e.g. bond pad the bump connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81469—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种半导体封装装置包含互连结构、电子组件、封装体及电触点。介电层具有顶部表面及底部表面。所述介电层界定从所述底部表面延伸到所述介电层中的空腔。图案化导电层安置在所述介电层的所述顶部表面上。导电垫至少部分地安置在所述空腔内且电连接到所述图案化导电层。所述导电垫包含第一金属层及第二金属层。所述第二金属层安置在所述第一金属层上且沿着所述第一金属层的侧表面延伸。所述电子组件电连接到所述图案化导电层。所述封装体覆盖所述电子组件及所述图案化导电层。所述电触点电连接到所述导电垫。

Description

半导体封装装置及其制造方法
技术领域
本公开大体上涉及一种半导体封装装置及其制造方法，且涉及一种包含焊接垫结构的半导体封装装置及其制造方法。
背景技术
半导体封装装置可包含将电子组件电连接到衬底的焊料球。在相当的半导体封装装置中，焊料球可直接结合到平坦焊料垫。那些焊料垫被称作“防焊剂限定”(solder maskdefined；SMD)型焊料垫。然而，使焊料球与焊料垫之间的连接承受侧向应力而不使焊料球分层可具有挑战性。
为了尝试解决上述问题，可从衬底暴露焊料垫的侧表面，且可将焊料球连接到焊料垫的侧表面及焊料垫的底部表面两者。这种类型的焊料垫被称作“非防焊剂限定”(non-solder mask defined；NSMD)型焊料垫。然而，由于焊料垫的侧表面及底部表面上的非均一阻挡层(例如，阻挡层在侧表面上相对薄且在底部表面上相对厚)，可能会形成不平的金属间化合物(intermetallic compound；IMC)层(例如，IMC层在侧表面上相对厚且在底部表面上相对薄)。IMC的相对厚部分往往可能会破裂。此外，可能会出现有问题的焊接问题，例如形成在垫的侧表面与衬底的介电层之间的间隙及/或在此类间隙中的污染。
此外，一些相当的扇出工艺可包含芯片最末工艺(chip-last process)及芯片优先工艺(chip-first process)。在芯片最末扇出工艺中，将导电线(具有约25/25微米(μm)的线宽及线距(line width and line space；L/S))及导电垫形成在载体的球侧处，且将重布层(redistribution layer；RDL)(具有约2/2μm的L/S)形成在载体的芯片侧处以形成导电图案。接着，实行裸片结合、成型、载体移除及球安装的工艺以形成具有扇出结构的半导体封装装置。尽管IMC可存在于焊料球与导电垫之间，但在一些实施方案中，只要导电垫的厚度大于例如约10μm，那么此类IMC就可能不会显著地影响连接的可靠性。然而，较厚导电垫可增大半导体封装装置的总大小，这可妨碍半导体封装装置的小型化。此外，导电线及RDL都是通过凸块化工艺而制成，这可增大制造成本。
在一些相当的芯片优先扇出工艺中，将芯片放置在载体上，将焊料球及RDL形成在芯片上，通过倒装芯片技术将芯片结合到衬底，且接着形成封装材料以覆盖芯片。然而，芯片优先扇出工艺可具有裸片产率损失问题。为了尝试克服裸片产率损失问题，可使用芯片最末扇出工艺来替换芯片优先扇出工艺。然而，如上文所提到，为了避免IMC问题(其可影响电性能)，导电垫的厚度可大于10μm，这可妨碍半导体封装装置的小型化。因此，需要使用芯片最末扇出工艺来解决上述IMC问题(例如在导电垫的厚度小于例如约5μm的状况下)。
发明内容
在一或多个实施例中，一种半导体封装装置包含互连结构、电子组件、封装体及电触点。介电层具有顶部表面及底部表面。所述介电层界定从所述底部表面延伸到所述介电层中的空腔。图案化导电层安置在所述介电层的所述顶部表面上。导电垫至少部分地安置在所述空腔内且电连接到所述图案化导电层。所述导电垫包含第一金属层及第二金属层。所述第二金属层安置在所述第一金属层上且沿着所述第一金属层的侧表面延伸。所述电子组件电连接到所述图案化导电层。所述封装体覆盖所述电子组件及所述图案化导电层。所述电触点电连接到所述导电垫。
在一或多个实施例中，一种半导体封装装置包含互连结构、电子组件、第一封装体、衬底及电触点。介电层具有顶部表面及底部表面。所述介电层界定从所述底部表面延伸到所述介电层中的空腔。图案化导电层安置在所述介电层的所述顶部表面上。导电垫至少部分地安置在所述空腔内且电连接到所述图案化导电层。所述导电垫包含第一金属层及第二金属层。所述第二金属层安置在所述第一金属层上且沿着所述第一金属层的侧表面延伸。所述电子组件电连接到所述图案化导电层。所述第一封装体覆盖所述电子组件及所述图案化导电层。所述电触点将所述导电垫电连接到所述衬底。
在一或多个实施例中，一种制造半导体封装装置的方法包含：提供载体；在所述载体上形成第一金属层；在所述载体上形成第二金属层以覆盖所述第一金属层；在所述第一金属层及所述第二金属层上形成介电层；及在所述介电层上形成图案化导电层。所述方法进一步包含：提供电子组件，所述电子组件电连接到所述图案化导电层；移除所述载体及所述第二金属层的部分以暴露所述第一金属层的底部表面及所述第一金属层的侧表面的部分；及形成电触点，所述电触点电连接到所述第一金属层的所述底部表面及所述第一金属层的所述侧表面的所述部分。所述第一金属层的厚度大于所述第二金属层的厚度。
附图说明
在与附图一起阅读时从以下详细描述最佳地理解本公开的方面。应注意，各种特征可能未按比例绘制，且各种特征的尺寸可出于论述清楚起见而任意地增大或减小。
图1说明根据本公开的一些实施例的半导体封装装置的横截面图。
图2说明根据本公开的一些实施例的半导体封装装置的横截面图。
图3说明根据本公开的一些实施例的半导体封装装置的横截面图。
图4A说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段。
图4B说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段。
图4C说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段。
图4D说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段。
图4E说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段。
图4F说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段。
图4G说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段。
图4H说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段。
图5A说明根据本公开的一些实施例的半导体封装装置。
图5B说明根据本公开的一些实施例的半导体封装装置。
贯穿图式及详细描述使用共同参考数字来指示相同或相似元件。根据结合附图作出的以下详细描述将容易理解本公开。
具体实施方式
图1说明根据本公开的一些实施例的半导体封装装置1的横截面图。半导体封装装置1包含互连结构10、电子组件11、封装体及电触点13。互连结构10包含介电层100、导电层110(例如图案化导电层110)、通孔100v及导电垫130。
介电层100具有顶部表面1001(也被称作第一表面)及与顶部表面1001相对的底部表面1002(也被称作第二表面)。在一些实施例中，介电层100可包含有机材料、防焊剂、聚酰亚胺(PI)、环氧树脂、味之素(Ajinomoto)累积膜(ABF)、一或多种封装材料、一或多种预浸复合纤维(例如，预浸体纤维)、硼磷硅酸盐玻璃(BPSG)、氧化硅、氮化硅、氮氧化硅、未掺杂硅酸盐玻璃(USG)、其任何组合等等。封装材料的实例可包含但不限于包含分散在其中的填料的环氧树脂。预浸体纤维的实例可包含但不限于通过堆叠或层压一或多种预浸材料或薄片而形成的多层结构。在一些实施例中，介电层100可包含无机材料，例如硅、陶瓷等等。
介电层100界定从底部表面1002延伸到介电层100中的空腔。导电垫130部分地安置在介电层100的空腔内。举例来说，导电垫130的第一部分安置在介电层100内，且导电垫130的第二部分从介电层100的底部表面1002突出。电触点13(例如焊料球或焊料凸块)安置在导电垫130上以提供半导体封装装置1与其它电路或电路板之间的电连接。在一些实施例中，电触点13是可控塌陷芯片连接(controlled collapse chip connection；C4)凸块、球栅格阵列(ball grid array；BGA)或焊盘栅格阵列(land grid array；LGA)。在一些实施例中，电触点13的直径在约0.1毫米(mm)到约0.3mm的范围内。
导电垫130包含金属层130a、金属层130b及金属层130c。在一或多个实施例中，可省略金属层130a、金属层130b及金属层130c中的一者。金属层130c安置在介电层100的空腔的侧壁及底部表面上。举例来说，金属层130c沿着介电层100的空腔的侧壁延伸。举例来说，金属层130c的至少一部分由介电层100环绕。金属层130c界定面向介电层100的底部表面1002的空腔以容纳金属层130b的至少一部分。举例来说，金属层130b安置在金属层130c的空腔的侧壁及底部表面上。举例来说，金属层130b沿着金属层130c的空腔的侧壁延伸。举例来说，金属层130b的至少一部分由金属层130c环绕。金属层130b界定面向介电层100的底部表面1002的空腔以容纳金属层130a的至少一部分。举例来说，金属层130a安置在金属层130b的空腔的侧壁及底部表面上。举例来说，金属层130a的至少一部分由金属层130b环绕。在一些实施例中，金属层130a的部分(例如金属层130a的侧表面的至少一部分)由电触点13覆盖以增大金属层130a与电触点13之间的结合强度。在一些实施例中，金属层130a、130b或130c中的至少一者不沿着介电层100的底部表面1002延伸(例如不覆盖介电层100的底部表面1002)。替代地，根据一些实施例，金属层130a、130b及130c中的一或多者可在介电层100的底部表面1002上及沿着介电层100的底部表面1002延伸。金属层130c可沿着金属层130b的侧表面的至少一部分延伸。金属层130b可沿着金属层130a的侧表面的至少一部分延伸。
在一些实施例中，金属层130c的宽度大于金属层130b的宽度，且金属层130b的宽度大于金属层130a的宽度。举例来说，金属层130a、130b及130c界定阶梯式结构。在一些实施例中，金属层130a及金属层130b从介电层100的底部表面1002突出。在一些实施例中，金属层130c不从介电层100的底部表面1002突出。在一些实施例中，金属层130a包含金(Au)、钯(Pd)、银(Ag)、另一金属或其合金中的至少一者。在一些实施例中，金属层130b包含镍(Ni)、钛钨(TiW)、铝(Al)、另一金属或其合金中的至少一者。在一些实施例中，金属层130c包含铜(Cu)、Au、Ag、Pd、另一金属或其合金中的至少一者。
在一些实施例中，金属层130a的厚度大于金属层130b的厚度。在一些实施例中，金属层130a的厚度与金属层130b的厚度的总和大于金属层130c的厚度。举例来说，金属层130a的厚度在约0.1微米(μm)到约1.5μm的范围内，金属层130b的厚度在约0.1μm到约0.5μm的范围内，且金属层130c的厚度在约0.1μm到约3μm的范围内。在一些实施例中，导电垫130的总厚度(包含金属层130a、130b及130c)在约0.3μm到约5μm的范围内，或小于或等于约5μm。
在一些实施例中，金属层130b被提供为阻挡层(或终止层)以消除或减少电触点13与金属层130c之间的IMC层的形成。此外，导电垫130(例如其界定阶梯式结构)可防止电触点13(例如在电触点13的形成期间)直接接触导电垫130的内层(例如，金属层130c)。
此外，如果将剪应力施加到导电垫130及电触点13，那么在金属层130a与金属层130b之间的界面处可能会首先发生剪切破裂(例如在金属层130b与金属层130c之间的界面处发生剪切破裂之前，或由此防止在金属层130b与金属层130c之间的界面处发生剪切破裂)。此外，因为金属层130a的侧表面的至少一部分由金属层130b覆盖且金属层130b的侧表面的至少一部分由金属层130c覆盖，所以由垂直于介电层100的底部表面1002的方向上的力造成的力矩相对小，这可帮助防止金属层130a、130b及130c分层。
晶种层120安置在介电层100的顶部表面1001上且通过通孔100v而电连接到导电垫130。导电层110安置在晶种层120上。在一些实施例中，导电层110包含Cu、Ag、Au、Pt、Al、另一金属、焊料合金，或其两者或多于两者的组合。在一些实施例中，导电层110的部分可由例如阻焊剂层的保护层(未展示)覆盖。
电子组件11安置在介电层100的顶部表面1001上且电连接到导电层110。电子组件11可包含芯片或裸片，芯片或裸片包含安置在其中的半导体衬底、一或多个集成电路装置及/或一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置，及/或例如电阻器、电容器、电感器的无源装置，或其两者或多于两者的组合。在一些实施例中，电子组件11通过倒装芯片技术而电连接到导电层110。导电层110可具有小于或等于约10μm的L/S。
封装体12安置在介电层11的顶部表面1001上且覆盖电子组件11。在一些实施例中，封装体12包含例如一或多种有机材料(例如，封装材料、双马来酰亚胺三嗪(BT)、PI、聚苯并恶唑(PBO)、阻焊剂、ABF、聚丙烯(PP)、环氧基材料，或其两者或多于两者的组合)、无机材料(例如，硅、玻璃、陶瓷、石英，或其两者或多于两者的组合)、液膜材料或干膜材料，或其两者或多于两者的组合。
图2说明根据本公开的一些实施例的半导体封装装置2的横截面图。半导体封装装置2相似于图1中的半导体封装装置1，但在一些方面上不同。举例来说，代替互连结构10或除了互连结构10之外，互连结构20也包含在半导体封装装置2中。导电垫130进一步包含在半导体封装装置2中。在下文所描述的实施例中，导电垫130被称作与互连结构20分离的组件，但在一些实施例中，导电垫130可包含在互连结构20中。互连结构20包含多个层。
半导体封装装置2包含介电层200a及介电层200b。介电层200a囊封或环绕导电垫130的至少一部分。介电层200a界定暴露导电垫130的金属层130c的部分的空腔(例如在介电层200a的顶部表面处)。晶种层220a安置在介电层200a上且延伸到介电层200a的空腔中以电连接到导电垫130的金属层130c的暴露部分。导电层210a安置在晶种层220a上及介电层200a的空腔内。
介电层200b安置在介电层200a上且覆盖导电层210a。介电层200b界定暴露导电层210a的部分的空腔(例如在介电层200a的顶部表面处)。晶种层220b安置在介电层200b上且延伸到介电层200b的空腔中以电连接到导电层210a的暴露部分。导电层210b安置在晶种层220b上及介电层200b的空腔内。在一些实施例中，导电层210a的线宽及线距(L/S)大于导电层210b的L/S。举例来说，导电层210a的L/S在约5μm到约15μm的范围内，且导电层210b的L/S在约2μm到约5μm的范围内。
图3说明根据本公开的一些实施例的电装置3的横截面图。电装置3包含如图2所展示的半导体封装装置2、衬底30、封装体32及电触点30b。在一些实施例中，电装置3可包含安置在半导体封装装置2与衬底30之间的底部填充料30u，且封装体32囊封半导体封装装置2及底部填充料30u。衬底30可包含或可附接到安置在衬底30a的顶部表面处的导电层(或导电垫)30c(例如图案化导电层30c)，及安置在衬底30的底部表面处的导电层(或导电垫)30c1。电触点30b安置在衬底30的底部表面上的导电层30c1(或导电垫)上以提供电连接。在其它实施例中，取决于设计规范，半导体封装装置2可由如图1所展示的半导体封装装置1替换。
半导体封装装置2安置在衬底30上且电连接到衬底30上的导电层30c(或导电垫)。衬底30可包含例如印刷电路板，例如纸基铜箔层压板、复合铜箔层压板，或聚合物浸渍玻璃纤维基铜箔层压板。衬底30可包含互连结构，例如RDL或接地元件。在一些实施例中，衬底30上的导电层30c的L/S大于或等于约10μm。
封装体32安置在衬底30上且覆盖半导体封装装置2。在一些实施例中，封装体32包含例如一或多种有机材料(例如，封装材料、BT、PI、PBO、阻焊剂、ABF、PP、环氧基材料，或其两者或多于两者的组合)、无机材料(例如，硅、玻璃、陶瓷、石英，或其两者或多于两者的组合)、液膜材料、干膜材料，或其两者或多于两者的组合。
在一些实施例中，半导体封装装置2的电触点13可由底部填充料30u覆盖或囊封，且封装体32安置在衬底30上以覆盖半导体封装装置2及底部填充料30u。在一些实施例中，底部填充料30u包含环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其两者或多于两者的组合。在一些实施例中，取决于不同实施例的规范，底部填充料可以是毛细底部填充料(capillaryunderfill；CUF)、成型底部填充料(molded underfill；MUF)或配制凝胶。
图4A、图4B、图4C、图4D、图4E、图4F、图4G及图4H是根据本公开的一些实施例的在各个阶段制作的半导体结构的横截面图。至少一些图已被简化以更佳地理解本公开的方面。
参看图4A，提供载体49且通过粘着剂(或离型膜)49h将晶种层490附接到载体49。在一些实施例中，晶种层490包含钛及铜合金(Ti/Cu)或其它合适材料。在一些实施例中，晶种层490可通过物理气相沉积(physical vapor deposition；PVD)或其它合适工艺而形成。
参看图4B，将光阻49p形成在晶种层490上。通过例如光刻技术在光阻49中形成一或多个开口以暴露晶种层490的部分。将金属层430a形成在光阻49p的一或多个开口内。在一些实施例中，金属层430a是通过例如电镀而形成。
参看图4C，从晶种层490移除光阻49p，在晶种层490上及在金属层430a上形成金属层430b，且可将金属层430b的部分安置在金属层430a的部分之间。在一些实施例中，金属层430b及晶种层490包含相同材料。金属层430b及晶种层490可包含不同材料。在一些实施例中，金属层430b可通过PVD或其它合适工艺而形成。将金属层430c形成在金属层430b上，且可将金属层430c的部分安置在金属层430a的部分之间。金属层430a的厚度可约等于或大于金属层340b的厚度。第三金属层的厚度可约等于或小于第一金属层的厚度与第二金属层的厚度的总和。
参看图4D，将钝化层(或介电层)400形成在金属层430c上以覆盖金属层430c。在一些实施例中，钝化层400是通过涂布或其它合适工艺而形成。通过例如光刻技术在钝化层400中形成一或多个开口以暴露金属层430c的部分。接着将导电材料400v(例如，构成通孔的至少一部分)形成在钝化层400的开口内以电连接到金属层430c的暴露部分。在一些实施例中，导电材料400v是通过电镀或其它合适工艺而形成。导电材料400v的部分可从钝化层400暴露。
参看图4E，将晶种层420形成在钝化层400上且电连接到导电材料400v的暴露部分。在一些实施例中，晶种层420包含Ti、Cu或其它合适材料。在一些实施例中，晶种层420可通过PVD或其它合适工艺而形成。
参看图4F，将光阻410p形成在晶种层420上。通过例如光刻技术在光阻410p中形成一或多个开口以暴露晶种层420的部分。将导电层410(例如图案化导电层410)形成在光阻410p的开口内。在一些实施例中，导电层410是通过例如电镀而形成。可提供电组件11且将其电连接到导电层410。
参看图4G，移除光阻410p及晶种层420的未由导电层410覆盖的部分。将保护层48形成在钝化层400上以覆盖导电层410。在一些实施例中，保护层48包含一或多种有机材料，且可包含钝化层、防焊剂等等。在一些实施例中，通过层压将保护层48附接到钝化层400。接着移除载体49及粘着剂49h。
参看图4H，移除晶种层490(例如由Ti/Cu合金形成)以暴露金属层430a的部分。在一些实施例中，通过例如蚀刻或其它合适工艺来移除晶种层490的部分。在一些实施例中，可实行两种蚀刻工艺以移除晶种层490，例如一种蚀刻工艺用于移除Ti，且另一蚀刻工艺用于移除Cu。在一些实施例中，移除金属层430b的至少一部分以暴露金属层430a的侧表面的至少一部分。在一些实施例中，移除金属层430c的至少一部分以暴露金属层430b的侧表面的至少一部分。移除保护层48以暴露导电层410及钝化层400的部分。接着将电触点43(例如，凸块或焊料球)形成在金属层430a上以形成如图1所展示的半导体封装装置1的互连结构10。在一些实施例中，电触点43可通过例如电镀、无电镀、溅射、膏印刷、凸块化或结合工艺而形成。
图5A及图5B说明根据本公开的一些实施例的不同类型的半导体封装装置。
如图5A所展示，多个芯片或裸片50放置在正方形载体51上。在一些实施例中，载体51可包含有机材料(例如，封装材料、BT、PI、PBO、阻焊剂、ABF、PP、环氧基材料，或其两者或多于两者的组合)，或无机材料(例如，硅、玻璃、陶瓷、石英，或其两者或多于两者的组合)。
如图5B所展示，多个芯片或裸片50放置在圆形载体52上。在一些实施例中，载体52可包含有机材料(例如，封装材料、BT、PI、PBO、阻焊剂、ABF、PP、环氧基材料，或其两者或多于两者的组合)，或无机材料(例如，硅、玻璃、陶瓷、石英，或其两者或多于两者的组合)。
如本文中所使用，术语“大约”、“基本上”、“基本”及“约”用于描述及考虑小变化。在结合事件或情境而使用时，所述术语可指所述事件或情境精确地发生的实例以及所述事件或情境相当近似地发生的实例。举例来说，在结合数值而使用时，所述术语可指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％，那么所述数值可被认为“基本上”或“约”相同。举例来说，“基本上”平行可指相对于0°的角度变化范围，其小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“基本上”垂直可指相对于90°的角度变化范围，其小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，那么两个表面可被认为共面或基本上共面。
如本文中所使用，术语“导电”、“导电性”及“导电率”是指输送电流的能力。导电性材料通常指示对电流流动几乎不展现对抗的那些材料。导电率的一个度量是西门子/米(S/m)。通常，导电性材料是具有大于大约104S/m的导电率的材料，例如至少105S/m或至少106S/m。材料的导电率有时可随着温度而变化。除非另有指定，否则材料的导电率是在室温下进行测量。
如本文中所使用，除非上下文另有明确规定，否则单数术语“一(a/an)”及“所述”可包含复数指示物。在一些实施例的描述中，一组件提供在另一组件“上”或“上方”可涵盖前一组件直接在后一组件上(例如，物理接触)的状况，以及一或多个介入组件位于前一组件与后一组件之间的状况。
虽然已参考本公开的特定实施例来描述及说明本公开，但这些描述及说明并不限制本公开。所属领域的技术人员可清楚地理解，在不脱离如由所附权利要求书界定的本公开的真实精神及范围的情况下，可进行各种改变且可在实施例内取代等效组件。绘示可能未必按比例绘制。由于制造工艺中的变量等等，本公开中的精巧呈现与实际设备之间可存在差别。本公开可存在未具体地说明的其它实施例。本说明书及图式应被视为说明性的而非限定性的。可进行修改以使特定情形、材料、物质成分、方法或工艺适应于本公开的目标、精神及范围。所有此类修改意欲属于所附权利要求书的范围内。虽然已参考以特定次序而执行的特定操作来描述本文中所公开的方法，但可理解，在不脱离本公开的教示的情况下，可将这些操作组合、细分或重新排序以形成等效方法。因此，除非本文中有特定指示，否则操作的次序及分组并不限制本公开。

Claims (30)

1.一种半导体封装装置，其包括：
互连结构，其包括：
介电层，其具有顶部表面及底部表面，所述介电层界定从所述底部表面延伸到所述介电层中的空腔；
图案化导电层，其安置在所述介电层的所述顶部表面上；
导电垫，其至少部分地安置在所述空腔内且电连接到所述图案化导电层，所述导电垫包括第一金属层及第二金属层，其中所述第二金属层安置在所述第一金属层上且沿着所述第一金属层的侧表面延伸；
电子组件，其电连接到所述图案化导电层；
封装体，其覆盖所述电子组件及所述图案化导电层；及
电触点，其电连接到所述导电垫。
2.根据权利要求1所述的半导体封装装置，其中所述导电垫进一步包括第三金属层，所述第三金属层安置在所述第二金属层上且沿着所述第二金属层的侧表面延伸，而不沿着所述介电层的所述底部表面延伸。
3.根据权利要求2所述的半导体封装装置，其中所述第三金属层的宽度大于所述第二金属层的宽度，且所述第二金属层的所述宽度大于所述第一金属层的宽度。
4.根据权利要求2所述的半导体封装装置，其中所述第三金属层包括铜(Cu)、金(Au)、银(Ag)或钯(Pd)中的至少一者。
5.根据权利要求2所述的半导体封装装置，其中所述第一金属层的厚度与所述第二金属层的厚度的总和大于所述第三金属层的厚度。
6.根据权利要求2所述的半导体封装装置，其中所述第一金属层及所述第二金属层从所述介电层的所述底部表面突出。
7.根据权利要求6所述的半导体封装装置，其中所述第三金属层不从所述介电层的所述底部表面突出。
8.根据权利要求1所述的半导体封装装置，其中所述第一金属层包括Au、Pd或Ag中的至少一者。
9.根据权利要求1所述的半导体封装装置，其中所述第二金属层包括镍(Ni)、Ti、钨(W)或铝(Al)中的至少一者。
10.根据权利要求1所述的半导体封装装置，其中所述导电垫的厚度等于或小于约5微米(μm)。
11.根据权利要求1所述的半导体封装装置，其中所述第一金属层的厚度大于所述第二金属层的厚度。
12.根据权利要求1所述的半导体封装装置，其进一步包括多个图案化导电层，所述多个图案化导电层包含第一图案化导电层及第二图案化导电层，相比于所述第一图案化导电层，所述第二图案化导电层被安置成较远离所述导电垫，其中所述第一图案化导电层的线宽及线距L/S大于所述第二图案化导电层的L/S。
13.根据权利要求12所述的半导体封装装置，其中所述第一图案化导电层的所述L/S在约5μm到约15μm的范围内，且所述第二图案化导电层的所述L/S在约2μm到约5μm的范围内。
14.根据权利要求1所述的半导体封装装置，其中所述电触点是焊料凸块，所述焊料凸块覆盖所述第一金属层的所述侧表面的部分。
15.根据权利要求1所述的半导体封装装置，其中所述电子组件安置在所述介电层的所述顶部表面上。
16.一种半导体封装装置，其包括：
互连结构，其包括：
介电层，其具有顶部表面及底部表面，所述介电层界定从所述底部表面延伸到所述介电层中的空腔；
图案化导电层，其安置在所述介电层的所述顶部表面上；
导电垫，其至少部分地安置在所述空腔内且电连接到所述图案化导电层，所述导电垫包括第一金属层及第二金属层，其中所述第二金属层安置在所述第一金属层上且沿着所述第一金属层的侧表面延伸；
电子组件，其电连接到所述图案化导电层；
第一封装体，其覆盖所述电子组件及所述图案化导电层；
衬底；及
电触点，其将所述导电垫电连接到所述衬底。
17.根据权利要求16所述的半导体封装装置，其中所述衬底包括L/S大于或等于约10μm的图案化导电层。
18.根据权利要求16所述的半导体封装装置，其中所述互连结构的所述图案化导电层的L/S小于或等于约10μm。
19.根据权利要求16所述的半导体封装装置，其中所述电触点是焊料凸块。
20.根据权利要求19所述的半导体封装装置，其中所述焊料凸块的直径在约0.1毫米(mm)到约0.3mm的范围内。
21.根据权利要求16所述的半导体封装装置，其中所述电子组件通过倒装芯片技术而电连接到所述图案化导电层。
22.根据权利要求16所述的半导体封装装置，其进一步包括底部填充料，所述底部填充料安置在所述介电层与所述衬底之间以覆盖所述电触点。
23.根据权利要求16所述的半导体封装装置，其进一步包括第二封装体，所述第二封装体覆盖所述第一封装体、所述互连结构及所述电触点。
24.根据权利要求16所述的半导体封装装置，其中所述导电垫进一步包括第三金属层，所述第三金属层安置在所述第二金属层上且沿着所述第二金属层的侧表面延伸，而不沿着所述介电层的所述底部表面延伸。
25.根据权利要求16所述的半导体封装装置，其中所述导电垫的厚度等于或小于约5μm。
26.根据权利要求16所述的半导体封装装置，其中所述电子组件安置在所述介电层的所述顶部表面上。
27.一种制造半导体封装装置的方法，其包括：
(a)提供载体；
(b)在所述载体上形成第一金属层；
(c)在所述载体上形成第二金属层以覆盖所述第一金属层，使得所述第一金属层的厚度大于所述第二金属层的厚度；
(d)在所述第一金属层及所述第二金属层上形成介电层；
(e)在所述介电层上形成图案化导电层；
(f)提供电子组件，所述电子组件电连接到所述图案化导电层；
(g)移除所述载体及所述第二金属层的部分以暴露所述第一金属层的底部表面及所述第一金属层的侧表面的部分；及
(h)形成电触点，所述电触点电连接到所述第一金属层的所述底部表面及所述第一金属层的所述侧表面的所述部分。
28.根据权利要求27所述的方法，其进一步包括在执行操作(d)之前形成第三金属层以覆盖所述第二金属层。
29.根据权利要求28所述的方法，其中所述第三金属层被形成使得所述第三金属层的厚度小于所述第一金属层的所述厚度与所述第二金属层的所述厚度的总和。
30.根据权利要求28所述的方法，其中所述操作(g)进一步包括移除所述第三金属层的部分以暴露所述第二金属层的侧表面的部分。
CN201810182192.0A 2017-10-13 2018-03-06 半导体封装装置及其制造方法 Active CN109671694B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/783,353 US10515889B2 (en) 2017-10-13 2017-10-13 Semiconductor package device and method of manufacturing the same
US15/783,353 2017-10-13

Publications (2)

Publication Number Publication Date
CN109671694A true CN109671694A (zh) 2019-04-23
CN109671694B CN109671694B (zh) 2023-07-04

Family

ID=66097104

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810182192.0A Active CN109671694B (zh) 2017-10-13 2018-03-06 半导体封装装置及其制造方法

Country Status (2)

Country Link
US (1) US10515889B2 (zh)
CN (1) CN109671694B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109075151B (zh) 2016-04-26 2023-06-27 亚德诺半导体国际无限责任公司 用于组件封装电路的机械配合、和电及热传导的引线框架
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US20210143072A1 (en) * 2019-11-12 2021-05-13 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and methods of manufacturing the same
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
US20220020693A1 (en) * 2020-07-17 2022-01-20 Taiwan Semiconductor Manufacturing Co., Ltd. Eccentric Via Structures for Stress Reduction
US20220037243A1 (en) * 2020-07-31 2022-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method
US11652037B2 (en) * 2020-07-31 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacture
US11515234B2 (en) * 2020-12-03 2022-11-29 Advanced Semiconductor Engineering, Inc. Semiconductor device package including promoters and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113272A1 (en) * 2002-09-10 2004-06-17 William Tze-You Chen [bump and fabricating process thereof]
US20100084763A1 (en) * 2008-10-06 2010-04-08 Wan-Ling Yu Metallic Bump Structure Without Under Bump Metallurgy And Manufacturing Method Thereof
US20150179592A1 (en) * 2013-12-19 2015-06-25 Texas Instruments Incorporated Self-aligned under bump metal
US20170229414A1 (en) * 2014-08-14 2017-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7847399B2 (en) * 2007-12-07 2010-12-07 Texas Instruments Incorporated Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
US7759212B2 (en) * 2007-12-26 2010-07-20 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
JP5147779B2 (ja) 2009-04-16 2013-02-20 新光電気工業株式会社 配線基板の製造方法及び半導体パッケージの製造方法
US9136293B2 (en) * 2012-09-07 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for sensor module
KR101666757B1 (ko) * 2015-07-13 2016-10-24 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9941186B2 (en) * 2016-06-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
US10629519B2 (en) * 2016-11-29 2020-04-21 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113272A1 (en) * 2002-09-10 2004-06-17 William Tze-You Chen [bump and fabricating process thereof]
US20100084763A1 (en) * 2008-10-06 2010-04-08 Wan-Ling Yu Metallic Bump Structure Without Under Bump Metallurgy And Manufacturing Method Thereof
US20150179592A1 (en) * 2013-12-19 2015-06-25 Texas Instruments Incorporated Self-aligned under bump metal
US20170229414A1 (en) * 2014-08-14 2017-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method

Also Published As

Publication number Publication date
US20190115294A1 (en) 2019-04-18
US10515889B2 (en) 2019-12-24
CN109671694B (zh) 2023-07-04

Similar Documents

Publication Publication Date Title
CN109671694A (zh) 半导体封装装置及其制造方法
US8080880B2 (en) Semiconductor device with arrangement of parallel conductor lines being insulated, between and orthogonal to external contact pads
US10079156B2 (en) Semiconductor package including dielectric layers defining via holes extending to component pads
KR102642327B1 (ko) 반도체 디바이스 및 그 제조 방법
KR20190055690A (ko) 반도체 패키지 및 그 형성 방법
KR20190091751A (ko) 반도체 패키지
TW201921529A (zh) 半導體裝置及其製造方法
US20120146231A1 (en) Semiconductor Device and Method of Manufacture Thereof
TWI714120B (zh) 封裝層電感器
CN113948479A (zh) 具有可路由囊封的传导衬底的半导体封装及方法
KR101496996B1 (ko) 반도체 패키지
CN109524378A (zh) 封装结构
CN110459526A (zh) 布线结构、电子装置和其制造方法
KR20200135758A (ko) 반도체 패키지 및 그 형성 방법
CN114361125A (zh) 半导体装置和制造半导体装置的方法
CN109390312A (zh) 半导体封装装置和其制造方法
CN108461406A (zh) 衬底结构、半导体封装结构及其制造方法
CN109560055A (zh) 半导体封装装置及其制造方法
US11062994B2 (en) Semiconductor device package and method of manufacturing the same
US11978687B2 (en) Semiconductor device and method of manufacturing a semiconductor device
US10903151B2 (en) Semiconductor device package and method of manufacturing the same
KR101764144B1 (ko) 재배선층을 이용한 반도체 패키지 제조방법
CN109243999A (zh) 半导体封装装置及其制造方法
CN219917164U (zh) 半导体封装装置
CN110634814A (zh) 半导体封装装置及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant