CN109243999A - 半导体封装装置及其制造方法 - Google Patents

半导体封装装置及其制造方法 Download PDF

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CN109243999A
CN109243999A CN201810113344.1A CN201810113344A CN109243999A CN 109243999 A CN109243999 A CN 109243999A CN 201810113344 A CN201810113344 A CN 201810113344A CN 109243999 A CN109243999 A CN 109243999A
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conductor wire
insulating layer
group
building brick
electronic building
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CN109243999B (zh
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方仁广
吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体装置封装包含：电子组件；第一组导电线，其电连接到所述电子组件；及绝缘层，其环绕所述第一组导电线。所述绝缘层暴露所述第一组所述导电线的部分。所述绝缘层缺少填料。

Description

半导体封装装置及其制造方法
技术领域
本公开大体上涉及一种半导体封装装置及其制造方法。本公开涉及一种包含扇出结构的半导体封装装置及其制造方法。
背景技术
在半导体封装装置中，可通过倒装芯片技术或导线结合技术将一或多个半导体装置附接或安装到衬底。倒装芯片技术(例如其可实施导电柱或插入件以提供半导体装置与衬底之间的电连接)可用于细距半导体装置封装(例如三维产品，例如三维集成电路)中。然而，使用倒装芯片技术的制造工艺可复杂且昂贵。
发明内容
在一个方面中，根据一些实施例，一种半导体装置封装包含：电子组件；第一组导电线，其电连接到所述电子组件；及绝缘层，其环绕所述第一组导电线。所述绝缘层暴露所述第一组所述导电线的部分。所述绝缘层并不包含填料。
在另一方面中，根据一些实施例，一种半导体装置封装包含：电子组件；第一组导电线，其电连接到所述电子组件；绝缘层，其环绕所述第一组导电线；及封装体，其囊封所述绝缘层。所述绝缘层暴露所述第一组所述导电线的部分。所述第一组导电线通过所述绝缘层而与所述封装体分离。
在又一方面中，根据一些实施例，一种制造半导体装置封装的方法包含提供包含多个导电触点的电子组件。所述方法进一步包含由第一导电线连接所述导电触点中的两者。所述方法又进一步包含形成缺少填料的绝缘层以覆盖所述第一导电线。
附图说明
在与附图一起阅读时从以下详细描述最佳地理解本公开的方面。应注意，各种特征可能未按比例绘制，且在图式中，所描绘特征的尺寸可出于论述清楚起见而任意地增大或减小。
图1A说明根据本公开的第一方面的半导体封装装置的一些实施例的横截面图。
图1B说明根据本公开的第一方面的半导体封装装置的一些实施例的横截面图。
图2A说明根据本公开的第二方面的半导体封装装置的一些实施例的横截面图。
图2B说明根据本公开的第二方面的半导体封装装置的一些实施例的横截面图。
图2C说明根据本公开的第二方面的半导体封装装置的一些实施例的横截面图。
图2D说明根据本公开的第二方面的半导体封装装置的一些实施例的横截面图。
图3A、图3B、图3C、图3D、图3E、图3F、图3G及图3H说明根据本公开的一些实施例的制造半导体封装装置的方法。
图4A、图4B及图4C说明根据本公开的一些实施例的制造半导体封装装置的方法。
图5A及图5B说明根据本公开的一些实施例的不同类型的半导体封装装置。
图6说明根据本公开的一些实施例的半导体封装装置的一些实施例的横截面图。
贯穿图式及详细描述使用共同参考数字来指示相同或相似元件。根据结合附图作出的以下详细描述将容易理解本公开。
具体实施方式
图1A说明根据本公开的第一方面的半导体封装装置1A的一些实施例的横截面图。半导体封装装置1A包含电子组件10、绝缘层11、封装体12、互连层13、保护层14及电触点15。
电子组件10具有有源表面101、与有源表面101相对的背表面102(也被称作背侧)，及在有源表面101与背表面102之间延伸的侧表面103。电子组件10可包含芯片或裸片，且可包含半导体衬底、一或多个集成电路装置，及/或其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置，及/或例如电阻器、电容器、电感器或其组合的无源装置。
多个导电线10w1分别电连接到安置在电子组件10的有源表面101上的导电触点10p。导电触点10p可连接到电子组件10内的一或多个重布层(RDL)，或可构成电子组件10内的一或多个重布层(RDL)的部分。在一些实施例中，包含导电触点10p的RDL的线宽/线距L/S等于或小于约2微米(μm)/约2μm。在一些实施例中，导电线10w1中的每一者为相应结合线的部分。导电线10w1从电子组件10的有源表面101向外延伸到保护层14。在一些实施例中，导电线10w1的宽度为约15μm到约25μm。在一些实施例中，导电线10w1包含金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钛(Ti)、钨(W)、镍(Ni)，或其它合适金属或合金。
绝缘层11安置在电子组件10的有源表面101上以覆盖电子组件10的有源表面101及导电线10w1的部分。每一导电线10w1的一个端子从绝缘层11暴露。绝缘层11具有第一表面111、第二表面112，及在第一表面111与第二表面112之间延伸的侧表面113。第二表面112可面对有源表面101，且第一表面111可与第二表面112相对。在一些实施例中，绝缘层11包含：缺少例如纤维或陶瓷粒子的填料的树脂，例如不具有填料的环氧树脂；聚酰亚胺；酚类化合物或材料；其中分散有硅酮的材料；或其组合。由于缺少填料，故所存在的任何填料被包含为不大于绝缘层11的约5重量％的量，例如不大于约3重量％、不大于2重量％，或不大于1重量％。在一些实施例中，绝缘层11包含灌封胶水或其它粘着材料。
绝缘层11及导电线10w1构成细线RDL的至少部分且可提供用于电子组件10的扇出结构。在一些实施例中，可通过使用插入件或铜柱来实现细线RDL。然而，用于制造具有细线结构的插入件或铜柱的成本可昂贵。通过将结合线(例如，导电线10w1)用于细线RDL，可减少制造成本及时间。
封装体12安置在电子组件10的侧表面103及绝缘层11的侧表面113上。在一些实施例中，封装体12包含具有填料的环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、其中分散有硅酮的材料，或其组合。
互连层13(其可包含例如RDL或其它图案化导电层)安置在绝缘层11的第一表面111及封装体12上。互连层13电连接到导电线10w1的暴露部分。互连层13的L/S(例如互连层13的导电垫的L/S)大于包含导电触点10p的RDL的L/S(例如大于导电触点10p的L/S)；举例来说，互连层13的至少两个邻近导电垫之间的间距大于至少两个邻近导电触点10p之间的间距。在一些实施例中，互连层13的L/S大于约7μm/约7μm。
保护层14安置在绝缘层11的第一表面111及封装体12上以覆盖互连层13的部分。保护层14界定暴露互连层13的部分的开口。在一些实施例中，保护层14包含阻焊剂(solderresist)或防焊剂(solder mask)。
电触点15安置在保护层14的开口内且电连接到互连层13的暴露部分。在一些实施例中，电触点15包含可控塌陷芯片连接(Controlled Collapse Chip Connection；C4)凸块、焊料球或焊盘栅格阵列(Land Grid Array；LGA)。
图1B说明根据本公开的第一方面的半导体封装装置1B的一些实施例的横截面图。半导体封装装置1B与图1A所展示的半导体封装装置1A相似，但以下情形除外：导电垫11p安置在绝缘层11的第一表面111上且分别电连接到导电线10w1，且半导体封装装置1B包含在绝缘层11上方延伸且覆盖导电垫11p的封装体12'(其可与封装体12相似且可代替封装体12被实施)，且半导体封装装置1B进一步包含安置在绝缘层11与保护层14之间的额外导电线10w2。
导电线10w2安置在导电垫11p上。导电垫11p构成RDL或其它图案化导电层的至少部分。包含导电垫11p的RDL的L/S大于包含导电触点10p的RDL的L/S(例如导电垫11p的L/S大于导电触点10p的L/S)。在一些实施例中，导电线10w1及10w2包含相同材料。导电线10w1及10w2可包含不同材料。在一些实施例中，互连层13的L/S大于包含导电触点11p的RDL的L/S。
封装体12'安置在电子组件10的侧表面103、绝缘层11的第一表面111及侧表面113上。在一些实施例中，封装体12'包含具有填料的环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、其中分散有硅酮的材料，或其组合。
图2A说明根据本公开的第二方面的半导体封装装置2A的一些实施例的横截面图。半导体封装装置2A包含：电子组件20a、20b；绝缘层21；封装体22；互连层23；保护层24；及电触点25。
电子组件20a具有有源表面20a1、与有源表面20a1相对的背表面20a2(也被称作背侧)，及在有源表面20a1与背表面20a2之间延伸的侧表面20a3。电子组件20a可包含芯片或裸片，且可包含半导体衬底、一或多个集成电路装置，及/或其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置，及/或例如电阻器、电容器、电感器或其组合的无源装置。
多个导电线20w1分别电连接到安置在电子组件20a的有源表面20a1上的导电触点20p。导电触点20p连接到电子组件20a内的RDL，或可构成电子组件20a内的RDL的部分。在一些实施例中，包含导电触点20p的RDL的L/S等于或小于约2μm/约2μm。在一些实施例中，导电线20w1中的每一者为结合线的部分。在一些实施例中，导电线20w1的宽度为约15μm到约25μm。在一些实施例中，导电线20w1包含Au、Ag、Cu、Pt、Ti、W、Ni，或其它合适金属或合金。
绝缘层21安置在电子组件20a的有源表面20a1及侧表面20a3上以覆盖电子组件10的有源表面20a1及侧表面20a3以及导电线20w1的部分。每一导电线20w1的一个端子从绝缘层21暴露。在一些实施例中，绝缘层21包含：缺少填料的树脂，例如不具有填料的环氧树脂；聚酰亚胺；酚类化合物或材料；其中分散有硅酮的材料；或其组合。在一些实施例中，绝缘层21包含灌封胶水。如图2A所展示，绝缘层21可为基本上钟形(例如绝缘层21的邻近于电子组件20a的有源表面或安置在电子组件20a的有源表面上的顶部表面基本上平行于绝缘层的与顶部表面相对的底部表面，且底部表面宽于顶部表面)。在一些实施例中，绝缘层21从底部表面朝向顶部表面渐缩。在其它实施例中，绝缘层21可为基本上圆柱形。举例来说，绝缘层21的顶部表面及侧表面可彼此基本上垂直。
导电垫21p安置在绝缘层21上且电连接到导电线20w1的暴露部分，且多个导电线20w2分别安置在导电垫21p上。导电线20w2中的一或多者(例如，导电线20w3)电连接到电子组件20b的有源表面20b1。导电线20w2的宽度大于导电线20w1的宽度。在一些实施例中，导电线20w1及20w2包含相同材料。导电线20w1及20w2可包含不同材料。在一些实施例中，导电线20w1的宽度不同于导电线20w3的宽度。举例来说，如果电子组件20b为高功率电子组件(例如，功率裸片)，那么可有利的是将连接到电子组件20b的导电线20w3的宽度(例如，在约20μm到约75μm的范围内的宽度)设置为大于导电线20w1的宽度。
绝缘层21及导电线20w1构成细线RDL，细线RDL可提供用于电子组件20a的扇出结构。在一些实施例中，可通过使用插入件或铜柱来实现细线RDL。然而，用于制造具有细线结构的插入件或铜柱的成本可昂贵。通过将结合线(例如，导电线20w1)用于细线RDL，可减少制造成本及时间。
封装体22经安置以覆盖绝缘层21、电子组件20b及导电线20w2、20w3的部分的外部表面。至少一些导电线20w2的一个端子从封装体22暴露。在一些实施例中，封装体22包含具有填料的环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、其中分散有硅酮的材料，或其组合。在一些实施例中，封装体22及绝缘层21包含相同材料。
互连层23(其可包含例如RDL)安置在封装体22上。互连层23电连接到导电线20w2的暴露部分。互连层23的L/S(例如互连层23的导电垫的L/S)大于包含导电垫21p的RDL的L/S，且大于包含导电触点20p的RDL的L/S。在一些实施例中，互连层23的L/S大于约7μm/约7μm。
保护层24安置在封装体22上以覆盖互连层23的部分。保护层24界定暴露互连层23的部分的开口。在一些实施例中，保护层24包含阻焊剂或防焊剂。
电触点25安置在保护层24的开口内且电连接到互连层23的暴露部分。在一些实施例中，电触点25包含C4凸块、焊料球或LGA。
图2B说明根据本公开的第二方面的半导体封装装置2B的一些实施例的横截面图。半导体封装装置2B与图2A所展示的半导体封装装置2A相似，但半导体封装装置2B进一步包含安置在封装体22与保护层24之间的RDL 26除外。
RDL 26包含互连层26r及介电层26d。互连层26r安置在封装体22上且电连接到导电线20w2的暴露部分。互连层26r的L/S大于包含导电垫21p的RDL的L/S。
介电层26d安置在封装体22上且覆盖互连层26r。在一些实施例中，介电层26d包含与绝缘层21、封装体22或保护层24相同的材料。介电层26d可包含不同材料。在一些实施例中，取决于设计规范，可在封装体22与保护层24之间安置任何数目个RDL。
图2C说明根据本公开的第二方面的半导体封装装置2C的一些实施例的横截面图。半导体封装装置2C与图2A所展示的半导体封装装置2A相似，但半导体封装装置2C进一步包含安置在导电线20w1及20w2之间的RDL 27除外。
RDL 27包含导电线27w1、27w2及封装体27p。导电线27w安置在导电垫21p上，导电垫21p安置在绝缘层21上且电连接到导电线20w1的暴露部分。导电线27中的一或多者(例如，导电线27w2)电连接到电子组件20b的有源表面20b1。导电垫(导电线27w1、27w2在封装体27p的上部表面上附接到导电垫)的L/S大于包含导电垫21p的RDL的L/S。在一些实施例中，导电线27w1、27w2及20w1包含相同材料。导电线27w1、27w2及20w1可包含不同材料。
封装体27p安置在绝缘层21上且覆盖导电线27w1、27w2的部分。至少一些导电线27w1的一个端子从封装体27p暴露。在一些实施例中，封装体27p及封装体22或绝缘层21包含相同材料。封装体27p及封装体22或绝缘层21可包含不同材料。在一些实施例中，取决于设计规范，可在导电线20w1及20w2之间安置任何数目个RDL。
图2D说明根据本公开的第二方面的半导体封装装置2D的一些实施例的横截面图。半导体封装装置2D与图2C所展示的半导体封装装置2C相似，但半导体封装装置2D包含绝缘层21'(其可与绝缘层21相似且可代替绝缘层21被实施)除外。根据俯视图，半导体封装装置2D的绝缘层21'呈基本上正方形或基本上矩形形状，及/或具有基本上垂直于顶部表面的侧表面。半导体封装装置2D进一步包含安置在绝缘层21'与保护层24之间的封装体28。在一些实施例中，封装体28的侧表面与绝缘层21'的侧表面基本上共面。
图3A、图3B、图3C、图3D、图3E、图3F、图3G及图3H为根据制造本公开的半导体封装装置的方法的一些实施例在各种制作阶段的半导体结构的横截面图。各种图已被简化以更清楚地呈现本公开的方面。
参看图3A，提供安置有粘着剂39a(例如，胶带)的载体39。经由粘着剂39a将电子组件30附接到载体39，粘着剂39a可帮助促进后续工艺。电子组件30具有安置有电触点30p1及30p2的有源表面301、与有源表面301相对的背表面302(也被称作背侧)，及在有源表面301与背表面302之间延伸的侧表面303。将电子组件30的背表面302附接到载体39。
接着形成或安置导电线30w1以将电子组件30的有源表面301上的一个电触点电连接到另一电触点。举例来说，导电线30w1将电触点30p1电连接到电触点30p2。在一些实施例中，导电线30w1可通过球形导线结合、楔形导线结合或其它合适工艺而形成。在一些实施例中，包含电触点30p1、30p2的RDL的L/S小于或等于约2μm/约2μm。在一些实施例中，导电线30w1包含Au、Ag、Cu、Pt、Ti、W、Ni，或其它合适金属或合金。
参看图3B，将绝缘层31形成在载体39上以覆盖电子组件30及导电线30w1。在一些实施例中，绝缘层31包含不具有填料的环氧树脂、聚酰亚胺、酚类化合物或材料、其中分散有硅酮的材料，或其组合。在一些实施例中，绝缘层31是通过灌封工艺而形成，灌封工艺可帮助避免由后续成型工艺造成的导线拂掠/移位(其可不利地影响半导体装置封装的性能)或导线接触(其可造成导线的短路或损害)的问题。在一些实施例中，绝缘层31是通过应用缺少填料的绝缘材料且接着将绝缘材料固化而形成。
参看图3C，移除绝缘层31及导电线30w1的部分以暴露导电线的剩余部分，剩余部分包含导电线30w11、30w12。举例来说，在图3C所展示的操作之后，将图3B所展示的导电线30w1划分成如图3C所展示的导电线30w11及30w12。所划分的导电线30w11、30w12中的每一者的一个端子从绝缘层31暴露。在一些实施例中，可通过研磨或其它合适工艺来移除绝缘层31及导电线30w1。
参看图3D，将图案化导电层31p形成在绝缘层31上以电接触导电线30w11、30w12的暴露部分。在一些实施例中，图案化导电层31p可通过包含以下操作的工艺而形成：(i)在绝缘层31上形成光阻或掩模；(ii)通过例如光刻技术在光阻或掩模上界定预定图案；(iii)镀覆导电材料以形成图案化导电层31p；及(iv)移除光阻或掩模。
参看图3E，形成导电线30w2以将图案化导电层31p的一个导电垫电连接到图案化导电层31p的另一导电垫。在一些实施例中，导电线30w2可通过球形导线结合、楔形导线结合或其它合适工艺而形成。导电线30w1及30w2可通过相同或不同工艺而形成。在一些实施例中，导电线30w2的宽度大于导电线30w1的宽度。在一些实施例中，导电线30w2包含Au、Ag、Cu、Pt、Ti、W、Ni，或其它合适金属或合金。
经由粘着剂39a将电子组件30a附接到载体39。电子组件30a具有有源表面30a1、与有源表面30a1相对的背表面30a2(也被称作背侧)。将电子组件30a的背表面30a2附接到载体39。将导电线30w2中的一或多者(例如，导电线30w3)电连接到电子组件30a的有源表面30a1。
接着形成封装体32以覆盖绝缘层31、电子组件30a及导电线30w2、30w3的外部表面。在一些实施例中，封装体32包含具有填料的环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、其中分散有硅酮的材料，或其组合。在一些实施例中，封装体32及绝缘层31包含相同材料。
参看图3F，移除封装体32及导电线30w2、30w3的部分以暴露导电线的剩余部分，剩余部分包含导电线30w21、30w31。举例来说，在图3E所展示的操作之后，将图3E所展示的导电线30w2划分成如图3F所展示的导电线30w21及30w22。相似地，将图3E所展示的导电线30w3划分成如图3F所展示的导电线30w31及30w32。所划分的导电线30w21、30w22、30w31及30w32中的每一者的一个端子从封装体32暴露。在一些实施例中，可通过研磨或其它合适工艺来移除封装体32及导电线30w2、30w3。
参看图3G，将图案化导电层33形成在封装体32上以电接触导电线30w21、30w22、30w31及30w32的暴露部分。在一些实施例中，图案化导电层33可通过包含以下操作的工艺而形成：(i)在封装体32上形成光阻或掩模；(ii)通过例如光刻技术在光阻或掩模上界定预定图案；(iii)镀覆导电材料以形成图案化导电层33；及(iv)移除光阻或掩模。图案化导电层33的L/S(例如图案化导电层33的导电垫的L/S)大于以下RDL中的至少一者的L/S：(i)包含电触点30p1、30p2的RDL；及(ii)包含图案化导电层31p的RDL。在一些实施例中，图案化导电层33的L/S大于约7μm/约7μm。接着，从封装体32移除载体39及粘着剂39a。
参看图3H，将保护层34形成在封装体32上以覆盖图案化导电层33。将多个开口形成在保护层34中以暴露图案化导电层33的部分。在一些实施例中，保护层34为阻焊剂或防焊剂。
接着将电触点35形成在保护层34的开口内且电连接到互连层33的暴露部分。在一些实施例中，电触点35包含C4凸块、焊料球或LGA。
图4A、4B及4C为根据制造本公开的半导体封装装置的方法的一些实施例在各种制作阶段的半导体结构的横截面图。各种图已被简化以更清楚地呈现本公开的方面。
参看图4A，提供安置有粘着剂49a(例如，胶带)的载体49，且经由粘着剂49a将裸片条(例如，晶片)40s附接到载体49。裸片条40s具有安置有电触点(例如电触点40p1及电触点40p2)的有源表面40s1，及与有源表面40s1相对的背表面40s2(也被称作背侧)。裸片条的每一裸片可包含半导体衬底、一或多个集成电路装置，及/或其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的一或多个有源装置，及/或例如电阻器、电容器、电感器或其组合的无源装置。
形成导电线40w以将裸片条40s的有源表面40s1上的一个电触点电连接到另一电触点。举例来说，导电线40w将电触点40p1电连接到电触点40p2。在一些实施例中，导电线40w可通过球形导线结合、楔形导线结合或其它合适工艺而形成。在一些实施例中，连接到电触点40p1、40p2的RDL的L/S小于或等于约2μm/约2μm。在一些实施例中，导电线40w包含Au、Ag、Cu、Pt、Ti、W、Ni，或其它合适金属或合金。
形成绝缘层41以覆盖裸片条40s的有源表面40s1。在一些实施例中，绝缘层41包含不具有填料的环氧树脂、聚酰亚胺、酚类化合物或材料、其中分散有硅酮的材料，或其组合。在一些实施例中，绝缘层41是通过灌封工艺而形成，灌封工艺可帮助避免由后续成型工艺造成的导线拂掠/移位(其可不利地影响半导体装置封装的性能)或导线接触(其可造成导线的短路或损害)的问题。
参看图4B，移除绝缘层41及导电线40w的部分以暴露导电线的剩余部分，剩余部分包含导电线40w1、40w2。举例来说，在图4B所展示的操作之后，将图4A所展示的导电线40w划分成如图4B所展示的导电线40w1及40w2。所划分的导电线40w1及40w2中的每一者的一个端子从绝缘层41暴露。在一些实施例中，可通过研磨或其它合适工艺来移除绝缘层41及导电线40w。
参看图4C，执行单切工艺以分离出个别半导体封装装置。也就是说，通过绝缘层41及裸片条40s执行单切工艺。举例来说，可通过使用划片机、激光或其它适当切割技术实行单切工艺。
图5A及图5B说明根据本公开的一些实施例的不同类型的半导体封装装置。
如图5A所展示，多个芯片50或裸片放置在基本上正方形载体51(例如根据本文中所描述的一或多个实施例)上。在一些实施例中，载体51可包含有机材料(例如，封装材料、双马来酰亚胺三嗪(BT)、聚酰亚胺(PI)、聚苯并恶唑(PBO)、阻焊剂、味之素(Ajinomoto)累积膜(ABF)、聚丙烯(PP)或环氧基材料)，及/或无机材料(例如，硅、玻璃、陶瓷或石英)。
如图5B所展示，多个芯片50或裸片放置在基本上圆形载体52(例如根据本文中所描述的一或多个实施例)上。在一些实施例中，载体52可包含有机材料(例如，封装材料、BT、PI、PBO、阻焊剂、ABF、PP或环氧基材料)，及/或无机材料(例如，硅、玻璃、陶瓷或石英)。
图6说明根据本公开的一些实施例的半导体封装装置6。半导体封装装置6包含：裸片60；导电线60w1、60w2；及绝缘层61，其覆盖裸片60及导电线60w1、60w2。
绝缘层61的高度(例如最大高度)被称作“h”，绝缘层61的宽度(例如最大宽度)被称作“D”，两个导电线60w1及60w2之间的距离(例如导电线60w1连接到衬底上的垫的点与导电线60w2连接到衬底上的垫的点之间的距离)被称作“d”，且绝缘层61的半径被称作“R”。根据力守恒定律，可根据以下方程式计算h，其中S为张力，ρ为绝缘层61的密度：
根据图6所展示的配置，因此，可如下导出h的范围：
以上方程式及不等式展示用于形成绝缘层61的一些可能的设计规范。举例来说，以上设计规范适用于图3B所展示的操作。
如本文中所使用，术语“大约”、“基本上”、“基本”及“约”用于描述及考虑小变化。在结合事件或情境而使用时，所述术语可指所述事件或情境精确地发生的实例以及所述事件或情境相当近似地发生的实例。举例来说，在结合数值而使用时，所述术语可指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％，那么所述值可被认为“基本上”或“约”相同。举例来说，“基本上”平行可指相对于0°的角度变化范围，其小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“基本上”垂直可指相对于90°的角度变化范围，其小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，那么两个表面可被认为共面或基本上共面。
如本文中所使用，术语“导电”、“导电性”及“导电率”是指输送电流的能力。导电性材料通常指示对电流流动几乎不展现对抗的那些材料。导电率的一个度量为西门子/米(S/m)。通常，导电性材料为具有大于大约104S/m的导电率的材料，例如至少105S/m或至少106S/m。材料的导电率有时可随着温度而变化。除非另有指定，否则材料的导电率是在室温下进行测量。
如本文中所使用，除非上下文另有明确规定，否则单数术语“一(a/an)”及“所述”可包含复数指示物。在一些实施例的描述中，一组件提供在另一组件“上”或“上方”可涵盖前一组件直接在后一组件上(例如，物理接触)的状况，以及一或多个介入组件位于前一组件与后一组件之间的状况。
虽然已参考本公开的特定实施例来描述及说明本公开，但这些描述及说明并不限制本公开。所属领域的技术人员可清楚地理解，在不脱离如由所附权利要求书界定的本公开的真实精神及范围的情况下，可进行各种改变且可在实施例内取代等效组件。绘示可能未必按比例绘制。由于制造工艺中的变量等等，本公开中的精巧呈现与实际设备之间可存在差别。本公开可存在未具体地说明的其它实施例。本说明书及图式应被视为说明性的而非限定性的。可进行修改以使特定情形、材料、物质成分、方法或工艺适应于本公开的目标、精神及范围。所有此类修改意欲属于所附权利要求书的范围内。虽然已参考以特定次序而执行的特定操作来描述本文中所公开的方法，但可理解，在不脱离本公开的教示的情况下，可将这些操作组合、细分或重新排序以形成等效方法。因此，除非本文中有特定指示，否则操作的次序及分组并不限制本公开。

Claims (22)

1.一种半导体装置封装，其包括：
电子组件；
第一组导电线，其电连接到所述电子组件；及
绝缘层，其环绕所述第一组导电线且暴露所述第一组所述导电线的部分，
其中所述绝缘层缺少填料。
2.根据权利要求1所述的半导体装置封装，其进一步包括囊封所述电子组件及所述绝缘层的囊封物。
3.根据权利要求1所述的半导体装置封装，其进一步包括安置在所述绝缘层上方且包含多个导电垫的第一图案化导电层，其中所述第一图案化导电层的所述导电垫分别电连接到所述第一组导电线的所述暴露部分。
4.根据权利要求3所述的半导体装置封装，其中
所述电子组件包括电连接到所述第一组所述导电线的多个导电触点；且
所述电子组件的至少两个邻近导电触点之间的间距小于所述第一图案化导电层的至少两个邻近导电垫之间的间距。
5.根据权利要求1所述的半导体装置封装，其进一步包括安置在所述绝缘层上且电连接到所述第一组所述导电线的所述暴露部分的第二组导电线。
6.根据权利要求5所述的半导体装置封装，其进一步包括覆盖所述电子组件、所述绝缘层及所述第二组导电线的囊封物。
7.根据权利要求5所述的半导体装置封装，其中所述第二组导电线中的至少一者的宽度大于所述第一组导电线中的至少一者的宽度。
8.根据权利要求1所述的半导体装置封装，其中
所述绝缘层具有邻近于所述电子组件的有源侧的第一表面及邻近于所述电子组件的背侧的第二表面；且
所述第一表面的宽度小于所述第二表面的宽度。
9.一种半导体装置封装，其包括：
电子组件；
第一组导电线，其电连接到所述电子组件；
绝缘层，其环绕所述第一组导电线且暴露所述第一组所述导电线的部分；及
封装体，其囊封所述绝缘层，
其中所述第一组导电线通过所述绝缘层而与所述封装体分离。
10.根据权利要求9所述的半导体装置封装，其中所述绝缘层缺少填料。
11.根据权利要求9所述的半导体装置封装，其进一步包括安置在所述绝缘层上方且包含多个导电垫的第一图案化导电层，其中所述第一图案化导电层的所述导电垫电连接到所述第一组导电线的所述暴露部分。
12.根据权利要求11所述的半导体装置封装，其中
所述电子组件包括电连接到所述第一组所述导电线的多个导电触点；且
所述电子组件的至少两个邻近导电触点之间的间距小于所述第一图案化导电层的至少两个邻近导电垫之间的间距。
13.根据权利要求9所述的半导体装置封装，其进一步包括安置在所述绝缘层上且电连接到所述第一组所述导电线的所述暴露部分的第二组导电线。
14.根据权利要求13所述的半导体装置封装，其中所述封装体覆盖所述电子组件、所述绝缘层及所述第二组导电线。
15.根据权利要求13所述的半导体装置封装，其中所述第二组导电线中的至少一者的宽度大于所述第一组导电线中的至少一者的宽度。
16.根据权利要求9所述的半导体装置封装，其中
所述绝缘层具有邻近于所述电子组件的有源侧的第一表面及邻近于所述电子组件的背侧的第二表面；且
所述绝缘层从所述第二表面朝向所述第一表面渐缩。
17.一种制造半导体装置封装的方法，其包括：
(a)提供包含多个导电触点的电子组件；
(b)由第一导电线连接所述导电触点中的两者；及
(c)形成缺少填料的绝缘层以覆盖所述第一导电线。
18.根据权利要求17所述的方法，其中操作(c)进一步包括：
应用缺少填料的绝缘材料以覆盖所述第一导电线；及
将所述绝缘材料固化以形成所述绝缘层。
19.根据权利要求17所述的方法，其进一步包括：
移除所述绝缘层的部分及所述第一导电线的部分以暴露所述第一导电线的部分；
及
形成安置在所述绝缘层上的包含多个导电垫的第一图案化导电层，其中所述导电垫中的一者电接触所述第一导电线的所述暴露部分。
20.根据权利要求19所述的方法，其中所述电子组件的所述导电触点的间距小于所述第一图案化导电层的所述导电垫的间距。
21.根据权利要求19所述的方法，其进一步包括：
由第二导电线连接所述第一图案化导电层的所述导电垫中的两者；及
形成囊封所述第二导电线的封装体。
22.根据权利要求21所述的方法，其进一步包括：
移除所述封装体的部分及所述第二导电线的部分以暴露所述第二导电线的部分；
及
形成安置在所述封装体上的包含多个导电垫的第二图案化导电层，其中所述第二图案化导电层的所述导电垫中的一者电接触所述第二导电线的所述暴露部分。
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