TWI717563B - 半導體裝置封裝 - Google Patents
半導體裝置封裝 Download PDFInfo
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- TWI717563B TWI717563B TW106136092A TW106136092A TWI717563B TW I717563 B TWI717563 B TW I717563B TW 106136092 A TW106136092 A TW 106136092A TW 106136092 A TW106136092 A TW 106136092A TW I717563 B TWI717563 B TW I717563B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 239000000463 material Substances 0.000 claims description 16
- 238000000465 moulding Methods 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 6
- 230000006698 induction Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 145
- 238000004519 manufacturing process Methods 0.000 description 26
- 239000000758 substrate Substances 0.000 description 14
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- 238000009413 insulation Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
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- 239000004020 conductor Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
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- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Abstract
本發明揭示一種半導體裝置封裝,其包括一介電層、一第一RDL、一第二RDL、一電感器、一第一電子組件及一第二電子組件。該第一RDL鄰近於該介電層之第一表面,且該第一RDL包括第一導電零件。該第二RDL鄰近於該介電層之一第二表面,且該第二RDL包括第二導電零件。該電感器安置於該介電層中。該電感器包括一感應柱,其中穿過該介電層安置感應柱中之每一者,且感應柱中之每一者在第一RDL之第一導電零件中之各別一者與第二RDL之第二導電零件中之各別一者之間互連。第一電子組件及第二電子組件在第一RDL與第二RDL之間,並且經由電感器電連接至彼此。
Description
本發明係關於半導體裝置封裝,且更特定言之,係關於具有減小之實體大小及厚度之半導體裝置封裝。
由於多種電子組件之整合密度之連續改良,半導體行業經歷了快速增長。由於對小型化、更高速度及更低功率消耗之需求之連續地增長,已經開發了堆疊裝置封裝(例如,三維(3D)裝置封裝)作為進一步減少裝置封裝之實體大小之方式。在堆疊裝置封裝中,主動組件(例如,邏輯電路、記憶體、處理器電路等等)及被動組件(例如,電容器、電感器、電阻器等等)係在單獨之半導體晶圓上製造之。主動組件及被動組件安裝在彼此之頂部上以進一步減少裝置封裝之橫向形狀因數。堆疊結構可以減少封裝裝置之面積,但封裝裝置之總體厚度及大小可能以另外之方式增大。
在一些實施例中,半導體裝置封裝包括介電層、第一RDL、第二RDL、電感器、第一電子組件及第二電子組件。介電層包括第一表面及與第一表面相對之第二表面。第一RDL鄰近於介電層之第一表面,並且第一RDL包括複數個第一導電零件。第二RDL鄰近於介電層之第二表面,並且第二RDL包括複數個第二導電零件。電感器安置於介電層中。電感器包括複數個感應柱,其中穿過介電層安置感應柱中之每一者,並且感應柱中之每一者在第一RDL之第一導電零件中之各別一者與第二RDL之第二導電零件中之各別一者之間互連。第一電子組件及第二電子組件在第一RDL與第二RDL之間,並且經由電感器電連接至彼此。 在一些實施例中,半導體裝置封裝包括介電層、第一電子組件、第二電子組件及電感器。介電層包括第一表面及與第一表面相對之第二表面。第一電子組件及第二電子組件安置於介電層中。電感器安置於介電層中,並且電連接至第一電子組件及第二電子組件。電感器包括實質上垂直於介電層之第一表面或第二表面之至少一個核心區。 在一些實施例中,半導體裝置封裝包括介電層、電感器、複數個導電零件及導線。介電層包括第一表面及與第一表面相對之第二表面。電感器在介電層中,並且電感器包括穿過介電層之複數個感應柱。導電零件安置在介電層之第一表面及第二表面上方,並且電連接至感應柱之一部分。導線電連接至感應柱中之至少一個,且經組態以調節電感器之阻抗。
貫穿圖式及具體實施方式使用共參考標號來指示相同或類似組件。本發明之實施例將容易從結合附圖進行之以下詳細描述中理解。 以下揭示內容提供用於實施所提供之主題之不同特徵之許多不同實施例或實例。下文描述組件及佈置之具體實例以解釋本發明之某些態樣。當然,該等組件及佈置僅為實例且並不意欲為限制性的。舉例而言,在以下描述中,第一特徵在第二特徵上方或第二特徵上之形成可包括第一特徵及第二特徵直接接觸地形成或安置之實施例,並且還可包括額外特徵可在第一特徵與第二特徵之間形成或安置使得第一特徵及第二特徵可不直接接觸之實施例。此外,本發明可在各種實例中重複參考標號及/或字母。此重複係出於簡單及清楚之目的,且本身並不指示所論述之各種實施例及/或組態之間的關係。 除非另外說明,否則例如「上方」、「下方」、「上」、「左」、「右」、「下」、「頂部」、「底部」、「垂直」、「水平」、「側面」、「高於」、「低於」、「上部」、「在……上」、「在……下」等等之空間描述係相對於圖中所示之定向來指示的。應理解,本文中所使用之空間描述僅係出於說明之目的,且本文中所描述之結構之實際實施可以任何定向或方式在空間上佈置,其限制條件為本發明之實施例之優點不因此佈置而有偏差。 本發明之至少一些實施例係關於半導體裝置封裝。在一些實施例中,半導體裝置封裝包括插入於兩個重佈層(RDL)之間的介電層、電感器以及兩個或多於兩個電子組件。電感器包括穿透穿過介電層之感應柱。兩個或多於兩個電子組件安置於介電層中並且經由電感器電連接至彼此。在一些實施例中,電感器包括至少一個實質上垂直於表面(例如,介電層之頂部表面或底部表面)之核心區。在一些實施例中,半導體裝置封裝包括在介電層之頂部表面及底部表面上方並且電連接至感應柱之一部分之導電零件。在一些實施例中,半導體裝置封裝包括連接至感應柱之一部分以調節電感器之阻抗之一或多個導線。 在一些實施例中,半導體裝置封裝包括插入於兩個RDL之間的介電層。半導體裝置封裝進一步包括整合式電感器,該整合式電感器包括穿透穿過介電層之感應柱及在介電層之兩個相對表面上方並且電連接至感應柱之導電零件。半導體裝置封裝進一步包括經由整合式電感器電連接至彼此之兩個或多於兩個電子組件。整合式電感器之感應柱安置在RDL之間並且鄰近於電子組件。因此,可以減小半導體裝置封裝之厚度及大小。在一些實施例中,半導體裝置封裝可以包括電連接至感應柱之一或多個導線。導線可以在形成電感器之後形成,並且因此可經組態以調節電感器之阻抗。 圖1係根據本發明之一些實施例之半導體裝置封裝1之截面圖。如圖1中所示,半導體裝置封裝1包括介電層40、電感器30、一或多個第一電子組件42及一或多個第二電子組件44。介電層40包括第一表面401 (例如,頂部表面)及與第一表面401相對之第二表面402 (例如,底部表面)。在一些實施例中,介電層40包括聚合物介電層,例如,模製化合物層。藉助於實例,聚合物介電層之材料可包括(但不限於)聚醯亞胺(PI)、聚苯并噁唑(PBO)或其他合適之材料。在一些實施例中,聚合物介電層之材料可以包括(但不限於)光固化材料或可由光固化材料形成(但不限於此),例如光阻劑或類似物。 在一些實施例中,半導體裝置封裝1可以進一步包括第一重佈層(RDL) 20及第二RDL 50。第一RDL 20安置為鄰近於介電層40之第一表面401,且第二RDL 50安置為鄰近於介電層40之第二表面402。在一些實施例中,第一RDL 20包括一或多個導電層201及堆疊至彼此之一或多個絕緣層202。導電層201中之一者可包括自至少一個絕緣層202中暴露且鄰近於介電層40之第一表面401之第一導電零件22。在一些實施例中,第一導電零件22之邊緣係由介電層40圍繞的,而一或多個表面(例如,第一導電零件22之上表面)係自介電層40之第一表面401中暴露的。在一些實施例中,絕緣層202可以包括氧化矽層、氮化矽層或類似物。 在一些實施例中,絕緣層202之硬度大於介電層40之硬度。舉例而言,絕緣層202之硬度(量測為凹痕硬度)可以為介電層40之硬度之至少約1.1倍、至少約1.3倍、或至少約1.5倍。在一些實施例中,第二RDL 50包括一或多個導電層501及堆疊至彼此之一或多個絕緣層502,並且導電層501中之一者可包括自絕緣層502中暴露且鄰近於介電層40之第二表面402之第二導電零件52。在一些實施例中,第二導電零件52在介電層40之第二表面402上方。 電感器30安置於介電層40中。在一些實施例中,電感器30包括一或多個感應柱32。感應柱32中之每一者穿透穿過介電層40,並且在第一RDL 20之第一導電零件22中之各別一者與第二RDL 50之第二導電零件52中之各別一者之間互連。在一些實施例中,感應支柱32與第一導電零件22之高度之總和大體上等於介電層40之厚度。在一些實施例中,感應柱32中之至少一些經由第一導電零件22電連接至導電層201中之至少一者及/或經由第二導電零件52電連接至導電層501中之至少一者。在一些實施例中,電感器30包括實質上垂直於介電層40之第一表面401或第二表面402之至少一個核心區,其中該核心區包括感應柱32中之一或多者。 第一電子組件42及第二電子組件44安置於介電層40中。在一些實施例中,第一電子組件42及第二電子組件44各自可包括呈積體電路(IC)形式之至少一個半導體晶粒。在一些實施例中,第一電子組件42可以包括(但不限於)至少一個主動組件,例如,處理器組件、開關組件、專用IC (ASIC)、場可程式化閘陣列(FPGA)、數位信號處理器(DSP)、記憶體組件或其他主動組件。在一些實施例中,第二電子組件44可包括(但不限於)至少一個被動組件,例如,電容器、電阻器或類似物。 在一些實施例中,第一電子組件42及/或第二電子組件44可為藉由表面安裝技術(SMT)安裝在第二RDL 50上且電連接至第二RDL 50之一或多個倒裝晶片組件。在一些實施例中,第一電子組件42及第二電子組件44可以經由(例如)電感器30電連接至彼此。在一些實施例中,第一電子組件42及第二電子組件44可以分別經由導電結構42C及導電結構44C電連接至第二RDL 50。導電結構42C及導電結構44C可包括(例如)導電柱、導電樁、接合墊或類似物。 在一些實施例中,半導體裝置封裝1進一步包括穿透穿過介電層40且電連接至第一RDL 20及第二RDL 50之連接柱46。在一些實施例中,第一電子組件42及第二電子組件44可經由(例如)電感器30進一步電連接至第一RDL 20,並經由(例如)連接柱46進一步電連接至第二RDL 50之至少一部分。在一些實施例中,導電結構42C及導電結構44C可以短於感應柱32及連接柱46。在一些實施例中,導電結構42C、導電結構44C、感應柱32及連接柱46中之每一者之至少一端可以實質上在與第二RDL 50相同之位準處並且電連接至第二RDL 50。 在一些實施例中,半導體裝置封裝1可以進一步包括安置在第一RDL 20之上方之一或多個第三電子組件60。至少一個第三電子組件60可與第一電子組件42及第二電子組件44相對地安置。在一些實施例中,至少一個第三電子組件60可經由一或多個導電凸塊61 (例如,焊料凸塊、焊料球、焊料膏或類似物)電連接至第一RDL 20。在一些實施例中,至少一個第三電子組件60可經由第一RDL 20電連接至第一電子組件42及/或第二電子組件44。在一些實施例中,第三電子組件60可包括(但不限於)至少一個主動組件,例如,處理器組件、開關組件、ASIC、FPGA、DSP、記憶體組件或其他主動組件。在一些實施例中,半導體裝置封裝1可進一步包括安置在第一RDL 20上方且囊封第三電子組件60之囊封物62。 在一些實施例中,半導體裝置封裝1可以進一步包括安置在第二RDL 50上方之至少一個導線48。導線48可在導線48之一端處電連接至第二導電零件52中之一者,並且在導線48之另一端處電連接至第二導電零件52中之另一者。在一些實施例中,導線48可藉由(例如)導線接合形成。導線48可在形成電感器30之後形成,並且因此可經組態以調節電感器30之阻抗(若電感器30之實際阻抗偏離預先設計之阻抗)。 在一些實施例中,半導體裝置封裝1可進一步包括在第二RDL 50上方且囊封導線48之模製層54。在一些實施例中,一或多個導電結構64 (例如,凸塊下金屬化物(UBM))可安置在模製層54之上方並且電連接至第二RDL 50。在一些實施例中,導電凸塊66 (例如,焊料凸塊、焊料球、焊料膏或類似物)可以安裝在導電結構64之上方且電連接至導電結構64,並且經組態以電連接至其他電子裝置(例如,電路板或類似物)。 圖2A、圖2B、圖2C、圖2D及圖2E說明根據本發明之一些實施例之半導體裝置封裝1之製造方法之實例之各個階段。如圖2A中所描繪,包括第一導電零件22之第一RDL 20形成於載體基板10之上方。在一些實施例中,載體基板10可以包括(但不限於)玻璃基板。 如圖2B中所描繪,感應柱32形成於第一RDL 20上方並且電連接至第一導電零件22。在一些實施例中,連接柱46形成於第一RDL 20上方,並且電連接至第一RDL 20。在一些實施例中,感應柱32及連接柱46在相同之程序中同時形成。在一些其他實施例中,感應柱32在形成連接柱46之前或在形成連接柱46之後形成。在一些實施例中,一或多個第一電子組件42及一或多個第二電子組件44安裝在第一RDL 20上並且電連接至第一RDL 20。 如圖2C中所描繪,介電層40形成於第一RDL 20上方。在一些實施例中,第一導電零件22、感應柱32、連接柱46、第一電子組件42及第二電子組件44之至少一些部分藉由介電層40囊封。在一些實施例中,感應柱32、連接柱46、第一電子組件42及第二電子組件44之至少一些部分係自介電層40之第二表面402中暴露的。 如圖2D中所描繪,包括第二導電零件52之第二RDL50形成於介電層40之第二表面402上方。第二導電零件52電連接至感應柱32之至少一部分。第二RDL 50電連接至連接柱46。第二導電零件52、感應柱32及第一導電零件22電連接並且共同地形成電感器30。在一些實施例中,可形成至少一個導線48以在導線48之一端處電連接第二導電零件52中之一者,並且在導線48之另一端處電連接第二導電零件52中之另一者。在一些實施例中,可藉由導線接合形成導線48,但並不限於此。在一些實施例中,模製層54可在第二RDL 50之上方形成以囊封導線48。在一些實施例中,導電結構64 (例如,UBM)可形成於第二RDL 50上方且電連接至第二RDL 50,並自模製層54中暴露。在一些實施例中,導電凸塊66可安裝在導電結構64之上方,並且電連接至導電結構64。 如圖2E中所描繪,第二RDL 50附接至另一載體基板12,並自載體基板10中釋放第一RDL 20。在一些實施例中,第二RDL 50經由黏著劑層14附接至載體基板12。在一些實施例中,一或多個第三電子組件60安置於或形成於第一RDL 20上方,並經由第一RDL 20電連接至第一電子組件42及/或第二電子組件44。在一些實施例中,囊封物62形成於第一RDL 20上方,囊封一或多個第三電子組件60。隨後,自第二RDL 50中釋放載體基板12。如圖1中所說明,形成半導體裝置封裝1。 本發明之半導體裝置封裝及製造方法不限於上述實施例,且可包括其他不同實施例。出於簡化描述之目的且為了方便在本發明之實施例中之每一者之間進行比較,以下實施例中之每一者中之相同組件標記有相同標號,且不過多地加以描述。 在一些實施例中,第三電子組件60可安置在半導體裝置封裝之任一側上。換言之,第三電子組件60可安置為鄰近於第一RDL 20或第二RDL 50。圖3係根據本發明之一些實施例之半導體裝置封裝2之截面圖。與如圖1中所示之半導體裝置封裝1不同,如圖3中所示之半導體裝置封裝2包括半導體裝置封裝2之第三電子組件60,該第三電子組件60安置在第二RDL 50上方並與第一電子組件42及第二電子組件44相對。在一些實施例中,至少一個第三電子組件60經由第二RDL 50電連接至第一電子組件42及/或第二電子組件44。在一些實施例中,可省略模製層54,且導體裝置封裝2之囊封物62安置在第二RDL 50上方且囊封至少一個第三電子組件60及導線48。在一些其他實施例中,囊封物62囊封至少一個第三電子組件60之一部分。在一些實施例中,半導體裝置封裝2之導電結構64可安置在第一RDL 20上方且電連接至第一RDL 20,且導電凸塊66可以安裝在導電結構64上方且電連接至導電結構64。 圖4A、圖4B、圖4C、圖4D及圖4E說明根據本發明之一些實施例之半導體裝置封裝2之製造方法之實例之各個階段。如圖4A中所描繪,包括第一導電零件22之第一RDL 20形成於載體基板10之上方。 如圖4B中所描繪,感應柱32形成於第一RDL 20上方,且電連接至第一導電零件22。在一些實施例中,連接柱46形成於第一RDL 20上方,且電連接至第一RDL 20。在一些實施例中,感應柱32及連接柱46在相同之程序中同時形成。在一些其他實施例中,感應柱32在形成連接柱46之前或在形成連接柱46之後形成。在一些實施例中,一或多個第一電子組件42及一或多個第二電子組件44安裝在第一RDL 20上且電連接至第一RDL 20。 如圖4C中所描繪,介電層40形成於第一RDL 20上方。在一些實施例中,第一導電零件22、感應柱32、連接柱46、第一電子組件42及第二電子組件44之至少一些部分藉由介電層40囊封。在一些實施例中,感應柱32、連接柱46、第一電子組件42及第二電子組件44之至少一些部分係自介電層40之第二表面402中暴露的。 如圖4D中所描繪,包括第二導電零件52之第二RDL50形成於介電層40之第二表面402上方。第二導電零件52電連接至感應柱32之至少一部分。第二RDL 50電連接至連接柱46。第二導電零件52、感應柱32及第一導電零件22電連接且共同地形成電感器30。在一些實施例中,可形成至少一個導線48以在導線48之一端處電連接第二導電零件52中之一者,並且在導線48之另一端處電連接第二導電零件52中之另一者。在一些實施例中,可藉由導線接合形成導線48,但不限於此。在一些實施例中,一或多個第三電子組件60安置於或形成於第二RDL 50上方,並經由第二RDL 50電連接至第一電子組件42及/或第二電子組件44。 如圖4E中所描繪,囊封物62形成於第二RDL 50上方,囊封至少一個第三電子組件60及導線48。隨後,自載體基板10中釋放第一RDL 20。在一些實施例中,導電結構64 (例如,UBM)可形成於第一RDL 20上方,且導電凸塊66可安裝在導電結構64上方並電連接至導電結構64以形成半導體裝置封裝2。 在一些實施例中,第一電子組件42及第二電子組件44可安置於第一RDL 20上方或第二RDL 50上方。圖5係根據本發明之一些實施例之半導體裝置封裝3之截面圖。與如圖1中所示之半導體裝置封裝1不同,半導體裝置封裝3包括如圖5中所示之安置在第一RDL 20上方且電連接至第一RDL 20之第一電子組件42及第二電子組件44。在一些實施例中,至少一個導線48安置在第二RDL 50上方,並且經由第二RDL 50電連接至第二導電零件52。在一些實施例中,第三電子組件60安置於或形成於第二RDL 50上方,並且經由第二RDL 50電連接至第一電子組件42及第二電子組件44。在一些實施例中,囊封物62安置在第二RDL 50上方,囊封至少一個第三電子組件60及導線48以及第一電子組件42及第二電子組件44。在一些實施例中,導電凸塊66可安裝在第一RDL 20上方,並電連接至第一RDL 20。 圖6A、圖6B、圖6C、圖6D及圖6E說明根據本發明之一些實施例之半導體裝置封裝3之製造方法之實例之各個階段。如圖6A中所描繪,包括第一導電零件22之第一RDL 20形成於載體基板10之上方。 如圖6B中所描繪,感應柱32形成於第一RDL 20上方,並電連接至第一導電零件22。在一些實施例中,連接柱46形成於第一RDL 20上方,並電連接至第一RDL 20。在一些實施例中,感應柱32及連接柱46在相同之程序中同時形成。在一些其他實施例中,感應柱32在形成連接柱46之前或在形成連接柱46之後形成。在一些實施例中,介電層40形成於第一RDL 20上方。在一些實施例中,第一導電零件22、感應柱32及連接柱46之至少一些部分藉由介電層40囊封。在一些實施例中,感應柱32及連接柱46之至少一些部分自介電層40之第二表面402中暴露。 如圖6D中所描繪,包括第二導電零件52之第二RDL50形成於介電層40之第二表面402上方。第二導電零件52電連接至感應柱32之至少一部分。第二RDL 50電連接至連接柱46。第二導電零件52、感應柱32及第一導電零件22電連接且共同地形成電感器30。 如圖6D中所描繪,移除絕緣層502之一部分及介電層40之一部分(例如,藉由噴砂)以暴露第一RDL 20之一部分。 如6E圖中所描繪,一或多個第一電子組件42及一或多個第二電子組件44安置在第一RDL 20上且電連接至第一RDL 20,該第一RDL 20從介電層40中暴露。在一些實施例中,一或多個第三電子組件60安置在第二RDL 50上方,並電連接至第二RDL 50。在一些實施例中,可形成至少一個導線48以在導線48之一端處電連接第二導電零件52中之一者,並在導線48之另一端處電連接第二導電零件52中之另一者。在一些實施例中,囊封物62形成於第二RDL 50上方,囊封第一電子組件42、第二電子組件44、第三電子組件60及導線48之至少一些部分。在一些實施例中,隨後,自載體基板10中釋放第一RDL 20。在一些實施例中,導電凸塊66可安裝在第一RDL 20上方且電連接至第一RDL 20以形成半導體裝置封裝3。 在一些實施例中,半導體裝置封裝可包括安置在兩個RDL之間的一或多個電子組件及囊封一或多個電子組件之模製層。圖7係根據本發明之一些實施例之半導體裝置封裝4之截面視圖。如圖7中所示,半導體裝置封裝4包括介電層40、電感器30、第一RDL 20、第二RDL 50、一或多個第一電子組件42及一或多個第二電子組件44。介電層40包括第一表面401及與第一表面401相對之第二表面402。在一些實施例中,介電層40可包括(但不限於)光固化材料或可由光固化材料形成(但不限於此),例如光阻劑或類似物。 在一些實施例中,第一RDL 20安置為鄰近於介電層40之第一表面401,且第二RDL 50安置為鄰近於介電層40之第二表面402。在一些實施例中,第一RDL 20包括一或多個導電層201及堆疊至彼此之一或多個絕緣層202。導電層201中之一者可包括自絕緣層202中暴露且鄰近於介電層40之第一表面401之第一導電零件22。在一些實施例中,第一導電零件22安置在介電層40之第一表面401上方。在一些實施例中,第二RDL 50包括一或多個導電層501及堆疊至彼此之一或多個絕緣層502。導電層501中之一者可包括自絕緣層502中暴露且鄰近於介電層40之第二表面402之第二導電零件52。在一些實施例中,第二導電零件52安置在介電層40之第二表面402上方。 電感器30安置於介電層40中。在一些實施例中,電感器30包括感應柱32。感應柱32中之每一者穿透穿過介電層40,並且感應柱32中之每一者在第一RDL 20之第一導電零件22中之各別一者與第二RDL 50之第二導電零件52中之各別一者之間互連。在一些實施例中,感應柱32之高度H大體上等於介電層40之厚度T。在一些實施例中,感應柱32中之至少一些經由第一導電零件22及第二導電零件52電連接。在一些實施例中,電感器30包括實質上垂直於介電層40之第一表面401或第二表面402之至少一個核心區,其中該核心區包括感應柱32中之一或多者。 在一些實施例中,第一電子組件42及第二電子組件44在第一RDL 20與第二RDL 50之間。在一些實施例中,半導體裝置封裝4進一步包括由介電層40圍繞之模製層55,且該模製層55囊封第一電子組件42及第二電子組件44。在一些實施例中,第一電子組件42及第二電子組件44可經由電感器30電連接至彼此。在一些實施例中,第一電子組件42及第二電子組件44可分別經由導電結構42C及導電結構44C電連接至第一RDL 20。導電結構42C及導電結構44C可包括導電柱、導電樁、接合墊或類似物。 在一些實施例中,半導體裝置封裝4進一步包括穿透穿過介電層40且電連接至第一RDL 20及第二RDL 50之連接柱46。在一些實施例中,第一電子組件42及第二電子組件44經由電感器30及連接柱46進一步電連接至第二RDL 50。在一些實施例中,導電結構42C及導電結構44C短於感應柱32及連接柱46。在一些實施例中,導電結構42C、導電結構44C、感應柱32及連接柱46中之每一者之至少一端可實質上在與第一RDL 20相同之位準處且電連接至第一RDL 20。 在一些實施例中,半導體裝置封裝4進一步包括安置在第一RDL 20上方且與第一電子組件42及第二電子組件44相對之一或多個第三電子組件60。在一些實施例中,至少一個第三電子組件60經由第一RDL 20電連接至第一電子組件42及第二電子組件44。在一些實施例中,半導體裝置封裝4可進一步包括安置在第一RDL 20上方之至少一個導線48。導線48可在導線48之一端處電連接至第一導電零件22中之一者,並在導線48之另一端處電連接至第一導電零件22中之另一者。在一些實施例中,可藉由導線接合形成導線48。導線48可在形成電感器30之後形成,並且因此可經組態以調節電感器30之阻抗(若電感器30之實際阻抗偏離預先設計之阻抗)。 在一些實施例中,半導體裝置封裝4可進一步包括安置在第一RDL 20上方且囊封至少一個第三電子組件60及導線48之囊封物62。在一些實施例中,半導體裝置封裝4可進一步包括導電凸塊66 (例如,焊料凸塊、焊料球、焊料膏或類似物),該導電凸塊66安裝在第二RDL 50上方且電連接至第二RDL 50,並且經組態以電連接至其他電子裝置(例如,電路板或類似物)。 圖8A、圖8B、圖8C、圖8D及圖8E說明根據本發明之一些實施例之半導體裝置封裝4之製造方法之實例之各個階段。如圖8A中所描繪,晶種層13形成於載體基板10上方。在一些實施例中,晶種層13可以包括鈦銅晶種層,但並不限於此。介電層40形成於晶種層13上方。在一些實施例中,介電層40可以包括(但不限於)光固化材料或可由光固化材料形成(但不限於此),例如光阻劑或類似物。在一些實施例中,介電層40包括至少部分暴露晶種層13之一或多個開口40H。 如圖8B中所描繪,感應柱32穿過至少一些開口40H形成於晶種層13上方,例如,藉由電鍍。在一些實施例中,連接柱46穿過開口40H中之至少一些形成於晶種層13上方。在一些實施例中,感應柱32及連接柱46在相同之程序中同時形成。在一些其他實施例中,感應柱32在形成連接柱46之前或在形成連接柱46之後形成。在一些實施例中,移除介電層40之一部分(例如,藉由噴砂)以暴露晶種層13之一部分。在一些實施例中,一或多個第一電子組件42及一或多個第二電子組件44安裝在晶種層13上方,例如,藉由在介電層40中形成開口且在開口中安裝第一電子組件42及第二電子組件44。 如圖8C中所描繪,模製層55形成於暴露之晶種層13上方,且囊封第一電子組件42及第二電子組件44。在一些實施例中,薄化(例如,藉由研磨)模製層55以暴露感應柱32、連接柱46、導電結構42C及導電結構44C之至少一些部分。如圖8D中所描繪,包括第一導電零件22之第一RDL 20形成於介電層40之第一表面401上方,並且電連接至感應柱32、連接柱46、導電結構42C及導電結構44C。在一些實施例中,一或多個第三電子組件60安置在第一RDL 20上方,並且電連接至第一RDL 20。在一些實施例中,可形成至少一個導線48以經由第一RDL 20電連接第一導電零件22之一部分。 如圖8E中所描繪,囊封物62形成於第一RDL 20上方,並且囊封至少一個第三電子組件60及導線48。在一些實施例中,隨後自載體基板10及晶種層13中釋放介電層40。在一些實施例中,包括第二導電零件52之第二RDL 50形成於介電層40之第二表面402上方,並且電連接至感應柱32及連接柱46。第二導電零件52、感應柱32及第一導電零件22電連接並且共同地形成電感器30。在一些實施例中,導電凸塊66可安裝在第二RDL 50上方且電連接至第二RDL 50以形成半導體裝置封裝4。 除非上下文另外明確規定,否則如本文所用,單數術語「一(a/an)」及「該」可包括多個指示物。 如本文所使用,術語「導電(conductive、electrically conductive)」及「電導率」指代傳遞電流之能力。導電材料通常指示呈現對於電流流動之極少或零對抗之那些材料。電導率之一個量度為西門子每公尺(S/m)。通常,導電材料為電導率大於近似104
S/m (例如,至少105
S/m或至少106
S/m)之一種材料。材料之電導率有時可隨溫度而變化。除非另外說明,否則材料之電導率係在室溫下量測的。 如本文中所使用,術語「近似」、「實質上」、「實質」及「約」用於描述及解釋小的變化。當與事件或情況結合使用時,所述術語可指事件或情況精確發生之例子以及事件或情況極近似地發生之例子。舉例而言,當結合數值使用時,術語可指小於或等於該等數值之±10%之變化範圍,例如,小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%。舉例而言,若兩個數值之間的差小於或等於該等值之平均值之±10% (例如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%,或小於或等於±0.05%),那麼可認為該兩個數值「實質上」相同或相等。舉例而言,「實質上」平行可指代相對於0°之小於或等於±10°之角度變化範圍,例如,小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°,或小於或等於±0.05°。舉例而言,「實質上」垂直可指代相對於90°之小於或等於±10°之角度變化範圍,例如,小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°,或小於或等於±0.05°。 此外,有時在本文中以範圍格式呈現量、比率及其他數值。應理解,此類範圍格式係用於便利及簡潔起見,且應靈活地理解,不僅包括明確地指定為範圍界限之數值,且亦包括涵蓋於該等範圍內之所有個體數值或子範圍,如同明確地規定每一數值及子範圍一般。 儘管已參考本發明之具體實施例描述並說明本發明,但該等描述及說明並不限制本發明。熟習此項技術者應理解,可在不脫離如由所附申請專利範圍定義之本發明之真實精神及範疇之情況下,作出各種改變且取代等效物。所述圖式可能未必按比例繪製。歸因於製造程序及容差,本發明中之藝術再現與實際設備之間可能存在區別。可存在並未特定說明之本發明之其他實施例。應將本說明書及圖式視為說明性的而非限制性的。可做出修改,以使特定情況、材料、物質組成、方法或程序適應於本發明之目標、精神以及範疇。所有此類修改都意欲在所附申請專利範圍之範圍內。雖然本文中所揭示之方法已參考按特定次序執行之特定操作加以描述,但應理解,可在不脫離本發明之教示之情況下組合、細分或重新排序該等操作以形成等效方法。因此,除非本文中特別指示,否則操作之次序及分組並非本發明之限制。
1‧‧‧半導體裝置封裝2‧‧‧半導體裝置封裝3‧‧‧半導體裝置封裝10‧‧‧載體基板13‧‧‧晶種層20‧‧‧第一重佈層(RDL)201‧‧‧導電層202‧‧‧絕緣層22‧‧‧第一導電零件30‧‧‧電感器32‧‧‧感應柱40‧‧‧介電層401‧‧‧第一表面402‧‧‧第二表面40H‧‧‧開口42‧‧‧第一電子組件42C‧‧‧導電結構44‧‧‧第二電子組件44C‧‧‧導電結構46‧‧‧連接柱48‧‧‧導線50‧‧‧第二RDL501‧‧‧導電層502‧‧‧絕緣層52‧‧‧第二導電零件54‧‧‧模製層60‧‧‧第三電子組件61‧‧‧導電凸塊62‧‧‧囊封物64‧‧‧導電結構66‧‧‧導電凸塊
當結合附圖閱讀時,自以下具體實施方式中最好地理解本發明之一些實施例之態樣。應注意,各種結構可能未按比例繪製,且各種結構之尺寸可出於論述之清楚起見而任意增大或減小。 圖1說明根據本發明之一些實施例之半導體裝置封裝之截面圖; 圖2A說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖2B說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖2C說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖2D說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖2E說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖3說明根據本發明之一些實施例之半導體裝置封裝之截面圖; 圖4A說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖4B說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖4C說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖4D說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖4E說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖5說明根據本發明之一些實施例之半導體裝置封裝之截面圖; 圖6A說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖6B說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖6C說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖6D說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖6E說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖7說明根據本發明之一些實施例之半導體裝置封裝之截面圖; 圖8A說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖8B說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖8C說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖8D說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段; 圖8E說明根據本發明之一些實施例之半導體裝置封裝之製造方法之實例之一或多個階段。
1‧‧‧半導體裝置封裝
20‧‧‧第一重佈層(RDL)
201‧‧‧導電層
202‧‧‧絕緣層
22‧‧‧第一導電零件
30‧‧‧電感器
32‧‧‧感應柱
40‧‧‧介電層
401‧‧‧第一表面
402‧‧‧第二表面
42‧‧‧第一電子組件
42C‧‧‧導電結構
44‧‧‧第二電子組件
44C‧‧‧導電結構
46‧‧‧連接柱
48‧‧‧導線
50‧‧‧第二RDL
501‧‧‧導電層
502‧‧‧絕緣層
52‧‧‧第二導電零件
54‧‧‧模製層
60‧‧‧第三電子組件
61‧‧‧導電凸塊
62‧‧‧囊封物
64‧‧‧導電結構
66‧‧‧導電凸塊
Claims (18)
- 一種半導體裝置封裝,其包含:一介電層,其包含一第一表面及與該第一表面相對之一第二表面;一第一重佈層(RDL),其鄰近於該介電層之該第一表面;一第二RDL,其鄰近於該介電層之該第二表面,其中該第一RDL及該第二RDL之其中至少一者包含一絕緣層,且該絕緣層之一硬度大於該介電層之一硬度;一電感器,其安置於該介電層中,該電感器包含複數個穿過該介電層之感應柱、複數個第一導電零件鄰近於該介電層之該第一表面,以及複數個第二導電零件鄰近於該介電層之該第二表面,其中該等感應柱中之每一者穿過該介電層,且該等感應柱中之每一者在該等第一導電零件中之各別一者與該等第二導電零件中之各別一者之間互連;以及一第一電子組件及一第二電子組件,其安置在該介電層並在該第一RDL與該第二RDL之間且經由該電感器電連接至彼此。
- 如請求項1之半導體裝置封裝,其中該第一電子組件包含一主動組件,且該第二電子組件包含一被動組件。
- 如請求項1之半導體裝置封裝,其中該介電層包含一聚合物介電層,且該聚合物介電層之一材料包含一光固化材料。
- 如請求項1之半導體裝置封裝,其進一步包含穿過該介電層且電連接至該第一RDL及該第二RDL之複數個連接柱。
- 如請求項1之半導體裝置封裝,其進一步包含在該第一RDL上方之一第三電子組件,其中該第一RDL安置在該第三電子組件及該第一電子組件之間及安置在該第三電子組件及該第二電子組件之間。
- 如請求項1之半導體裝置封裝,其進一步包含在該第二RDL上方之一導線,其中該導線在該導線之一端處電連接至該等第二導電零件中之一者,且在該導線之另一端處電連接至該等第二導電零件中之另一者。
- 如請求項1之半導體裝置封裝,其中介電層圍繞該等第一導電零件之至少一部分。
- 一種半導體裝置封裝,其包含:一介電層,其包含一第一表面及與該第一表面相對之一第二表面;一電感器,其安置於該介電層中,該電感器包含:穿過該介電層之複數個感應柱;複數個第一導電零件鄰近於該介電層之該第一表面且電連接至該等感應柱;及複數個第二導電零件鄰近於該介電層之該第二表面且電連接至該等感應柱,其中該等感應柱之一第一感應柱與堆疊於該第一感應柱上之該等第一導電零件之一第一導電零件的一高度和大體上 等於該介電層之一厚度;及一導線,其電連接至該等感應柱中之至少一者。
- 如請求項8之半導體裝置封裝,其進一步包含囊封該導線之一模製層。
- 如請求項8之半導體裝置封裝,其進一步包含一第一重佈層(RDL)鄰近於該介電層之該第一表面。
- 如請求項10之半導體裝置封裝,其中該第一RDL包含一第一絕緣層及安置於該第一絕緣層上的一第一導電層。
- 如請求項10之半導體裝置封裝,其進一步包含一第二RDL鄰近於該介電層之該第二表面。
- 如請求項12之半導體裝置封裝,其中該第二RDL包含一第二絕緣層及安置於該第二絕緣層上的一第二導電層。
- 如請求項12之半導體裝置封裝,其進一步包含穿過該介電層且電連接至該第一RDL及該第二RDL之複數個連接柱。
- 如請求項8之半導體裝置封裝,其進一步包含複數個一電子組件,其安置在該介電層並經由該電感器電連接至彼此。
- 如請求項8之半導體裝置封裝,其中該介電層圍繞該等第一導電零件的邊緣。
- 如請求項8之半導體裝置封裝,其中該介電層暴露出該等第二導電零件的邊緣。
- 如請求項8之半導體裝置封裝,其中該介電層包含一聚合物介電層。
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TW201901881A (zh) | 2019-01-01 |
US20180337164A1 (en) | 2018-11-22 |
US10475718B2 (en) | 2019-11-12 |
CN108962871A (zh) | 2018-12-07 |
CN108962871B (zh) | 2021-11-12 |
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