TW201717293A - 具有空腔之聚合物系半導體結構 - Google Patents

具有空腔之聚合物系半導體結構 Download PDF

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TW201717293A
TW201717293A TW105130495A TW105130495A TW201717293A TW 201717293 A TW201717293 A TW 201717293A TW 105130495 A TW105130495 A TW 105130495A TW 105130495 A TW105130495 A TW 105130495A TW 201717293 A TW201717293 A TW 201717293A
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cavity
dielectric layer
device die
top surface
encapsulating material
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TWI616958B (zh
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余振華
郭鴻毅
蔡豪益
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台灣積體電路製造股份有限公司
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Abstract

一種結構，其包括一裝置晶粒；以及一囊封材料，囊封該裝置晶粒於其中。該囊封材料具有一頂部表面，與該裝置晶粒的一頂部表面共平面；以及一空腔，在該囊封材料中。該空腔穿透過該囊封材料。

Description

具有空腔之聚合物系半導體結構
本揭露係關於一種具有空腔之聚合物系半導體結構及其製造方法。
隨著半導體技術的發展，半導體晶片/晶粒變得越來越小。於此同時，更多功能必須被整合至半導體晶粒中。據此，半導體晶粒必須具有來越大數目的輸入/輸出(input/output，I/O)墊封裝至較小的面積中，且I/O墊的密度隨時間快速上升。結果，半導體晶粒的封裝變得更困難，其負面地影響封裝良率。 習用封裝件技術可分成兩類別。在第一類別中，在晶圓上之晶粒係在它們被鋸下之前封裝。此封裝技術具有一些有利特徵，諸如較大產能以及較低成本。再者，需要較少底膠填充或模塑料。然而，此封裝技術也受缺點所苦。由於晶粒的大小變得越來越小，以及對應封裝件僅可以是扇入型封裝件，其中各晶粒之I/O墊限制在直接在對應晶粒表面上方之區。以受限之晶粒面積，I/O墊的數目因I/O墊節距之限制而受限。若將墊的節距降低，焊料區可能彼此橋接，而造成電路故障。另外，在固定球大小之要求下，焊球必然具有一定大小，其進而限制可封裝在晶粒表面上之焊球數目。 在另一類別封裝中，晶粒係在它們被封裝之前自晶圓上鋸下。此封裝的一有利特徵是形成扇出封裝件的可能性，其意味著在晶粒上之I/O墊可再分佈至大於該晶粒之面積，而因此可增加封裝在晶粒表面上之I/O墊的數目。此封裝技術的另一有利特徵是將“已知良好晶粒(known-good-die)”封裝，並將缺陷晶粒丟棄，而因此不會將成本與氣力浪費在缺陷晶粒上。
根據本揭露的一些實施例，一種結構係包括一裝置晶粒；以及一囊封材料，囊封該裝置晶粒於其中。該囊封材料具有一頂部表面，與該裝置晶粒的一頂部表面共平面；以及一空腔，在該囊封材料中。該空腔穿透過該囊封材料。 根據本揭露的一些實施例，一種封裝件係包括一裝置晶粒；以及一囊封材料，囊封該裝置晶粒於其中。該囊封材料具有一頂部表面，與該裝置晶粒的一頂部表面共平面。一電感，其包括一線圈，該線圈具有一部分，該部分自該囊封材料的該頂部表面延伸至該囊封材料的該底部表面。至少一個介電層係在該囊封材料以及該線圈之該部分上方。複數個重佈線係形成在該至少一個介電層中。該電感係透過該等重佈線電耦合至該裝置晶粒。一空腔，穿透該囊封材料以及該至少一個介電層。 根據本揭露的一些實施例，一種方法係包括：囊封一裝置晶粒在一囊封材料中；平坦化該裝置晶粒的一頂部表面以及該囊封材料的一頂部表面；形成至少一個介電層在該囊封材料以及該裝置晶粒上方；以及形成複數個重佈線在該至少一個介電層中。該等重佈線係電耦合至該裝置晶粒。該囊封材料以及該至少一個介電層的一部分係被移除，以形成一空腔，該空腔穿透過該至少一個介電層以及該囊封材料。
下列揭露提供許多用於實現本發明之不同特徵的不同實施例、或實例。為了簡化本揭露，於下描述組件及配置的具體實例。當然這些僅為實例而非意圖為限制性。例如，在下面說明中，形成第一特徵在第二特徵上方或上可包括其中該第一及第二特徵係經形成為直接接觸之實施例，以及也可包括其中額外特徵可形成在該第一與第二特徵之間而使得該第一及第二特徵不直接接觸之實施例。此外，本揭露可重複參考編號及/或字母於各種實例中。此重複係為了簡單與清楚之目的且其本身並不決定所討論的各種實施例及/或組態之間的關係。 再者，空間相關詞彙，諸如“下方(underlying)”、“之下(below)”、“下(lower)”、“上方(overlying)”、“上(upper)”和類似詞彙，可為了使說明書便於描述如圖式繪示的一個元件或特徵與另一個（或多個）元件或特徵的相對關係而使用於本文中。除了圖式中所畫的方位外，這些空間相對詞彙也意圖用來涵蓋裝置在使用中或操作時的不同方位。該設備可以其他方式定向(旋轉90度或於其它方位)，據此在本文中所使用的這些空間相關說明符可以類似方式加以解釋。 根據各種例示性實施例係提供一種封裝件以及形成該封裝件之方法，該封裝件具有一空腔，該空腔可穿透過對應封裝件的一囊封材料。係繪示形成該封裝件的中間階段。係討論一些實施例的一些變化。遍及各種視圖及說明性實施例，類似的參考編號係用於表示類似的元件。 圖1至17係根據本揭露的一些實施例繪示在一些封裝件的形成中之中間階段的剖面圖以及俯視圖。在圖1至17中所顯示之步驟也示意性地繪示在圖20中所顯示的製程流程圖200中。 圖1繪示載體20以及形成在載體20上方的離型層22。載體20可以是玻璃載體、陶瓷載體、或類似物。載體20可具有圓形俯視形狀，且可具有矽晶圓大小。例如，載體20可具有8英吋直徑、12英吋直徑、或類似者。離型層22可由聚合物系材料(諸如光熱轉換(light to heat conversion，LTHC)材料)所形成，其可連同載體20自將於後續步驟中形成的上方結構移除。根據本揭露的一些實施例，離型層22係由環氧系熱離型材料所形成。根據本揭露的一些實施例，離型層22係由紫外光(ultra-violet，UV)膠所形成。離型層22可呈液體供給並固化。根據本揭露的替代性實施例，離型層22係層壓膜且係層壓至載體20上。離型層22的頂部表面係整平且具有高度共平面性。 根據本揭露的一些實施例，介電層24係形成在離型層22上方。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟202。在最終產品中，介電層24可用來作為鈍化層，以將上方金屬特徵與溼氣及其他害物質的負面效果隔離。介電層24可由聚合物所形成，該聚合物也可以是光敏材料諸如聚苯并噁唑(polybenzoxazole，PBO)、聚醯亞胺、苯并環丁烯(benzocyclobutene，BCB)、及類似物。根據本揭露的替代性實施例，介電層24係由無機材料(等)所形成，該材料可以是氮化物諸如氮化矽、氧化物諸如氧化矽、磷矽酸鹽玻璃(PhosphoSilicate Glass，PSG)、硼矽酸鹽玻璃(BoroSilicate Glass，BSG)、硼摻雜磷矽酸鹽玻璃(Boron-doped PhosphoSilicate Glass，BPSG)、或類似物。根據本揭露的又些替代性實施例，沒有介電層24被形成。據此，介電層24係以虛線顯示，以表明其可形成或可不形成。 圖2以及3繪示導電部件32之形成，由於導電部件穿透將在後續步驟中施加之囊封材料52(圖6)，故下文中將導電部件稱作貫穿導體。參考圖2，晶種層26係例如透過物理氣相沉積(Physical Vapor Deposition，PVD)或金屬箔層壓而形成在介電層24上方。晶種層26可由銅、鋁、鈦、或其之多層所形成。根據本揭露的一些實施例，晶種層26包括鈦層(未顯示)以及在鈦層上方的銅層(未顯示)。根據替代性實施例，晶種層26包括單一銅層。 光阻28係施加在晶種層26上方且接著被圖案化。對應步驟也顯示成圖20中所顯示之製程流程圖的步驟202。因此，開口30係形成在光阻28中，透過開口30暴露出晶種層26的一些部分。 如圖2所顯示，貫穿導體32係透過鍍覆製程形成在開口30中，該鍍覆製程可以是電鍍或無電式電鍍。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟204。貫穿導體32係鍍覆在晶種層26之暴露的部分上。貫穿導體32可包括銅、鋁、鎢、鎳或其合金。貫穿導體32的俯視形狀包括但不限於螺旋、環、長方形、正方形、圓形、及類似物，這取決於貫穿導體32的意欲功能。根據各種實施例，貫穿導體32的高度係由後續所放之裝置晶粒38的厚度(圖3)判定，具有貫穿導體32的高度大於或等於裝置晶粒38的厚度。 在貫穿導體32鍍覆之後，光阻28移除，且所得結構顯示在圖3中。暴露出晶種層26先前被光阻28覆蓋的部分(圖2)。接著實施蝕刻步驟，以移除晶種層26之暴露的部分，其中該蝕刻可以是非等向性或等向性蝕刻。另一方面，晶種層26被貫穿導體32所重疊的部分維持未被蝕刻。在整個說明書中，將晶種層26留下的下方部分視為貫穿導體32的底部部分。當晶種層26係由相似於或相同於對應上方貫穿導體32所具者之材料形成時，晶種層26可與貫穿導體32融合而在其等之間沒有可區分介面。據此，晶種層26未顯示在後續圖式中。根據本揭露的替代性實施例，在晶種層26與上方經鍍覆之貫穿導體32的部分之間存在有可區分介面。 貫穿導體32的俯視形狀係關於它們的意欲功能且由它們的意欲功能判定。根據一些其中貫穿導體32係用來形成電感之例示性實施例，所繪示之貫穿導體32可以是線圈的部件。圖19A及19B係根據一些例示性實施例繪示一些電感的俯視圖。在圖19A中，貫穿導體32形成複數個同心環，以外環圍繞內環。該等環具有中斷以允許外環透過橋36連接至內環，且該等環係串聯連接至兩個端口34。在圖19B中，貫穿導體32係一體式螺旋的部分，該一體式螺旋也具有端口34。雖然圖19B繪示左側的端口34係與裝置晶粒38不連接，根據一些實施例，左側的端口34也可連接至裝置晶粒38。 圖4繪示置放裝置晶粒38在載體20上方。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟206。裝置晶粒38可透過晶粒附接膜(Die-Attach Film，DAF)40黏附至介電層24，DAF係黏著劑膜。根據本揭露的一些實施例，裝置晶粒38係中央處理單元(Central Processing Unit，CPU)晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入輸出(Input-output，IO)晶粒、基頻(BaseBand，BB)晶粒、或應用處理機(Application Processor，AP)晶粒。雖然繪示一個裝置晶粒38，可將更多裝置晶粒放在介電層24上方。根據本揭露的一些實施例，封裝件的形成係在晶圓級。據此，可將複數個與裝置晶粒38完全相同之裝置晶粒放在載體20上，且係呈具有複數個列與行之陣列分佈。 裝置晶粒38可包括半導體基板42，其可以是矽基板。積體電路44係形成在半導體基板42上。積體電路44可包括主動裝置諸如電晶體及二極體及/或被動裝置諸如電阻、電容、電感、或類似物。裝置晶粒38可包括電耦合至積體電路44之金屬柱46。金屬柱46可包埋在介電層48中，介電層可以是由例如PBO、聚醯亞胺、或BCB所形成。也繪示鈍化層50，其中金屬柱46可延伸至鈍化層50中。鈍化層50可包括氮化矽、氧化矽、或其之多層。 接下來，參考圖5，將囊封材料52囊封/成型在裝置晶粒38上。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟208。囊封材料52填充相鄰貫穿導體32之間的間隙以及貫穿導體32與裝置晶粒38之間的間隙。囊封材料52可包括聚合物系材料，且可包括模塑料、模塑底膠填充、環氧化物、及/或樹脂。囊封材料52的頂部表面高於金屬柱46的頂端。 在後續步驟中，如圖6所顯示，實施平坦化製程諸如化學機械拋光(Chemical Mechanical Polish，CMP)製程或研磨製程，以減少囊封材料52的頂部表面，直到暴露出貫穿導體32及金屬柱46。對應步驟也顯示成圖20中所顯示之製程流程圖的步驟210。由於平坦化，貫穿導體32的頂端係實質上與金屬柱46的頂部表面齊平(共平面)，且係實質上與囊封材料52的頂部表面共平面。 在如上述之例示性製程步驟中，貫穿導體32係經形成為穿透過囊封材料52。再者，貫穿導體32係與裝置晶粒38共平面。根據本揭露的一些其他實施例，沒有貫穿導體係經形成為穿透過囊封材料52。 圖7至11繪示正面重佈線(redistribution line，RDL)及相應介電層的形成。參考圖7，係形成介電層54。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟212。根據本揭露的一些實施例，介電層54是由聚合物諸如PBO、聚醯亞胺、或類似物所形成。根據本揭露的替代性實施例，介電層54是由無機材料諸如氮化矽、氧化矽、或類似物所形成。開口56係形成在介電層54中(例如，透過曝光及顯影)，以暴露出貫穿導體32及金屬柱46。開口56可透過光微影製程形成。 接下來，參考圖8，形成重佈線(RDL)58以連接金屬柱46及貫穿導體32。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟214。RDL 58也可互連金屬柱46與貫穿導體32。此外，RDL 58也可用來形成電感33的橋36(圖19A)。RDL 58包括金屬跡線(金屬線)在介電層54上方以及延伸至介電層54中之通路。在RDL 58中之通路係連接至貫穿導體32及金屬柱46。根據本揭露的一些實施例，RDL 58之形成係包括形成整片銅晶種層(blanket copper seed layer)、形成及圖案化遮罩層在整片銅晶種層上方、實施鍍覆以形成RDL 58、移除遮罩層、以及蝕刻整片銅晶種層不被RDL 58所覆蓋的部分。RDL 58可由金屬或金屬合金，包括鋁、銅、鎢、及/或其合金所形成。 參考圖9，根據一些實施例，介電層60係形成在圖8所顯示之結構上方，接著係形成開口62在介電層60中。RDL 58的一些部分因此被暴露出。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟216。可使用選自用於形成介電層54之相同候選材料之材料來形成介電層60。 接下來，如圖10所顯示，RDL 64係形成在介電層60中。對應步驟也顯示成圖20中所顯示之製程流程圖的步驟216。根據本揭露的一些實施例，RDL 64之形成係包括形成整片銅晶種層、形成及圖案化遮罩層在整片銅晶種層上方、實施鍍覆以形成RDL 64、移除遮罩層、以及蝕刻整片銅晶種層不被RDL 64所覆蓋的部分。RDL 64也可由金屬或金屬合金，包括鋁、銅、鎢、及/或其合金所形成。可以理解的是，雖然在繪示之例示性實施例中形成兩層RDL(58及64)，但可具有任何數目的RDL層，諸如一層或多於兩層。 圖11及12係根據一些例示性實施例繪示介電層66及電連接件68之形成。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟218。參考圖11，介電層66係使用例如PBO、聚醯亞胺、或BCB形成。開口59係形成在介電層66中，以暴露出下方金屬墊，其係RDL 64之部件。根據一些實施例，凸塊下金屬(Under-Bump Metallurgies，UBMs，未顯示)係經形成為延伸至在介電層66中之開口59中。 接著形成電連接件68，如圖12所顯示。電連接件68之形成可包括將焊球放在UBM之暴露的部分上，以及接著回銲焊球。根據本揭露的替代性實施例，電連接件68之形成係包括實施鍍覆步驟以形成焊料區在RDL 64中之暴露的金屬墊上方，以及接著回銲焊料區。電連接件68也可包括金屬柱、或金屬柱與焊料帽，其也可透過鍍覆形成。在整個說明書中，包括介電層24以及組合之上方結構的結構被稱作封裝件100，其係包括複數個裝置晶粒38之複合晶圓。 接下來，封裝件100係自載體20去接合，例如藉由投射UV光或雷射束在離型層22上，而使得離型層22在UV光或雷射束的熱下分解。封裝件100因此自載體20去接合。所得封裝件100係顯示於圖13中。根據本揭露的一些實施例，在所得封裝件100中，介電層24留下作為封裝件100的底部部件，並保護貫穿導體32。介電層24可以是整層，且其中沒有貫穿開口。根據替代性實施例，不形成介電層24，且在去接合之後，暴露出囊封材料52的底部表面及貫穿導體32的底部表面。可實施(或可不實施)背面研磨以移除DAF 40(若有使用之)，而使得貫穿導體32的底部表面係與裝置晶粒38的底部表面共平面。裝置晶粒38的底部表面也可以是半導體基板42的底部表面。 在後續步驟中，如圖14A所顯示，形成空腔70。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟220。根據本揭露的一些實施例，空腔70係藉由雷射鑽孔形成。根據替代性實施例，空腔70係藉由使用鑽頭鑽孔形成。根據本揭露的又其他實施例，空腔70係藉由使用刀片切割形成。據此，空腔70的俯視形狀可以是環狀形狀、矩形(例如正方形)形狀、多邊形、或另一種形狀，這取決於空腔70的意欲用途，如將在後續步驟中討論者。由於空腔70可使用雷射、鑽頭、或刀片形成，空腔的側壁70C可以是垂直，且頂部尺寸W1係等於底部尺寸W2。根據替代性實施例，側壁70C係直且傾斜，例如具有在約45度與約135度之間範圍之傾斜角α。據此，頂部尺寸W1可大於或小於底部尺寸W2。最佳傾斜角α以及最佳寬度W1與W2係藉由在後續步驟中將放在空腔70中之組件的形狀及大小判定。 根據本揭露的一些例示性實施例，如圖19A及19B所顯示，空腔70被電感33中之貫穿導體(等)32圍繞，如藉由空腔70A所繪示者。根據替代性實施例，如藉由空腔70B所表示者，空腔70係不被電感33圍繞。根據一些例示性實施例，在各封裝件100中有複數個空腔，且一些空腔(諸如70A)被貫穿導體32圍繞且一些其它者(諸如70B)不被貫穿導體32圍繞。 回頭參考圖14A，根據一些例示性實施例，空腔70穿透過囊封材料52，且進一步穿透過介電層54、60、及66。空腔70可穿透過介電層24，因此空腔70形成穿透過整個封裝件100的貫穿孔。根據一些其它實施例，如圖14B所顯示，空腔70穿透過囊封材料52，而空腔70不穿透過介電層24。根據又些替代性實施例，空腔70穿透過介電層54、60、及66，且延伸至囊封材料52的頂部表面52A與底部表面52B之間的中間水平。虛線72繪示對應底部表面。空腔70也可具有兩面都被傾斜底部表面所包圍之平面，如也藉由虛線72所繪示者。 根據本揭露的一些實施例，接著封裝件100被單粒化且封裝件100被鋸成複數個彼此完全相同之封裝件100’。圖15繪示例示性封裝件100’。根據一些例示性實施例，組件76係插入至空腔70中。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟222。根據一些例示性實施例，如圖15所顯示，包括鏡頭78之攝像機76係放在空腔70中。根據一些實施例，線80表示攝像機76的電線。未顯示在封裝件100’中之插入組件76的安裝機制，其可透過例如黏著、螺接、或類似者達成。組件76可不需使用任何固定組件諸如黏著劑、夾具、及螺釘而固定在空腔70中。例如，藉由小心地設計空腔70及組件76的大小，可將組件76擠進囊封材料52中，而因此牢固。替代地來說，移除攝像機76而不破壞封裝件100’是可能的。根據本揭露的一些實施例，插入組件76係包括與囊封材料52齊平的第一部分，以及與上方介電層54/60/66齊平的第二部分。根據本揭露的替代性實施例，插入組件76的整體係低於囊封材料52的頂部表面或與囊封材料52的頂部表面齊平。據此，插入組件76係完全在囊封材料52內，且不包括與上方介電層54/60/66齊平的部分。 根據一些實施例，插入組件76係鐵磁體材料，其也放在空腔70中，如圖18所顯示。根據一些實施例，鐵磁體材料76可包括錳-鋅、鎳-鋅、或類似物。鐵磁體材料76在高頻具有相對低損失，且係用來作為電感33的芯(也參考圖19A及19B)，其可以是無線充電器或開關模式電源供應器的部件。 圖16及17係根據一些例示性實施例繪示封裝件100’的組裝製程。對應步驟係顯示成圖20中所顯示之製程流程圖的步驟224。圖16繪示將封裝件100’接合至封裝件元件110，此係例如透過電連接件68。封裝件元件110可以是印刷電路板(Printed Circuit Board，PCB)、插入物、封裝件基板、或類似物。根據替代性實施例，封裝件100’係電連接至撓性PCB(未顯示)，其可與空腔70及組件76重疊、或從側邊連接。 圖17繪示產品，其中封裝件100’及封裝件元件110係放在外殼82中。外殼82可以是例如蜂巢式電話、平版、或電腦的外殼。外殼82的經繪示部分係下部，且外殼82進一步包括在封裝件100’及封裝件元件110上方的上部以及在封裝件100’及封裝件元件110左邊與右邊的部分(未顯示)。根據本揭露的一些實施例，窗84係經形成為對準攝像機76，其中窗84係由透光材料諸如玻璃、塑膠、或類似物所形成。鏡頭78因此可接收穿過窗84的光。組件76及囊封材料52之各者可與外殼82接觸、或以小間隙與外殼82分隔開。 在如圖17所顯示之例示性結構中，作為一實例，係繪示電感33。根據一些實施例，不形成電感33，而攝像機76(或其它插入物體)係固定在囊封材料52內。 本揭露的實施例具有一些有利特徵。藉由形成一空腔在一封裝件的囊封材料中，而可將一組件插入至該囊封材料中。據此，該組件不必凸出超過該囊封材料，而因此減少所得產品厚度。 根據本揭露的一些實施例，一種結構係包括一裝置晶粒；以及一囊封材料，囊封該裝置晶粒於其中。該囊封材料具有一頂部表面，與該裝置晶粒的一頂部表面共平面；以及一空腔，在該囊封材料中。該空腔穿透過該囊封材料。 根據本揭露的一些實施例，一種封裝件係包括一裝置晶粒；以及一囊封材料，囊封該裝置晶粒於其中。該囊封材料具有一頂部表面，與該裝置晶粒的一頂部表面共平面。一電感，其包括一線圈，該線圈具有一部分，該部分自該囊封材料的該頂部表面延伸至該囊封材料的該底部表面。至少一個介電層係在該囊封材料以及該線圈之該部分上方。複數個重佈線係形成在該至少一個介電層中。該電感係透過該等重佈線電耦合至該裝置晶粒。一空腔，穿透該囊封材料以及該至少一個介電層。 根據本揭露的一些實施例，一種方法係包括：囊封一裝置晶粒在一囊封材料中；平坦化該裝置晶粒的一頂部表面以及該囊封材料的一頂部表面；形成至少一個介電層在該囊封材料以及該裝置晶粒上方；以及形成複數個重佈線在該至少一個介電層中。該等重佈線係電耦合至該裝置晶粒。該囊封材料以及該至少一個介電層的一部分係被移除，以形成一空腔，該空腔穿透過該至少一個介電層以及該囊封材料。 前面列述了數個實施例的特徵以便本技術領域具有通常知識者可更佳地理解本揭露之態樣。本技術領域具有通常知識者應了解他們可輕易地使用本揭露作為用以設計或修改其他製程及結構之基礎以實現本文中所介紹實施例的相同目的及/或達成本文中所介紹實施例的相同優點。本技術領域具有通常知識者也應體認到此等均等構造不會背離本揭露之精神及範疇，以及他們可在不背離本揭露之精神及範疇下做出各種改變、取代、或替代。
20‧‧‧載體
22‧‧‧離型層
24、48、54、60、66‧‧‧介電層
26‧‧‧晶種層
28‧‧‧光阻
30、56、59、62‧‧‧開口
32‧‧‧導電部件/貫穿導體
33‧‧‧電感
34‧‧‧端口
36‧‧‧橋
38‧‧‧裝置晶粒
40‧‧‧晶粒附接膜/DAF
42‧‧‧半導體基板
44‧‧‧積體電路
46‧‧‧金屬柱
50‧‧‧鈍化層
52‧‧‧囊封材料
52A‧‧‧頂部表面
52B‧‧‧底部表面
58、64‧‧‧重佈線/RDL
68‧‧‧電連接件
70、70A、70B‧‧‧空腔
70C‧‧‧側壁
72‧‧‧虛線
76‧‧‧攝像機/組件/插入組件/鐵磁體材料
78‧‧‧鏡頭
80‧‧‧線
82‧‧‧外殼
84‧‧‧窗
100、100’‧‧‧封裝件
110‧‧‧封裝件元件
200‧‧‧製程流程圖
202、204、206、208、210、212、214、216、218、220、222、224‧‧‧步驟
W1‧‧‧頂部尺寸/寬度
W2‧‧‧底部尺寸/寬度
α‧‧‧傾斜角
本揭露之態樣將在與隨附圖式一同閱讀下列詳細說明下被最佳理解。請注意，根據業界標準作法，各種特徵未依比例繪製。事實上，為了使討論內容清楚，各種特徵的尺寸可刻意放大或縮小。 圖1至17係根據一些實施例繪示在一些封裝件的形成中之中間階段的剖面圖。 圖18係根據一些實施例繪示包括有插入至空腔中之鐵磁體材料的封裝件的剖面圖。 圖19A及19B係根據一些實施例繪示一些封裝件的俯視圖。 圖20係根據一些實施例繪示用於形成封裝件之製程流程圖。
24、48、54、60、66‧‧‧介電層
32‧‧‧導電部件/貫穿導體
33‧‧‧電感
38‧‧‧裝置晶粒
40‧‧‧晶粒附接膜/DAF
42‧‧‧半導體基板
44‧‧‧積體電路
46‧‧‧金屬柱
50‧‧‧鈍化層
52‧‧‧囊封材料
58、64‧‧‧重佈線/RDL
68‧‧‧電連接件
70‧‧‧空腔
76‧‧‧攝像機/組件/插入組件/鐵磁體材料
78‧‧‧鏡頭
80‧‧‧線
82‧‧‧外殼
84‧‧‧窗
100’‧‧‧封裝件
110‧‧‧封裝件元件

Claims (10)

  1. 一種結構，其包含： 一裝置晶粒； 一囊封材料，囊封該裝置晶粒於其中；以及 一空腔，在該囊封材料中，其中該空腔穿透過該囊封材料。
  2. 如申請專利範圍第1項之結構，進一步包含： 複數個介電層，在該囊封材料上方； 重佈線，在該等介電層中，其中該空腔進一步以該空腔包含一側壁自該等介電層的一最頂部層的一頂部表面延伸至該囊封材料的一底部表面而穿透過該等介電層； 一焊料區，在該等介電層的一頂部表面；以及 一封裝件元件，接合至該焊料區。
  3. 如申請專利範圍第1項之結構，進一步包含： 一導電線圈，穿透過該囊封材料，其中該空腔被該導電線圈圍繞；以及 一鐵磁體材料，放置在該空腔中。
  4. 如申請專利範圍第1項之結構，進一步包含： 一介電層，在該囊封材料下方，其中該空腔進一步穿透過該介電層。
  5. 一種結構，其包含： 一封裝件，其包含： 一裝置晶粒； 一囊封材料，囊封該裝置晶粒於其中； 一電感，其包含： 一線圈，其包含一部分，該部分自該囊封材料的一頂部表面延伸至該囊封材料的一底部表面；以及 至少一個介電層，在該囊封材料以及該線圈之該部分上方； 複數個重佈線，在該至少一個介電層中，其中該電感透過該等重佈線電耦合至該裝置晶粒；以及 一空腔，其中該空腔穿透過該囊封材料以及該至少一個介電層。
  6. 如申請專利範圍第5項之結構，其中該空腔自該至少一個介電層中的一最頂部層的一頂部表面延伸至該囊封材料的該底部表面。
  7. 如申請專利範圍第5項之結構，其中該空腔具有與該囊封材料的該頂部表面及該底部表面垂直的側壁。
  8. 如申請專利範圍第5項之結構，進一步包含一印刷電路板，接合至該封裝件，其中該印刷電路板覆蓋該空腔。
  9. 一種方法，其包含： 囊封一裝置晶粒在一囊封材料中； 平坦化該裝置晶粒的一頂部表面以及該囊封材料的一頂部表面； 形成至少一個介電層在該囊封材料以及該裝置晶粒上方； 形成複數個重佈線在該至少一個介電層中，其中該等重佈線電耦合至該裝置晶粒；以及 移除該囊封材料以及該至少一個介電層的一部分，以形成一空腔，該空腔穿透過該至少一個介電層以及該囊封材料。
  10. 如申請專利範圍第9項之方法，進一步包含插入一組件至該空腔中，該方法更包括形成一電感，具有一部分與該裝置晶粒共平面，其中該空腔被該電感圍繞，以及在該平坦化之後，露出該電感之該部分的一頂部表面，以及其中該插入該組件係包含插入一鐵磁體至該空腔中。
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