CN107068625B - 具有空腔的聚合物系半导体结构 - Google Patents

具有空腔的聚合物系半导体结构 Download PDF

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CN107068625B
CN107068625B CN201610969011.XA CN201610969011A CN107068625B CN 107068625 B CN107068625 B CN 107068625B CN 201610969011 A CN201610969011 A CN 201610969011A CN 107068625 B CN107068625 B CN 107068625B
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cavity
encapsulation material
dielectric layer
device die
package
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CN107068625A (zh
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余振华
郭鸿毅
蔡豪益
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露涉及一种具有空腔的聚合物系半导体结构。一种结构，其包括装置裸片；以及囊封材料，在其中囊封所述装置裸片。所述囊封材料具有顶部表面，与所述装置裸片的顶部表面共平面；以及空腔，在所述囊封材料中。所述空腔穿透所述囊封材料。

Description

具有空腔的聚合物系半导体结构
技术领域
本揭露涉及一种具有空腔的聚合物系半导体结构和其制造方法。
背景技术
随着半导体技术的发展，半导体芯片/裸片变得越来越小。于此同时，更多功能必须被集成到半导体裸片中。据此，半导体裸片必须具有越来越大数目的输入/输出(input/output，I/O)垫封装到较小的面积中，且I/O垫的密度随时间快速上升。结果，半导体裸片的封装变得更困难，其负面地影响封装成出率。
习用封装件技术可分成两类别。在第一类别中，在晶片上的裸片是在它们被锯下之前封装。此封装技术具有一些有利特征，例如较大产能以及较低成本。再者，需要较少底胶填充或模塑料。然而，此封装技术也受缺点所苦。由于裸片的大小变得越来越小，以及对应封装件仅可以是扇入型封装件，其中各裸片的I/O垫限制在直接在对应裸片表面上方的区。以受限的裸片面积，I/O垫的数目因I/O垫节距的限制而受限。如果将垫的节距降低，那么焊料区可能彼此桥接，而造成电路故障。另外，在固定球大小的要求下，焊球必然具有一定大小，其进而限制可封装在裸片表面上的焊球数目。
在另一类别封装中，裸片是在它们被封装之前从晶片上锯下。此封装的一有利特征是形成扇出封装件的可能性，其意味着在裸片上的I/O垫可再分布到大于所述裸片的面积，而因此可增加封装在裸片表面上的I/O垫的数目。此封装技术的另一有利特征是将“已知良好裸片(known-good-die)”封装，并将缺陷裸片丢弃，而因此不会将成本与气力浪费在缺陷裸片上。
发明内容
根据本揭露的一些实施例，一种结构包括装置裸片；以及囊封材料，在其中囊封所述装置裸片。所述囊封材料具有顶部表面，与所述装置裸片的顶部表面共平面；以及空腔，在所述囊封材料中。所述空腔穿透所述囊封材料。
根据本揭露的一些实施例，一种封装件包括装置裸片；以及囊封材料，在其中囊封所述装置裸片。所述囊封材料具有顶部表面，与所述装置裸片的顶部表面共平面。电感，其包括线圈，所述线圈具有一部分，所述部分从所述囊封材料的所述顶部表面延伸到所述囊封材料的所述底部表面。至少一个介电层是在所述囊封材料以及所述线圈的所述部分上方。多个再分布线形成在所述至少一个介电层中。所述电感是通过所述再分布线电耦合到所述装置裸片。空腔，穿透所述囊封材料以及所述至少一个介电层。
根据本揭露的一些实施例，一种方法包括：在囊封材料中囊封装置裸片；平坦化所述装置裸片的顶部表面以及所述囊封材料的顶部表面；在所述囊封材料以及所述装置裸片上方形成至少一个介电层；以及在所述至少一个介电层中形成多个再分布线。所述再分布线电耦合到所述装置裸片。去除所述囊封材料以及所述至少一个介电层的一部分，以形成空腔，所述空腔穿透所述至少一个介电层以及所述囊封材料。
附图说明
本揭露的方面将在与随附图式一同阅读下列详细说明下被最佳理解。请注意，根据业界标准作法，各种特征未依比例绘制。事实上，为了使讨论内容清楚，各种特征的尺寸可刻意放大或缩小。
图1到17是根据一些实施例绘示在一些封装件的形成中的中间阶段的剖面图。
图18是根据一些实施例绘示包括有插入到空腔中的铁磁体材料的封装件的剖面图。
图19A和19B是根据一些实施例绘示一些封装件的俯视图。
图20是根据一些实施例绘示用于形成封装件的工艺流程图。
具体实施方式
下列揭露提供许多用于实现本发明的不同特征的不同实施例、或实例。为了简化本揭露，于下描述组件和布置的具体实例。当然这些仅为实例而非意图为限制性。例如，在下面说明中，形成第一特征在第二特征上方或上可包括其中所述第一和第二特征经形成为直接接触的实施例，以及也可包括其中额外特征可形成在所述第一与第二特征之间而使得所述第一和第二特征不直接接触的实施例。此外，本揭露可重复参考编号和/或字母于各种实例中。此重复是为了简单与清楚的目的且其本身并不决定所讨论的各种实施例和/或配置之间的关系。
再者，空间相关词汇，例如“下方(underlying)”、“之下(below)”、“下(lower)”、“上方(overlying)”、“上(upper)”和类似词汇，可为了使说明书便于描述如图式绘示的一个元件或特征与另一个(或多个)元件或特征的相对关系而使用于本文中。除了图式中所画的方位外，这些空间相对词汇也意图用来涵盖装置在使用中或操作时的不同方位。所述设备可以其它方式取向(旋转90度或于其它方位)，据此在本文中所使用的这些空间相关说明符可以类似方式加以解释。
根据各种例示性实施例提供一种封装件以及形成所述封装件的方法，所述封装件具有空腔，所述空腔可穿透对应封装件的囊封材料。绘示形成所述封装件的中间阶段。讨论一些实施例的一些变化。贯穿各种视图和说明性实施例，类似的参考编号是用于表示类似的元件。
图1到17是根据本揭露的一些实施例绘示在一些封装件的形成中的中间阶段的剖面图以及俯视图。在图1到17中所显示的步骤也示意性地绘示在图20中所显示的工艺流程图200中。
图1绘示载体20以及形成在载体20上方的离型层22。载体20可以是玻璃载体、陶瓷载体、或类似物。载体20可具有圆形俯视形状，且可具有硅晶片大小。例如，载体20可具有8英寸直径、12英寸直径、或类似者。离型层22可由聚合物系材料(例如光热转换(light toheat conversion，LTHC)材料)所形成，其可连同载体20从将于后续步骤中形成的上方结构去除。根据本揭露的一些实施例，离型层22是由环氧系热离型材料所形成。根据本揭露的一些实施例，离型层22是由紫外(ultra-violet，UV)胶所形成。离型层22可呈液体供给并固化。根据本揭露的替代性实施例，离型层22是层压膜且层压到载体20上。离型层22的顶部表面整平且具有高度共平面性。
根据本揭露的一些实施例，介电层24形成在离型层22上方。对应步骤显示成图20中所显示的工艺流程图的步骤202。在最终产品中，介电层24可用来作为钝化层，以将上方金属特征与湿气和其它有害物质的负面效果隔离。介电层24可由聚合物所形成，所述聚合物也可以是光敏材料，例如聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺、苯并环丁烯(benzocyclobutene，BCB)、及类似物。根据本揭露的替代性实施例，介电层24由无机材料(等)所形成，所述材料可以是氮化物例如氮化硅、氧化物例如氧化硅、磷硅酸盐玻璃(PhosphoSilicate Glass，PSG)、硼硅酸盐玻璃(BoroSilicate Glass，BSG)、掺杂硼的磷硅酸盐玻璃(Boron-doped PhosphoSilicate Glass，BPSG)、或类似物。根据本揭露的另外的替代性实施例，没有介电层24被形成。据此，介电层24以虚线显示，以表明其可形成或可不形成。
图2和3绘示导电部件32的形成，由于导电部件穿透将在后续步骤中施加的囊封材料52(图6)，故下文中将导电部件称作贯穿导体。参考图2，晶种层26例如通过物理气相沉积(Physical Vapor Deposition，PVD)或金属箔层压而形成在介电层24上方。晶种层26可由铜、铝、钛、或其的多层所形成。根据本揭露的一些实施例，晶种层26包括钛层(未显示)以及在钛层上方的铜层(未显示)。根据替代性实施例，晶种层26包括单一铜层。
光致抗蚀剂28施加在晶种层26上方且接着被图案化。对应步骤也显示成图20中所显示的工艺流程图的步骤202。因此，开口30形成在光致抗蚀剂28中，通过开口30暴露出晶种层26的一些部分。
如图2所显示，贯穿导体32通过镀覆工艺形成在开口30中，所述镀覆工艺可以是电镀或无电式电镀。对应步骤显示成图20中所显示的工艺流程图的步骤204。贯穿导体32镀覆在晶种层26的暴露的部分上。贯穿导体32可包括铜、铝、钨、镍或其合金。贯穿导体32的俯视形状包括但不限于螺旋、环、长方形、正方形、圆形、及类似物，这取决于贯穿导体32的意图功能。根据各种实施例，贯穿导体32的高度由后续所放的装置裸片38的厚度(图3)确定，其中贯穿导体32的高度大于或等于装置裸片38的厚度。
在贯穿导体32镀覆之后，光致抗蚀剂28去除，且所得结构显示在图3中。暴露出晶种层26先前被光致抗蚀剂28覆盖的部分(图2)。接着实施蚀刻步骤，以去除晶种层26的暴露的部分，其中所述蚀刻可以是非等向性或等向性蚀刻。另一方面，晶种层26被贯穿导体32所重叠的部分维持未被蚀刻。在整个说明书中，将晶种层26留下的下方部分视为贯穿导体32的底部部分。当晶种层26由相似于或相同于对应上方贯穿导体32所具有的材料形成时，晶种层26可与贯穿导体32融合而在其等之间没有可区分接口。据此，晶种层26未显示在后续图式中。根据本揭露的替代性实施例，在晶种层26与上方经镀覆的贯穿导体32的部分之间存在有可区分接口。
贯穿导体32的俯视形状是关于它们的意图功能且由它们的意图功能确定。根据一些其中贯穿导体32用来形成电感的例示性实施例，所绘示的贯穿导体32可以是线圈的部件。图19A和19B是根据一些例示性实施例绘示一些电感的俯视图。在图19A中，贯穿导体32形成多个同心环，以外环围绕内环。所述环具有中断以允许外环通过桥36连接到内环，且所述环串联连接到两个端口34。在图19B中，贯穿导体32是一体式螺旋的部分，所述一体式螺旋也具有端口34。虽然图19B绘示左侧的端口34与装置裸片38不连接，但根据一些实施例，左侧的端口34也可连接到装置裸片38。
图4绘示放置装置裸片38在载体20上方。对应步骤显示成图20中所显示的工艺流程图的步骤206。装置裸片38可通过裸片附接膜(Die-Attach Film，DAF)40粘附到介电层24，DAF是粘接剂膜。根据本揭露的一些实施例，装置裸片38是中央处理单元(CentralProcessing Unit，CPU)裸片、微控制单元(Micro Control Unit，MCU)裸片、输入输出(Input-output，IO)裸片、基带(BaseBand，BB)裸片、或应用处理机(ApplicationProcessor，AP)裸片。虽然绘示一个装置裸片38，但可将更多装置裸片放在介电层24上方。根据本揭露的一些实施例，封装件的形成是在晶片级。据此，可将多个与装置裸片38完全相同的装置裸片放在载体20上，且是呈具有多个行与列的阵列分布。
装置裸片38可包括半导体衬底42，其可以是硅衬底。集成电路44形成在半导体衬底42上。集成电路44可包括有源装置，例如晶体管和二极管；和/或无源装置，例如电阻、电容、电感、或类似物。装置裸片38可包括电耦合到集成电路44的金属柱46。金属柱46可包埋在介电层48中，介电层可以是由例如PBO、聚酰亚胺、或BCB所形成。也绘示钝化层50，其中金属柱46可延伸到钝化层50中。钝化层50可包括氮化硅、氧化硅、或其的多层。
接下来，参考图5，将囊封材料52囊封/成型在装置裸片38上。对应步骤显示成图20中所显示的工艺流程图的步骤208。囊封材料52填充相邻贯穿导体32之间的间隙以及贯穿导体32与装置裸片38之间的间隙。囊封材料52可包括聚合物系材料，且可包括模塑料、模塑底胶填充、环氧化物、和/或树脂。囊封材料52的顶部表面高于金属柱46的顶端。
在后续步骤中，如图6所显示，实施平坦化工艺例如化学机械抛光(ChemicalMechanical Polish，CMP)工艺或研磨工艺，以减少囊封材料52的顶部表面，直到暴露出贯穿导体32和金属柱46。对应步骤也显示成图20中所显示的工艺流程图的步骤210。由于平坦化，贯穿导体32的顶端实质上与金属柱46的顶部表面齐平(共平面)，且实质上与囊封材料52的顶部表面共平面。
在如上述的例示性工艺步骤中，贯穿导体32经形成为穿透囊封材料52。再者，贯穿导体32与装置裸片38共平面。根据本揭露的一些其它实施例，没有贯穿导体经形成为穿透囊封材料52。
图7到11绘示正面再分布线(redistribution line，RDL)和相应介电层的形成。参考图7，形成介电层54。对应步骤显示成图20中所显示的工艺流程图的步骤212。根据本揭露的一些实施例，介电层54是由聚合物例如PBO、聚酰亚胺、或类似物所形成。根据本揭露的替代性实施例，介电层54是由无机材料例如氮化硅、氧化硅、或类似物所形成。开口56形成在介电层54中(例如，通过曝光和显影)，以暴露出贯穿导体32和金属柱46。开口56可通过光刻工艺形成。
接下来，参考图8，形成再分布线(RDL)58以连接金属柱46和贯穿导体32。对应步骤显示成图20中所显示的工艺流程图的步骤214。RDL 58也可互连金属柱46与贯穿导体32。此外，RDL 58也可用来形成电感33的桥36(图19A)。RDL 58包括金属迹线(金属线)在介电层54上方以及延伸到介电层54中的通路。在RDL 58中的通路连接到贯穿导体32和金属柱46。根据本揭露的一些实施例，RDL 58的形成包括形成整片铜晶种层(blanket copper seedlayer)、形成和图案化掩模层在整片铜晶种层上方、实施镀覆以形成RDL 58、去除掩模层、以及蚀刻整片铜晶种层不被RDL 58所覆盖的部分。RDL 58可由金属或金属合金，包括铝、铜、钨、和/或其合金所形成。
参考图9，根据一些实施例，介电层60形成在图8所显示的结构上方，接着在介电层60中形成开口62。RDL 58的一些部分因此被暴露出。对应步骤显示成图20中所显示的工艺流程图的步骤216。可使用选自用于形成介电层54的相同候选材料的材料来形成介电层60。
接下来，如图10所显示，RDL 64形成在介电层60中。对应步骤也显示成图20中所显示的工艺流程图的步骤216。根据本揭露的一些实施例，RDL 64的形成包括形成整片铜晶种层、在整片铜晶种层上方形成和图案化掩模层、实施镀覆以形成RDL 64、去除掩模层、以及蚀刻整片铜晶种层不被RDL 64所覆盖的部分。RDL 64也可由金属或金属合金，包括铝、铜、钨、和/或其合金所形成。可以理解的是，虽然在绘示的例示性实施例中形成两层RDL(58及64)，但可具有任何数目的RDL层，例如一层或多于两层。
图11和12是根据一些例示性实施例绘示介电层66和电连接件68的形成。对应步骤显示成图20中所显示的工艺流程图的步骤218。参考图11，介电层66使用例如PBO、聚酰亚胺、或BCB形成。开口59形成在介电层66中，以暴露出下方金属垫，其是RDL 64的部件。根据一些实施例，凸块下金属(Under-Bump Metallurgies，UBM，未显示)经形成为延伸到在介电层66中的开口59中。
接着形成电连接件68，如图12所显示。电连接件68的形成可包括将焊球放在UBM的暴露的部分上，以及接着回焊焊球。根据本揭露的替代性实施例，电连接件68的形成包括实施镀覆步骤以在RDL 64中的暴露的金属垫上方形成焊料区，以及接着回焊焊料区。电连接件68也可包括金属柱、或金属柱与焊料帽，其也可通过镀覆形成。在整个说明书中，包括介电层24以及组合的上方结构的结构被称作封装件100，其包括多个装置裸片38的复合晶片。
接下来，封装件100从载体20去接合，例如通过在离型层22上投射UV光或激光束，而使得离型层22在UV光或激光束的热下分解。封装件100因此从载体20去接合。所得封装件100显示于图13中。根据本揭露的一些实施例，在所得封装件100中，介电层24留下作为封装件100的底部部件，并保护贯穿导体32。介电层24可以是整层，且其中没有贯穿开口。根据替代性实施例，不形成介电层24，且在去接合之后，暴露出囊封材料52的底部表面和贯穿导体32的底部表面。可实施(或可不实施)背面研磨以去除DAF 40(如果有使用的话)，而使得贯穿导体32的底部表面与装置裸片38的底部表面共平面。装置裸片38的底部表面也可以是半导体衬底42的底部表面。
在后续步骤中，如图14A所显示，形成空腔70。对应步骤显示成图20中所显示的工艺流程图的步骤220。根据本揭露的一些实施例，空腔70是通过激光钻孔形成。根据替代性实施例，空腔70是通过使用钻头钻孔形成。根据本揭露的又其它实施例，空腔70是通过使用刀片切割形成。据此，空腔70的俯视形状可以是环状形状、矩形(例如正方形)形状、多边形、或另一种形状，这取决于空腔70的意图用途，如将在后续步骤中讨论者。由于空腔70可使用激光、钻头、或刀片形成，空腔的侧壁70C可以是垂直，且顶部尺寸W1等于底部尺寸W2。根据替代性实施例，侧壁70C直且倾斜，例如具有在约45度与约135度之间范围的倾斜角α。据此，顶部尺寸W1可大于或小于底部尺寸W2。最佳倾斜角α以及最佳宽度W1与W2是通过在后续步骤中将放在空腔70中的组件的形状和大小确定。
根据本揭露的一些例示性实施例，如图19A和19B所显示，空腔70被电感33中的贯穿导体(等)32围绕，如通过空腔70A所绘示者。根据替代性实施例，如通过空腔70B所表示者，空腔70不被电感33围绕。根据一些例示性实施例，在各封装件100中有多个空腔，且一些空腔(例如70A)被贯穿导体32围绕且一些其它者(例如70B)不被贯穿导体32围绕。
返回参考图14A，根据一些例示性实施例，空腔70穿透囊封材料52，且进一步穿透介电层54、60、和66。空腔70可穿透介电层24，因此空腔70形成穿透整个封装件100的贯穿孔。根据一些其它实施例，如图14B所显示，空腔70穿透囊封材料52，而空腔70不穿透介电层24。根据另外的替代性实施例，空腔70穿透介电层54、60、和66，且延伸到囊封材料52的顶部表面52A与底部表面52B之间的中间水平。虚线72绘示对应底部表面。空腔70也可具有两面都被倾斜底部表面所包围的平面，如也通过虚线72所绘示者。
根据本揭露的一些实施例，接着封装件100被单粒化且封装件100被锯成多个彼此完全相同的封装件100'。图15绘示例示性封装件100'。根据一些例示性实施例，组件76插入到空腔70中。对应步骤显示成图20中所显示的工艺流程图的步骤222。根据一些例示性实施例，如图15所显示，包括镜头78的摄像机76放在空腔70中。根据一些实施例，线80表示摄像机76的电线。未显示在封装件100'中的插入组件76的安装机制，其可通过例如粘附、螺接、或类似者达成。组件76可不需使用任何固定组件例如粘接剂、夹具、和螺钉而固定在空腔70中。例如，通过小心地设计空腔70和组件76的大小，可将组件76挤进囊封材料52中，而因此牢固。替代地来说，去除摄像机76而不破坏封装件100'是可能的。根据本揭露的一些实施例，插入组件76包括与囊封材料52齐平的第一部分，以及与上方介电层54/60/66齐平的第二部分。根据本揭露的替代性实施例，插入组件76的整体低于囊封材料52的顶部表面或与囊封材料52的顶部表面齐平。据此，插入组件76完全在囊封材料52内，且不包括与上方介电层54/60/66齐平的部分。
根据一些实施例，插入组件76是铁磁体材料，其也放在空腔70中，如图18所显示。根据一些实施例，铁磁体材料76可包括锰-锌、镍-锌、或类似物。铁磁体材料76在高频具有相对低损失，且是用来作为电感33的芯(也参考图19A和19B)，其可以是无线充电器或开关模式电源供应器的部件。
图16和17是根据一些例示性实施例绘示封装件100'的组装工艺。对应步骤显示成图20中所显示的工艺流程图的步骤224。图16绘示将封装件100'接合到封装件元件110，此是例如通过电连接件68。封装件元件110可以是印刷电路板(Printed Circuit Board，PCB)、插入物、封装件衬底、或类似物。根据替代性实施例，封装件100'电连接到柔性PCB(未显示)，其可与空腔70和组件76重叠、或从侧边连接。
图17绘示产品，其中封装件100'和封装件元件110放在外壳82中。外壳82可以是例如蜂窝式电话、平板、或计算机的外壳。外壳82的经绘示部分是下部，且外壳82进一步包括在封装件100'和封装件元件110上方的上部以及在封装件100'和封装件元件110左边与右边的部分(未显示)。根据本揭露的一些实施例，窗84经形成为对准摄像机76，其中窗84是由透光材料例如玻璃、塑料、或类似物所形成。镜头78因此可接收穿过窗84的光。组件76和囊封材料52的各者可与外壳82接触、或以小间隙与外壳82分隔开。
在如图17所显示的例示性结构中，作为实例，是绘示电感33。根据一些实施例，不形成电感33，而摄像机76(或其它插入物体)固定在囊封材料52内。
本揭露的实施例具有一些有利特征。通过形成空腔在封装件的囊封材料中，而可将组件插入到所述囊封材料中。据此，所述组件不必凸出超过所述囊封材料，而因此减少所得产品厚度。
根据本揭露的一些实施例，一种结构包括装置裸片；以及囊封材料，囊封所述装置裸片于其中。所述囊封材料具有顶部表面，与所述装置裸片的顶部表面共平面；以及空腔，在所述囊封材料中。所述空腔穿透所述囊封材料。
根据本揭露的一些实施例，一种封装件包括装置裸片；以及囊封材料，囊封所述装置裸片于其中。所述囊封材料具有顶部表面，与所述装置裸片的顶部表面共平面。电感，其包括线圈，所述线圈具有部分，所述部分从所述囊封材料的所述顶部表面延伸到所述囊封材料的所述底部表面。至少一个介电层是在所述囊封材料以及所述线圈的所述部分上方。多个再分布线形成在所述至少一个介电层中。所述电感通过所述再分布线电耦合到所述装置裸片。空腔，穿透所述囊封材料以及所述至少一个介电层。
根据本揭露的一些实施例，一种方法包括：囊封装置裸片在囊封材料中；平坦化所述装置裸片的顶部表面以及所述囊封材料的顶部表面；形成至少一个介电层在所述囊封材料以及所述装置裸片上方；以及形成多个再分布线在所述至少一个介电层中。所述再分布线电耦合到所述装置裸片。所述囊封材料以及所述至少一个介电层的一部分被去除，以形成空腔，所述空腔穿透所述至少一个介电层以及所述囊封材料。
前文列述了数个实施例的特征以便所属领域的一般技术人员可更佳地理解本揭露的方面。所属领域的一般技术人员应了解，他们可轻易地使用本揭露作为用以设计或修改其它工艺和结构的基础以实现本文中所介绍实施例的相同目的和/或达成本文中所介绍实施例的相同优点。所属领域的一般技术人员也应体认到，此等均等构造不会背离本揭露的精神和范围，以及他们可在不背离本揭露的精神和范围下做出各种改变、取代、或替代。
符号说明
100、100' 封装件
110 封装件元件
200 工艺流程图
202、204、206、208、210、212、214、216、218、220、222、224 步骤
20 载体
22 离型层
24、48、54、60、66 介电层
26 晶种层
28 光致抗蚀剂
30、56、59、62 开口
32 导电部件/贯穿导体
33 电感
34 端口
36 桥
38 装置裸片
40 裸片附接膜/DAF
42 半导体衬底
44 集成电路
46 金属柱
50 钝化层
52 囊封材料
52A 顶部表面
52B 底部表面
58、64 再分布线/RDL
68 电连接件
70、70A、70B 空腔
70C 侧壁
72 虚线
76 摄像机/组件/插入组件
/铁磁体材料
78 镜头
80 线
82 外壳
84 窗
W1 顶部尺寸/宽度
W2 底部尺寸/宽度
α 倾斜角

Claims (20)

1.一种具有空腔的聚合物系半导体的结构，其包含：
装置裸片；
囊封材料，在其中囊封所述装置裸片；
导电线圈，穿透所述囊封材料；以及
空腔，在所述囊封材料中，其中所述空腔穿透所述囊封材料；
其中所述空腔被所述导电线圈围绕。
2.根据权利要求1所述的结构，进一步包含：
多个介电层，在所述囊封材料上方；以及
再分布线，在所述介电层中，其中所述空腔进一步以所述空腔包含从所述介电层的最顶部层的顶部表面延伸到所述囊封材料的底部表面的侧壁而穿透所述介电层。
3.根据权利要求2所述的结构，进一步包含：
焊料区，在所述介电层的顶部表面；以及
封装件元件，接合到所述焊料区。
4.根据权利要求1所述的结构，
其中所述空腔被所述导电线圈螺旋形围绕。
5.根据权利要求4所述的结构，进一步包含铁磁体材料，放置在所述空腔中。
6.根据权利要求1所述的结构，进一步包含摄像机，放置在所述空腔中。
7.根据权利要求1所述的结构，进一步包含：
介电层，在所述囊封材料下方，其中所述空腔进一步穿透所述介电层。
8.一种具有空腔的聚合物系半导体的结构，其包含：
封装件，其包含：
装置裸片；
囊封材料，在其中囊封所述装置裸片；
电感，其包含：
线圈，其包含一部分，所述部分从所述囊封材料的顶部表面延伸到所述囊封材料的底部表面；以及
至少一个介电层，在所述囊封材料以及所述线圈的所述部分上方；
多个再分布线，在所述至少一个介电层中，其中所述电感通过所述再分布线电耦合到所述装置裸片；以及
空腔，其中所述空腔被所述线圈围绕以及穿透所述囊封材料以及所述至少一个介电层。
9.根据权利要求8所述的结构，其中所述空腔从所述至少一个介电层中的最顶部层的顶部表面延伸到所述囊封材料的所述底部表面。
10.根据权利要求8所述的结构，其中所述空腔具有与所述囊封材料的所述顶部表面和所述底部表面垂直的侧壁。
11.根据权利要求8所述的结构，其中所述空腔具有既不与所述囊封材料的所述顶部表面和所述底部表面垂直也不与所述囊封材料的所述顶部表面和所述底部表面平行的倾斜侧壁。
12.根据权利要求8所述的结构，进一步包含铁磁体材料，放置在所述空腔中。
13.根据权利要求8所述的结构，进一步包含摄像机，放置在所述空腔中。
14.根据权利要求8所述的结构，进一步包含印刷电路板，所述印刷电路板接合到所述封装件，其中所述印刷电路板覆盖所述空腔。
15.一种制造具有空腔的聚合物系半导体的方法，其包含：
在囊封材料中囊封装置裸片；
在部分所述装置裸片共平面处形成电感；
平坦化所述装置裸片的顶部表面以及所述囊封材料的顶部表面；
在所述囊封材料以及所述装置裸片上方形成至少一个介电层；
在所述至少一个介电层中形成多个再分布线，其中所述再分布线电耦合到所述装置裸片；以及
去除所述囊封材料以及所述至少一个介电层的一部分，以形成空腔，所述空腔穿透所述至少一个介电层以及所述囊封材料；
其中所述空腔被所述电感围绕。
16.根据权利要求15所述的方法，进一步包含将组件插入到所述空腔中。
17.根据权利要求16所述的方法，其中所述插入所述组件包含插入摄像机到所述空腔中。
18.根据权利要求16所述的方法，
其中在所述平坦化之后，露出所述电感的所述部分的顶部表面，以及其中所述插入所述组件包含插入铁磁体到所述空腔中。
19.根据权利要求15所述的方法，其中所述形成所述空腔包含选自下列各者的钻孔工艺：钻头、激光钻孔、或刀片切割。
20.根据权利要求15所述的方法，其中所述装置裸片以及所述囊封材料是封装件的部件，以及所述方法进一步包含将封装件元件接合到所述封装件。
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