TWI757674B - 封裝體及其封裝方法 - Google Patents

封裝體及其封裝方法 Download PDF

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Publication number
TWI757674B
TWI757674B TW108148050A TW108148050A TWI757674B TW I757674 B TWI757674 B TW I757674B TW 108148050 A TW108148050 A TW 108148050A TW 108148050 A TW108148050 A TW 108148050A TW I757674 B TWI757674 B TW I757674B
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Taiwan
Prior art keywords
antenna
redistribution structure
redistribution
substrate
forming
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TW108148050A
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English (en)
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TW202029454A (zh
Inventor
莊博堯
蔡柏豪
鄭心圃
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台灣積體電路製造股份有限公司
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Priority claimed from US16/559,143 external-priority patent/US11532867B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202029454A publication Critical patent/TW202029454A/zh
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Publication of TWI757674B publication Critical patent/TWI757674B/zh

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Abstract

一種封裝方法，包括將天線基板接合至重佈結構。天線基板具有第一天線的第一部分，而重佈結構具有第一天線的第二部分。上述方法更包括將天線基板密封至密封材料中，並將封裝組件接合至重佈結構。重佈結構包括第二天線的第三部分，而封裝組件包括第二天線的第四部分。

Description

封裝體及其封裝方法
本揭露係有關於一種3D(三維)封裝體，特別係有關於一種包括天線的3D封裝體。
內建天線(built-in antenna)被廣泛用於諸如手機之行動裝置(mobile applications)中。傳統上，所形成的天線可以有一部分在重佈線路(redistribution line)中，而另一部分在印刷電路板中。因為所得天線的頻寬(bandwidth)與印刷電路板和重佈線路間之距離有關而為固定，因此這種方法對多波段(multi-band)的應用造成問題。
本揭露實施例提供一種封裝方法。上述封裝方法包括將一天線基板接合至一重佈結構，其中上述天線基板包括第一天線的第一部分，而上述重佈結構包括第一天線的第二部分；將上述天線基板密封於密封材料中；以及將一封裝組件接合至上述重佈結構，其中上述重佈結構與上述天線基板中的一者包括第二天線的第三部分，而上述封裝組件包括第二天線的第四部分。
本揭露實施例提供一種封裝方法。上述封裝方法包括將一RFIC晶 粒接合至一重佈結構；將一天線基板接合至上述重佈結構；以及將一印刷電路板接合至上述重佈結構，其中上述重佈結構、上述天線基板、以及上述印刷電路板中的每一者，包括第一天線及第二天線中的一者或兩者的至少一個組件，其中第一天線包括第一補釘本體及第一反射器，且第一補釘本體與第一反射器之間具有第一間隔，而第二天線包括第二補釘本體及第二反射器，且第二補釘本體與第二反射器之間具有第二間隔，其中第一間隔不同於第二間隔。
本揭露實施例提供一種封裝體。上述封裝體包括一重佈結構；一天線基板，接合至上述重佈結構；以及一印刷電路板，接合至上述重佈結構，其中上述重佈結構、上述天線基板、以及上述印刷電路板共同形成第一天線及第二天線，其中上述重佈結構、上述天線基板、以及上述印刷電路板中的每一者，包括第一天線及第二天線中的一者或兩者的至少一個組件。
20:介電核心
21:覆蓋式基板
22A、22B:金屬膜
24:貫穿開口
26、26A、26B:通孔電極
28、28A、28B:導電特徵
30A、30B:介電遮罩層
34:電性連接器
38:天線基板
40:晶圓
42:半導體基板
44:電路
46:互連結構
48:表面導電特徵
50:電性連接器
56:裝置晶粒
60:載體
62:脫離薄膜
64:介電緩衝層
66:介電層
68:開口
70:重佈線路
70A:重佈線路
70B:金屬墊
74:介電層
76:重佈線路
77:重佈結構
78:金屬支柱
80:電鍍遮罩
82:開口
84:黏著薄膜
86:密封材料
88:重建晶圓
90:電性連接器
92:封裝體
87:虛線
94:封裝組件
100:封裝體
102:反射器
104、106:天線
S1、S2:間隔
76A:補釘本體
76B:反射器
28A1、28A2:補釘本體
120:反射器
S2’:間隔
28A3:補釘本體
S2”:間隔
57:裝置晶粒
78’:金屬支柱
122:獨立被動元件
22A-22A:截面
200:製程流程
202-240:製程
本揭露之態樣自後續實施方式及附圖可更佳理解。須強調的是，依據產業之標準作法，各種特徵並未按比例繪製。事實上，各種特徵之尺寸可能任意增加或減少以清楚論述。
第1圖至第6圖係根據本揭露一些實施例所示，形成天線基板之中間階段的截面圖，該天線基板包括射頻(RF)天線的一些部分。
第7圖及第8圖係根據本揭露一些實施例所示，形成裝置晶粒之中間階段的截面圖。
第9圖至第19圖係根據本揭露一些實施例所示，形成包括RF天線之封裝體的中間階段的截面圖。
第20圖及第21圖係根據本揭露一些實施例所示，包括RF天線之一些封裝體的截面圖。
第22A圖及第22B圖分別為根據本揭露一些實施例所示，包括RF天線之封裝體的截面圖及平面圖。
第23圖係根據本揭露一些實施例所示，形成包括RF天線之封裝體的製程流程。
以下之揭露提供許多不同實施例或範例，用以實施本揭露之不同特徵。本揭露之各部件及排列方式，其特定範例敘述於下以簡化說明。理所當然的，這些範例並非用以限制本揭露。舉例來說，若敘述中有著第一特徵成形於第二特徵之上或上方，其可能包含第一特徵與第二特徵以直接接觸成形之實施例，亦可能包含有附加特徵形成於第一特徵與第二特徵之間，而使第一特徵與第二特徵間並非直接接觸之實施例。此外，本揭露可在多種範例中重複參考數字及/或字母。該重複之目的係為簡化及清晰易懂，且本身並不規定所討論之多種實施例及/或配置間之關係。
進一步來說，本揭露可能會使用空間相對術語，例如「下方」、「在...下方」、「低於」、「在...上方」、「高於」及類似詞彙，以便於敘述圖式中一個元件或特徵與其他元件或特徵間之關係。除了圖式所描繪之方位外，空間相對術語亦欲涵蓋使用中或操作中之裝置其不同方位。設備可能會被轉向不同方位(旋轉90度或其他方位)，而此處所使用之空間相對術語則可相應地進行解讀。
根據一些實施例，提供一種包括多波段內建天線的封裝體(package)及其形成方法。根據一些實施例出示形成封裝體的中間階段，討論了一些實施例的一些變型。本文所討論的實施例將提供範例，以使本揭露之標的得以被製造或使用，且於本揭露所屬技術領域中具通常知識者將能輕易理解，他們可在維持在不同實施例所預期的範圍內的情況下進行修改。綜觀各種示意圖及說明性實施例，相似的參考編號用於指示相似的元件。儘管方法實施例在討論中可被以特定順序執行，但其他方法實施例可以以任何具有邏輯的順序執行。
根據本揭露一些實施例，藉由將射頻積體電路(Radio-Frequency Integrated Circuit,RFIC)晶粒接合(bond)至重佈結構，以形成扇出(fan-out)封裝體。天線基板及封裝組件(例如：印刷電路板)可被接合至重佈結構的相對側。天線的組件可被分配在天線基板、重佈結構、以及封裝組件中。第一距離(介於天線基板與重佈結構之間)及第二距離(介於封裝組件與重佈結構之間)可被選擇，以具有所欲獲得的不同數值。因此，藉由在天線基板、重佈結構、以及封裝組件中選擇性地分配多波段天線的組件，可以訂製多波段天線的頻寬。
第1圖至第6圖係根據本揭露一些實施例所示，形成天線基板之中間階段的截面圖，其中形成有多波段天線的一些部分。相應之製程示意性地反映於第23圖所示的製程流程200中。
參照第1圖，提供了覆蓋式基板(blanket substrate)。覆蓋式基板21包括介電核心20，以及介電核心20相對側上的覆蓋之金屬膜22A及金屬膜22B。根據一些實施例，介電核心20由下列材料形成或包括下列材料：環氧樹脂(epoxy)、樹脂(resin)、預浸體(prepreg，包括環氧樹脂、樹脂及/或玻璃纖維)、樹 脂塗覆的銅(resin coated Copper,RCC)、玻璃、模制化合物(molding compound)、塑膠(例如：聚氯乙烯(PolyVinylChloride,PVC)、丙烯腈-丁二烯-苯乙烯(Acrylonitrile,Butadiene & Styrene,ABS)、聚丙烯(Polypropylene,PP)、聚乙烯(Polyethylene,PE)、聚苯乙烯(PolyStyrene,PS)、聚甲基丙烯酸甲酯(Polymethyl Methacrylate,PMMA)、聚對苯二甲酸乙二酯(Polyethylene Terephthalate,PET)、聚碳酸酯(Polycarbonates,PC)、聚苯硫(Polyphenylene sulfide,PPS)、flex(polyimide，聚酰亞胺)、ABF(Ajinomoto build-up film，味素堆積膜)、BT樹脂、BCB(Benzocyclobutene，苯環丁烯)、陶瓷、PTFE(Polytetrafluoroethylene，聚四氟乙烯)或鐵氟龍(Teflon))、其組合、及其多層。介電核心20亦可由諸如矽的一些其他材料形成。金屬膜22A及金屬膜22B可由銅或其他導電材料形成。介電核心20厚度可以在約200μm(微米)與約600μm之間的範圍內。
參照第2圖，貫穿開口(through-openings，亦可稱為通孔)24，舉例來說，可藉由雷射鑽孔形成(laser drilling)。對應之製程在第23圖所示之製程流程200中被顯示為製程202。貫穿開口24穿過金屬膜22A、金屬膜22B、以及介電核心20。
接著參考第3圖，藉由電鍍(plating)製程以導電材料填充貫穿開口24，以在其中形成通孔電極(through-vias)26(包括通孔電極26A及通孔電極26B)。對應之製程在第23圖所示之製程流程200中被顯示為製程204。可由金屬材料形成通孔電極26，例如銅、鎢(tungsten)、鋁、鈦(titanium)、鎳(nickel)或其合金。電鍍製程可包括形成電鍍遮罩，電鍍遮罩的形成可包括黏附(adhere)及圖案化乾式薄膜(dry film)，或是形成光阻並接之以曝光製程及顯影製程。金屬膜22A及金屬膜22B接著在蝕刻製程中被圖案化以形成導電特徵28(包括導電特徵28A及導 電特徵28B)。對應之製程在第23圖所示之製程流程200中被顯示為製程206。介電核心20之相對側上的導電特徵28可經由通孔電極26互連(interconnect)。導電特徵28A可包括重佈線路(RDL)及金屬墊，並可被用作電性連接線路，為天線的一部分(例如補釘天線(patch antenna)的補釘本體(patch))。舉例來說，通孔電極26A及導電特徵28A可被用於電性連接，其可被連接至所得封裝體100中的裝置晶粒56(第19圖)。導電特徵28B可被用於熱消耗(thermal dissipation)。通孔電極26B及導電特徵28B可被用作熱消耗的熱路徑，其在所得封裝體100(第19圖)中電性浮接(electrically floating)。
第4圖顯示介電遮罩層30A及介電遮罩層30B的形成，其係由焊料抗蝕劑(solder resist)或其他類型之適用的介電材料所形成。對應之製程在第23圖所示之製程流程200中被顯示為製程208。在隨後的製程中，如第5圖所示，介電遮罩層30A及介電遮罩層30B被圖案化，舉例來說，在蝕刻製程中被圖案化，使得一些導電特徵28被曝露出來。對應之製程在第23圖所示之製程流程200中被顯示為製程210。舉例來說，被用作多波段天線之一部分的導電特徵28A的部分可被曝露，以降低訊號隔離(signal isolation)。被用作熱路徑的導電特徵28B可被(或可不被)覆蓋，以減少氧化。金屬防護層(metal finish，未圖示)可接著被形成，例如經由電鍍形成，以防止曝露之導電特徵28氧化。根據本揭露一些實施例，金屬防護層包括或包含：化鎳化鈀浸金(Electroless Nickel Electroless Palladium Immersion Gold,ENEPIG)、有機可焊性防腐劑(Organic Solderability Preservative,OSP)、化鎳浸金(Electroless Nickel Immersion Gold,ENIG)、直接浸金(Direct Immersion Gold,DIG)等。
第6圖顯示電性連接器34的形成。對應之製程在第23圖所示之製 程流程200中被顯示為製程212。電性連接器34的形成可包括再導電特徵28A上放置焊球(solder ball)，並接著使焊球回流(reflow)。根據本揭露替代性實施例，電性連接器34的形成包括執行電鍍製程以在導電特徵28A上形成焊料層，並接著使焊料層回流。電性連接器34亦可包括非焊料金屬支柱(pillar)或金屬支柱，以及非焊料金屬支柱上的焊料覆帽(solder cap)，且可經由電鍍來形成。接著執行切割製程(singulation process)，以將所示的基板切割為多個天線基板38。對應之製程在第23圖所示之製程流程200中被顯示為製程214。天線基板38之所以如此命名，是因為它們包括天線的一些部分。
第7圖及第8圖係根據一些實施例所示，形成裝置晶粒(可為RFIC晶粒)之中間階段的截面圖。對應之製程亦示意性地顯示於第23圖所示之製程流程200中。參照第7圖，提供晶圓40。晶圓40包括半導體基板42，以及形成於半導體基板42之頂部表面的特徵。半導體基板42可由晶態矽、晶態鍺、矽鍺(silicon germanium)等形成。
電路44形成於晶圓40中，且電路44可為RF電路，被配置以產生及/或接收RF訊號。電路44中亦可包括邏輯電路。根據本揭露一些實施例，電路44包括低雜訊放大器(Low Noise Amplifier,LNA)、低損耗濾波器(low-loss filter,)、功率放大器(power amplifier)、基頻帶(Baseband,BB)電路、功率管理積體電路(Power Management Integrated Circuit,PMIC)、記憶體、微機電系統(Micro Electro Mechanical System,MEMS)裝置、及/或其他主動電路(active circuit)。
電路44上方為互連結構46。互連結構46包括金屬線路及通孔(未圖示)，被形成於介電層(亦稱為金屬間介電質(Inter-metal Dielectric,IMD))中。金屬線路及通孔可由銅或銅合金形成，且它們亦可由其他金屬形成。根據本揭露一 些實施例，介電層包括低k值介電材料，低k值介電材料可包括含碳之低k值介電材料、氫矽倍半氧烷(Hydrogen SilsesQuioxane,HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane,MSQ)等。鈍化層(passivation layer)被形成於低k值介電層上，且可由低k值介電材料所形成。表面導電特徵48可為球下金屬層(Under-Bump Metallurgies,UBMs)、金屬墊、金屬支柱等，並被形成於晶圓40的表面處。對應之製程在第23圖所示之製程流程200中被顯示為製程216。
第8圖顯示電性連接器50的形成。對應之製程在第23圖所示之製程流程200中被顯示為製程218。電性連接器50的形成可包括將焊球放置或電鍍在球下金屬層48(或稱為表面導電特徵48)上，並接著使焊球回流。電性連接器50亦可包括非焊料金屬支柱或金屬支柱，以及非焊料金屬支柱上的焊料覆帽，且可經由電鍍來形成。接著執行切割製程，以將晶圓40切割為多個裝置晶粒56。對應之製程在第23圖所示之製程流程200中被顯示為製程220。在說明書的實施例中，裝置晶粒56可替代地被稱為RFIC晶粒56。
第9圖至第19圖根據一些實施例顯示形成封裝體之中間階段的截面圖，其中封裝體包括RF天線。對應之製程亦示意性地反映於第23圖所示之製程流程200中。第9圖顯示載體(carrier)60及設置於載體60上的脫離薄膜(release film)62。載體60可為玻璃載體、陶瓷載體等。載體60可具有在俯視下為圓形或矩形形狀，並可具有矽晶圓的尺寸。脫離薄膜62可由基於聚合物的材料(例如：光熱轉換(Light-To-Heat-Conversion,LTHC)材料)形成，其可與載體60一同自將於後續階段中形成的覆蓋結構(overlying structure)中移除。根據本揭露一些實施例，脫離薄膜62由基於環氧基之熱釋放(epoxy-based thermal-release)材料形成。在其他實施例中，脫離薄膜62由紫外線(UV)膠形成。脫離薄膜62可以以可流動 的形式分配然後固化。
介電緩衝層64被形成於脫離薄膜62上。根據本揭露一些實施例，介電緩衝層64由諸如聚合物的有機材料形成，其亦可為光敏性材料，例如聚苯并
Figure 108148050-A0305-02-0012-1
唑(polybenzoxazole,PBO)、聚酰亞胺(polyimide,PI)、苯並環丁烯(Benzocyclobutene,BCB)等。介電緩衝層64可經由曝光及顯影來圖案化。根據本揭露之替代性實施例，介電緩衝層64由無機材料形成，該無機材料可為諸如氮化矽的氮化物、諸如氧化矽的氧化物、磷矽酸鹽玻璃(PhosphoSilicate Glass,PSG)、硼矽玻璃(BoroSilicate Glass,BSG)、硼摻雜之磷矽酸鹽玻璃(Boron-doped PhosphoSilicate Glass,BPSG)等、其組合、及/或其多層。
介電層66被形成於介電緩衝層64上，並接著被圖案化。對應之製程在第23圖所示之製程流程200中被顯示為製程222。根據本揭露一些實施例，介電層66由諸如聚合物的有機材料形成，其可為諸如PBO、聚酰亞胺(PI)、BCB(苯並環丁烯)之光敏性聚合物，或是包括環氧樹脂、樹脂、預浸體(包括環氧樹脂、樹脂及/或玻璃纖維)、玻璃、模制化合物、塑膠(例如：聚氯乙烯(PVC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚丙烯(PP)、聚乙烯(PE)、聚苯乙烯(PS)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚苯硫(PPS)、flex(聚酰亞胺)、ABF(味素堆積膜)、雙馬來亞醯胺三嗪(Bismaleimide Triazine,BT)樹脂、BCB(苯環丁烯)、陶瓷、聚四氟乙烯(PTFE)或鐵氟龍(Teflon))等。根據本揭露之替代性實施例，介電層66由無機材料形成，該無機材料可為諸如氮化矽的氮化物、諸如氧化矽的氧化物、磷矽酸鹽玻璃(PSG)、硼矽玻璃(BSG)、硼摻雜之磷矽酸鹽玻璃(BPSG)等。介電層66接著被圖案化以形成開口68。
參照第10圗，重佈線路70被形成。重佈線路70可包括重佈線路 70A，以及在重佈線路70A下方且連接至重佈線路70A的金屬墊70B。對應之製程在第23圖所示之製程流程200中被顯示為製程224。重佈線路70的形成可包括在介電緩衝層64上形成金屬種晶層(metal seed layer，未圖示)、在金屬種晶層上形成諸如光阻的圖案化遮罩(未圖示)、以及接著在曝露的種晶層上執行金屬電鍍製程。然後移除圖案化遮罩，並接著移除種晶層先前由被移除之圖案化遮罩所覆蓋的部分，留下如第10圗之重佈線路70。根據本揭露一些實施例，種晶層包括鈦層以及在鈦層上方的銅層。種晶層之形成，舉例來說，可使用物理氣相沉積(Physical Vapor Deposition,PVD)。電鍍的執行，舉例來說，可使用無電式電鍍(electro-less plating)、電化學電鍍(electro-chemical plating)等。
接下來，介電層74被形成於重佈線路70上，如第11圗所示。介電層74之底部表面與重佈線路70及介電層66之頂部表面接觸。根據本揭露一些實施例，介電層74的材料選自與形成介電層66之候選材料相同的一組材料，且可選自PBO、聚酰亞胺、氮化矽、氧化矽等。介電層74可接著被圖案化以形成開口，經由這些開口，重佈線路70A的一些部分被曝露。
第12圖顯示附加之介電層74及重佈線路76的形成。附加之介電層74及重佈線路76的形成製程在第23圖所示之製程流程200中被顯示為製程226。附加之介電層74的材料及形成製程與介電層64相似。重佈線路76的材料及形成製程與重佈線路70相似。因此，此處不再重複附加之介電層74及重佈線路76之製程的細節。重佈線路76的頂層可被用於電性路由(routing)及/或接合(bonding)。在說明書的實施例中，介電層64、介電層66、介電層74以及重佈線路70(含金屬墊)與重佈線路76共同被稱為重佈結構77。
第13圖顯示金屬支柱78的形成。對應之製程在第23圖所示之製程 流程200中被顯示為製程228。金屬支柱78可包括銅、鎳、鈀、焊料、其合金、及/或其多層。根據本揭露一些實施例，金屬支柱78的形成包括形成覆蓋之種晶層(未圖示)、形成圖案化之電鍍遮罩80、以及在電鍍遮罩80中的開口82中電鍍金屬支柱78，其中圖案化之電鍍遮罩80由光阻所形成並經由曝光及顯影進行圖案化。金屬種晶層可包括鈦層及在鈦層之上的銅層，兩者皆可經由PVD形成。接下來，移除電鍍遮罩80，並蝕刻金屬種晶層先前由電鍍遮罩80所覆蓋的部分，留下金屬支柱78。所得的結構顯示於第14圖。根據替代性實施例，金屬種晶層並未被形成，且金屬支柱78是經由曝露於開口82之重佈線路76的曝露部分所電鍍。在電鍍遮罩80移除後，所得之結構亦相似於第14圖所示之結構。
參照第15圖，RFIC晶粒56被接合至重佈結構77，舉例來說，經由焊料區域接合，其中焊料區域被回流以連接RFIC晶粒56與重佈線路76。對應之製程在第23圖所示之製程流程200中被顯示為製程230。根據本揭露一些實施例，黏著(adhesive)薄膜84被附接到RFIC晶粒56的背部表面。黏著薄膜84可在晶圓40的切割製程(如第8圖所示)之前被附接到RFIC晶粒56，並與晶圓40一起被切割。因此，黏著薄膜84具有與RFIC晶粒56之對應邊緣齊平的邊緣。應理解的是，儘管出示了一個金屬支柱78，但在製造製程中，可形成複數金屬支柱78，其可以以環狀的方式對準，且RFIC晶粒56可被以環狀包圍。
此外，作為範例，一個RFIC晶粒被顯示為接合至重佈結構77。可能會有複數裝置晶片及獨立的被動元件被接合至重佈線路70，它們在第22A圖中被繪製為裝置晶粒57及獨立被動元件122以作為範例。這些晶粒可包括但不限於：包括LNAs、低損耗濾波器、功率放大器、基頻帶電路、功率管理積體電路、記憶體、微機電系統裝置、及/或其他主動電路的晶粒。
第16圖顯示將天線基板38接合至重佈結構77上。對應之製程在第23圖所示之製程流程200中被顯示為製程232。第16圖所示之天線基板38為示意性的，並未出示其中的一些細節，且天線基板38可具有如第6圖所示的結構。根據本揭露一些實施例，經由電性連接器34進行接合，電性連接器34可包括焊料區域。當黏著薄膜84在RFIC晶粒56上時，天線基板38之底部表面可與黏著薄膜84接觸。黏著薄膜84具有兩種功能。首先，它填充RFIC晶粒56與天線基板38之間的間隙。此間隙對後續之密封材料(encapsulant)86(第17圖)而言可能小至無法填充，而黏著薄膜84的使用防止此無法填充之微小間隙的形成。其次，它有助於保持天線基板38與金屬支柱78之間的間隔距離，並進而防止電性連接器34中的焊料被壓碎。RFIC晶粒56可與天線基板38重疊。此外，天線基板38的尺寸小於下方之重佈結構77，使得重佈結構77的某些部分未被天線基板38所覆蓋，因此重佈結構77的這些部分可被用作天線的一部分。
接下來，同樣如第17圖所示，密封材料86被設置以在其中密封天線基板38、RFIC晶粒56及金屬支柱78，並接著進行固化(cure)。對應之製程在第23圖所示之製程流程200中被顯示為製程234。密封材料86填充RFIC晶粒56與天線基板38之間的間隙。密封材料86可包括模制化合物、模制底膠(molding underfill)、環氧樹脂、及/或樹脂。根據本揭露一些實施例，密封材料86包括基礎材料以及基礎材料中的填充劑顆粒(filler particle)。基礎材料可為環氧樹脂、樹脂、聚合物等。填充劑顆粒可為二氧化矽、氧化鋁等之球形顆粒。密封(encapsulation)製程可藉由暴露成型(expose molding)來執行，其中將脫離薄膜(未圖示)壓在天線基板38上，以防止密封材料86成型在天線基板38上。當黏著薄膜84被形成時，密封材料86亦圍繞黏著薄膜84。否則，當黏著薄膜84未被形成時， 將密封材料86填充到RFIC晶粒56與天線基板38之間的間隙中。在說明書之實施例中，覆蓋在脫離薄膜62上的結構及組件，被合稱為重建晶圓(reconstructed wafer)88。
接下來，重建晶圓88自載體60被去接合(de-bond)。對應之製程在第23圖所示之製程流程200中被顯示為製程236。根據本揭露一些實施例，為了去接合重建晶圓88，光束被投射在脫離薄膜62上，且光穿過透明載體60。根據本揭露一些實施例，光包括雷射束，雷射束掃描遍及整個脫離薄膜62。作為曝光(例如：雷射掃描)的結果，可將載體60自介電緩衝層64上抬起，並因此將重建晶圓88自載體60上去接合(卸下)。在曝光期間，脫離薄膜62響應於曝光所引入的熱量而分解，進而使載體60與重建晶圓88分離。所得之重建晶圓88如第18圖所示。
第18圖進一步顯示電性連接器90的形成，其可包括焊料區域。對應之製程在第23圖所示之製程流程200中被顯示為製程238。接下來，可將重建晶圓88放置在膠帶(tape，未圖示)上，該膠帶被附接到切割框架(dicing frame，未圖示)上。重建晶圓88接著被切割為複數封裝體92，舉例來說，在鋸切製程(sawing process)中切割。對應之製程在第23圖所示之製程流程200中被顯示為製程240。
第19圖顯示經由焊料區域90(或稱電性連接器90)將封裝體92接合至封裝組件94，並藉此形成封裝體100。根據一些實施例，封裝組件94為印刷電路板、其他封裝體、封裝基板、插入器(interposer)等。底膠(underfill，未圖示)可被設置於封裝體92與封裝組件94之間，以保護焊料區域90。所得之封裝體100為多波段天線封裝體，包括其中的多波段之天線104及多波段之天線106。
根據本揭露一些實施例，封裝體100包括天線104，天線104包括 補釘本體(patch)76A及反射器(reflector)102。補釘本體76A為重佈線路76的一部分，位於重佈結構77中。補釘本體76A亦經由其間的饋線(feed line)與RFIC晶粒56電性地且訊號地連接，其中饋線包括重佈線路76的一些部分。天線104的反射器104可電性接地(electrically grounded)，舉例來說，經由焊料區域90、重佈線路70、介電層74、以及電性連接器50以連接至RFIC晶粒56中的電接地。反射器102被形成於封裝組件94的選擇層中，舉例來說，在頂層、底層或它們之間的任何其他層中。補釘本體76A與反射器102之間的間隔S1可處於約10μm至約600μm之間的範圍內。除了替焊料區域90的高度選擇適當的數值外，補釘本體76A及反射器102的位置亦可被選擇，以將間隔S1調整為期望的數值。
根據一些實施例，封裝體100亦包括天線106。天線106包括補釘本體28A1及反射器76B，其中反射器76B為重佈線路76的一部分。補釘本體28A1為天線基板38中之導電特徵28的一部分。補釘本體28A1亦經由其間的饋線與RFIC晶粒56電性地且訊號地連接，其中饋線包括重佈線路76的一些部分、金屬支柱78、電性連接器34、以及導墊特徵28A的一部分。反射器76B電性接地，舉例來說，經由重佈線路76以連接至RFIC晶粒56中的接地。補釘本體28A1與反射器76B之間的間隔S2可處於約10μm至約600μm之間的範圍內。除了調整電性連接器34及金屬支柱78的高度外，補釘本體28A1及反射器76B的位置亦可被選擇，以將間隔S2調整為適當的數值。由於每個天線104及天線106之面積及間隔的調整上的彈性，天線104的中心頻率可等於、高於、或是低於天線106的中心頻率，且天線104的頻寬可寬於、等於、或是窄於天線106的頻寬。
根據本揭露一些實施例，天線106更包括補釘本體28A2，補釘本體28A2為電性浮接的。因此，天線106包括堆疊之補釘本體28A2及補釘本體 28A1，使得天線106的頻寬可進一步增加。根據替代性實施例，並不會形成補釘本體28A2。因此，補釘本體28A2使用虛線繪製，以顯示根據不同實施例，它可被形成或可不被形成。
如第19圖所示，根據一些實施例，天線104自天線基板38偏移(offset)，因此天線基板38並未覆蓋天線104，且因此並未不利地阻擋天線104向上接收或發射訊號。根據替代性實施例，當基天線基板38的材料不會顯著影響天線104時，天線基板38可更多地延伸以覆蓋天線104，且虛線87出示了介電核心20以及介電遮照層30A及介電遮罩層30B可以延伸到的位置。因此，密封材料86、天線基板38及重佈結構77的左側邊緣可以彼此齊平，且密封材料86、天線基板38及重佈結構77的右側邊緣可以彼此齊平。相似之虛線87亦顯示於第20圖、第21圖、以及第22A圖。另一方面，RFIC晶粒56可與天線基板38重疊。每個天線104及天線106可為補釘天線或端射天線(end-fire antenna)。根據一些實施例，天線104為補釘天線，且它的訊號方向為向上方向。天線106亦可為端射天線，根據本揭露一些實施例，它可被形成於重佈結構77及天線基板38的右側末端，以允許訊號發射方向朝向天線106的右側。
根據一些實施例，天線104及天線106的(俯視)面積影響各自之天線的中心頻率，且面積越大，中心頻率越高。另一方面，間隔S1及間隔S2可影響各自之天線104及天線106的頻寬，且間隔S1及間隔S2越大，對應之頻寬就越大。根據本揭露一些實施例，可以獨立地調整每個間隔S1及間隔S2且不影響彼此，盡而允許獨立地將各自之天線104及天線106的頻寬調整在期望的範圍內。間隔S1及間隔S2可以彼此不同或彼此相等。而且，天線104及天線106的面積亦可被獨立地調整，盡而允許各自之天線104及天線106的中心頻率數值被獨立地 調整。因此，天線104及天線106可具有不同的頻帶(band)，並共同形成多波段天線。
應注意的是，採用根據本揭露實施例的結構，可藉由移動天線組件的位置來達到不同的間隔。舉例來說，第20圖及第21圖顯示根據本揭露一些實施例的封裝體100。除非另有說明，否則這些實施例中的組件的材料及形成製程，與相似之組件基本相同，相似之組件在第1圖至第19圖所示之前述實施例中，由相同的參考符號表示。因此，可在前述實施例之討論中，找到關於第20圖及第21圖所示之組件的形成製程及材料的細節。
參照第20圖，天線106的反射器120並非形成於重佈結構77中(如第19圖之反射器76B所示)，而是形成於封裝組件94中。這顯著地增加了間隔S2’，間隔S2’為補釘本體28A1與反射器120之間的間隔。根據本揭露一些實施例，間隔S2’處於約20μm與約1,200μm之間的範圍內。在補釘本體28A1與反射器120之間沒有導電特徵。間隔S2’的增加可使天線106的頻寬增加，因此當需要大頻寬時可以使用天線106。此外，補釘本體28A2可被形成也可不被形成，且用虛線表示。
參照第21圖，天線106的反射器120並非形成於重佈結構77中，而是也形成於封裝組件94中。此外，補釘本體28A3被形成於天線基板38的頂部側，且連接至補釘本體28A3的饋線包括金屬支柱78、焊料區域34(或稱電性連接器34)、導電特徵28A、以及天線基板38中的通孔電極26A。這顯著地增加了間隔S2”，間隔S2”為補釘本體28A3與反射器120之間的間隔。根據本揭露一些實施例，間隔S2”處於約20μm與約1,700μm之間的範圍內。在補釘本體28A3與反射器120之間沒有導電特徵。間隔S2”的增加可使天線106的頻寬進一步增加，因此當需要大頻寬時可以使用天線106。
第22A圖顯示接合至重佈結構的附加之裝置晶粒57。接合可經由金屬支柱78’為之，金屬支柱78’將裝置晶粒57連接到天線基板38。根據一些實施例，裝置晶粒57亦為RFIC晶粒。每個天線104及天線106可電性連接至裝置晶粒56與裝置晶粒57的其中一個。根據其他實施例，裝置晶粒57包括RFIC電路以外的其他電路，且其他電路包括但不限於：LNA、低損耗濾波器、功率放大器、功率管理積體電路、記憶體、微機電系統裝置、及/或其他邏輯電路。獨立被動元件(Independent Passive Device,IPD)122(可為電容器、電感器、電阻器等)可被接合至重佈結構77以增強信號。
第22B圖顯示如第22A圖所示之封裝體100的平面圖。第22A圖所示之截面圖取自第22B圖之參考截面22A-22A。存在複數金屬支柱78(以及對應之焊料區域34)，環繞RFIC晶粒56及裝置晶粒57呈環狀排列。亦出示了補釘本體76A及補釘本體28A1。
在前述實施例中，根據本揭露一些實施例討論了一些製程及特徵，以形成三維(3D)封裝體。其他特徵及製程亦包括在內。舉例來說，可包括測試結構以輔助3D封裝體或3DIC裝置的驗證測試。舉例來說，測試結構可包括形成於重佈層中或基板上的測試墊，其允許使用探針及/或探針卡等對3D封裝體或3DIC進行測試。驗證測試可在中間結構以及最終結構上執行。此外，本文所揭露之結構及方法，可與結合了已知合格晶粒(known good die)之中間驗證的測試方法結合使用，以增加產量並降低成本。
本揭露實施例具有一些有益的特徵。藉由利用一個封裝體中不同的封裝組件來形成具有不同間隔的天線，天線之頻寬可被設計為具有期望的數值。藉由在所選的位置設置天線的組件，可達成不同的間隔。此外，藉由採用 堆疊式補釘天線可達成較寬的頻寬。因此，可在不犧牲天線之中心頻率及頻寬的情況下，將多波段天線整合到同一個封裝體中。
根據本揭露一些實施例提供一種封裝方法。上述封裝方法包括將一天線基板接合至一重佈結構，其中上述天線基板包括第一天線的第一部分，而上述重佈結構包括第一天線的第二部分；將上述天線基板密封於密封材料中；以及將一封裝組件接合至上述重佈結構，其中上述重佈結構與上述天線基板中的一者包括第二天線的第三部分，而上述封裝組件包括第二天線的第四部分。在一個實施例中，上述封裝方法更包括將一RFIC晶粒接合至上述重佈結構，其中上述RFIC晶粒電性耦接至第一天線與第二天線中的至少一者。在一個實施例中，上述封裝方法更包括將一黏著薄膜黏附至上述RFIC晶粒上，其中上述黏著薄膜具有接觸上述RFIC晶粒及上述天線基板的相對表面。在一個實施例中，上述天線基板及上述封裝組件接合至上述重佈結構的相對側邊。在一個實施例中，第一天線的第一部分包括一補釘本體，而第一天線的第二部分包括一接地反射器。在一個實施例中，第二天線的第三部分包括一補釘本體，而第二天線的第四部分包括一接地反射器。在一個實施例中，上述封裝方法更包括形成上述重佈結構，包括：形成複數重佈線路，其中第一天線之第一部分及第二天線之第三部分在上述重佈線路中；以及在上述重佈線路之一者上形成一金屬支柱，其中上述天線基板被接合至上述金屬支柱。在一個實施例中，上述封裝方法更包括形成上述天線基板，包括：在一覆蓋式基板中形成複數通孔，其中上述覆蓋式基板包括一介電核心，以及在上述介電核心之相對側的複數金屬薄膜；填充上述通孔以形成複數通孔電極；以及蝕刻上述金屬薄膜以形成連接至上述通孔電極的複數重佈線路。
根據本揭露一些實施例提供一種封裝方法。上述封裝方法包括將一RFIC晶粒接合至一重佈結構；將一天線基板接合至上述重佈結構；以及將一印刷電路板接合至上述重佈結構，其中上述重佈結構、上述天線基板、以及上述印刷電路板中的每一者，包括第一天線及第二天線中的一者或兩者的至少一個組件，其中第一天線包括第一補釘本體及第一反射器，且第一補釘本體與第一反射器之間具有第一間隔，而第二天線包括第二補釘本體及第二反射器，且第二補釘本體與第二反射器之間具有第二間隔，其中第一間隔不同於第二間隔。在一個實施例中，上述封裝方法更包括將第一天線的複數第一組件分配至上述重佈結構及上述天線基板，以及將第二天線的複數第二組件分配至上述重佈結構及上述印刷電路板。在一個實施例中，上述封裝方法更包括形成上述重佈結構，包括：形成複數介電層；以及形成複數重佈線路，其中第一天線及第二天線在上述重佈結構中的部分為上述重佈線路的一部分。在一個實施例中，上述封裝方法更包括在上述重佈線路中的一頂部重佈線路上形成一金屬支柱，其中上述天線基板中的一導電特徵被接合至上述金屬支柱。在一個實施例中，上述導電特徵連接至第一天線中的補釘本體。在一個實施例中，上述重佈結構經由複數焊料區域接合至上述印刷電路板，且第二天線的一組件在上述印刷電路板中，且經由上述焊料區域中的一者連接至上述射頻積體電路晶粒。
根據本揭露一些實施例提供一種封裝體。上述封裝體包括一重佈結構；一天線基板，接合至上述重佈結構；以及一印刷電路板，接合至上述重佈結構，其中上述重佈結構、上述天線基板、以及上述印刷電路板共同形成第一天線及第二天線，其中上述重佈結構、上述天線基板、以及上述印刷電路板中的每一者，包括第一天線及第二天線中的一者或兩者的至少一個組件。在一 個實施例中，第一天線包括第一補釘本體及第一反射器，第一補釘本體與第一反射器之間具有第一間隔，而第二天線包括第二補釘本體及第二反射器，第二補釘本體與第二反射器之間具有第二間隔，且第一間隔不同於第二間隔。在一個實施例中，上述封裝體更包括一射RFIC晶粒，接合至上述重佈結構，其中上述RFIC晶粒電性耦接至第一天線及第二天線中的至少一者。在一個實施例中，上述封裝體更包括一黏著薄膜，包括第一表面及相對的第二表面，第一表面接觸上述射頻積體電路晶粒，而第二表面接觸上述天線基板；以及一密封材料，其中密封有上述天線基板及上述射頻積體電路晶粒。在一個實施例中，上述密封材料的頂部表面基本上與上述天線基板的頂部表面共面。在一個實施例中，第一天線包括一補釘天線，其中上述天線基板包括上述補釘天線的一補釘本體，且上述重佈結構及上述印刷電路板中的一者包括上述補釘天線的一反射器。
前述內文概述多項實施例之特徵，如此可使於本技術領域中具有通常知識者更佳地瞭解本揭露之態樣。本技術領域中具有通常知識者應當理解他們可輕易地以本揭露為基礎設計或修改其他製程及結構，以完成相同之目的及/或達到與本文介紹之實施例或範例相同之優點。本技術領域中具有通常知識者亦需理解，這些等效結構並未脫離本揭露之精神及範圍，且在不脫離本揭露之精神及範圍之情況下，可對本揭露進行各種改變、置換以及變更。
20:介電核心
28A:導電特徵
30A、30B:介電遮罩層
34:電性連接器
38:天線基板
42:半導體基板
44:電路
46:互連結構
48:表面導電特徵
50:電性連接器
56:裝置晶粒
64:介電緩衝層
66:介電層
70:重佈線路
74:介電層
76:重佈線路
77:重佈結構
78:金屬支柱
84:黏著薄膜
86:密封材料
90:電性連接器
92:封裝體
87:虛線
94:封裝組件
100:封裝體
102:反射器
104、106:天線
S1、S2:間隔
76A:補釘本體
76B:反射器
28A1、28A2:補釘本體

Claims (9)

  1. 一種封裝方法，包括：形成一重佈結構，其中形成上述重佈結構的操作包括：形成複數重佈線路；以及在上述重佈線路之一者上形成一金屬支柱；將一天線基板接合至上述重佈結構，並且上述天線基板中的一導電特徵被接合至上述金屬支柱，其中上述天線基板包括一第一天線的一第一部分，而上述重佈結構包括上述第一天線的一第二部分；將上述天線基板密封於一密封材料中；以及將一封裝組件接合至上述重佈結構，其中上述重佈結構與上述天線基板中的一者包括一第二天線的一第三部分，而上述封裝組件包括上述第二天線的一第四部分，其中上述第一天線之上述第二部分及上述第二天線之上述第三部分在上述重佈線路中，其中上述導電特徵連接至上述第一天線中的上述第一部分。
  2. 如申請專利範圍第1項所述之封裝方法，更包括將一射頻積體電路(RFIC)晶粒接合至上述重佈結構，其中上述射頻積體電路晶粒電性耦接至上述第一天線與上述第二天線中的至少一者。
  3. 如申請專利範圍第1項所述之封裝方法，其中上述第一天線的上述第一部分及上述第二天線的上述第三部分各包括一補釘本體，而上述第一天線的上述第二部分及上述第二天線的上述第四部份各包括一接地反射器。
  4. 如申請專利範圍第1項所述之封裝方法，更包括形成上述天線基板，其中形成上述天線基板的操作包括：在一覆蓋式基板中形成複數通孔，其中上述覆蓋式基板包括一介電核心，以 及在上述介電核心之相對側的複數金屬薄膜；填充上述通孔以形成複數通孔電極；以及蝕刻上述金屬薄膜以形成連接至上述通孔電極的複數重佈線路。
  5. 一種封裝方法，包括：形成一重佈結構，其中形成上述重佈結構的操作包括：形成複數介電層；形成複數重佈線路；以及在上述重佈線路中的一頂部重佈線路上形成一金屬支柱；將一射頻積體電路(RFIC)晶粒接合至上述重佈結構；將一天線基板接合至上述重佈結構，其中上述天線基板中的一導電特徵被接合至上述金屬支柱；以及將一印刷電路板接合至上述重佈結構，其中上述重佈結構、上述天線基板、以及上述印刷電路板中的每一者，包括一第一天線及一第二天線中的一者或兩者的至少一個組件，其中上述第一天線包括一第一補釘本體及一第一反射器，且上述第一補釘本體與上述第一反射器之間具有一第一間隔，而上述第二天線包括一第二補釘本體及一第二反射器，且上述第二補釘本體與上述第二反射器之間具有一第二間隔，其中上述第一間隔不同於上述第二間隔，其中上述第一天線及上述第二天線在上述重佈結構中的部分為上述重佈線路的一部分，其中上述導電特徵連接至上述第一天線中的上述第一補釘本體。
  6. 如申請專利範圍第5項所述之封裝方法，更包括將上述第一天線的複數第一組件分配至上述重佈結構及上述天線基板，以及將上述第二天線的複 數第二組件分配至上述重佈結構及上述印刷電路板。
  7. 一種封裝體，包括：一重佈結構，具有形成複數重佈線路，其中上述重佈線路中的一頂部重佈線路上設置有一金屬支柱；一天線基板，接合至上述重佈結構，其中上述天線基板中的一導電特徵被接合至上述金屬支柱；以及一印刷電路板，接合至上述重佈結構，其中上述重佈結構、上述天線基板、以及上述印刷電路板共同形成一第一天線及一第二天線，其中上述重佈結構、上述天線基板、以及上述印刷電路板中的每一者，包括上述第一天線及上述第二天線中的一者或兩者的至少一個組件，其中上述第一天線包括一第一補釘本體及一第一反射器，並且上述導電特徵連接至上述第一天線中的上述第一補釘本體。
  8. 如申請專利範圍第7項所述之封裝體，其中上述第一補釘本體與上述第一反射器之間具有一第一間隔，而上述第二天線包括一第二補釘本體及一第二反射器，上述第二補釘本體與上述第二反射器之間具有一第二間隔，且上述第一間隔不同於上述第二間隔。
  9. 如申請專利範圍第7項所述之封裝體，更包括：一射頻積體電路(RFIC)晶粒，接合至上述重佈結構，其中上述射頻積體電路晶粒電性耦接至上述第一天線及上述第二天線中的至少一者；一黏著薄膜，包括一第一表面及相對的一第二表面，上述第一表面接觸上述射頻積體電路晶粒，而上述第二表面接觸上述天線基板；以及一密封材料，上述密封材料中密封有上述天線基板及上述射頻積體電路晶 粒，其中上述密封材料的頂部表面基本上與上述天線基板的頂部表面共面。
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