US9991216B2 - Antenna cavity structure for integrated patch antenna in integrated fan-out packaging - Google Patents

Antenna cavity structure for integrated patch antenna in integrated fan-out packaging Download PDF

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US9991216B2
US9991216B2 US15/621,084 US201715621084A US9991216B2 US 9991216 B2 US9991216 B2 US 9991216B2 US 201715621084 A US201715621084 A US 201715621084A US 9991216 B2 US9991216 B2 US 9991216B2
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layer
rdl
forming
structures
die
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US20170278808A1 (en
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Wen-Shiang Liao
Chewn-Pu Jou
Feng Wei KUO
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • LTCC Low Temperature Co-Fired Ceramic
  • PCB printed circuit board
  • FIG. 1 is a cross-sectional view illustration of a portion of a 2.5D/3D IC package in which one or more of the metal wiring bead of the present disclosure can be incorporated according to some embodiments.
  • FIG. 3 shows a one-layer metal wiring bead according to some embodiments.
  • FIGS. 5A and 5B show two-layer metal wiring beads embodiments according to some embodiments.
  • FIGS. 7A and 7B show a two-layer metal wiring bead according to some embodiments.
  • FIG. 9 shows another three-layer metal wiring bead according to some embodiments.
  • FIG. 11 shows plots of R, XL, Z performance values from a simulation of a metal wiring bead according to some embodiments of the present disclosure.
  • FIG. 32A is an illustration of an antenna cavity formed by a single solid wall structure according to some embodiments.
  • FIG. 32B is an illustration of an antenna cavity formed by two or more continuous solid segments according to some embodiments.
  • FIGS. 33A-33B show a flow chart of the method of manufacturing the InFO package in accordance with some embodiments.
  • Some embodiments of the present disclosure relate to an impedance element, in particular, relates to an element which is used as a bead filter or a noise filter to eliminate power noise and suppress electromagnetic interference in integrated circuit (IC) devices.
  • IC integrated circuit
  • Integrated fan-out (InFO) packages can be integrated with antenna structures such as patch antennas that are coupled to an RF IC die through a feed structure that is directly connected to the RF IC die.
  • antenna structures such as patch antennas that are coupled to an RF IC die through a feed structure that is directly connected to the RF IC die.
  • one or more antenna can be integrated with the RF IC die through an integrated fan-out redistribution structures comprising a metallization layer (e.g. a redistribution layer) coupled to a package molding compound with the RF IC die embedded therein.
  • a metallization layer e.g. a redistribution layer
  • the interposer 120 comprises a multiple layers of wiring structures.
  • the multiple layers of wiring structures comprise a plurality of wiring layers 122 , 124 , and 126 and via layers 121 , 123 and 125 .
  • the wiring layers 122 , 124 , and 126 each comprises various wiring structures formed from conductor materials M 1 , M 2 , M 3 , corresponding to the wiring layers 122 , 124 , 126 respectively, disposed in a dielectric material.
  • the via layers 121 , 123 and 125 each comprises a plurality of vias generally referred to herein as V 1 , V 2 , V 3 , respectively, disposed in a non-ferrite polymeric dielectric material.
  • the vias provide the electrical connection between the wiring layers.
  • the vias V 1 in the first via layer 121 provide the electrical connection between the wiring structures of the first wiring layer 122 and the IC device 110 .
  • the conductor materials M 1 , M 2 , M 3 are copper-based metal and the dielectric material is one or more types of polymers.
  • the conductor materials M 1 , M 2 , and M 3 generally are the same materials but they can be different.
  • FIG. 2 is a schematic illustration of an example of a 2.5D IC package 200 in which one or more of the metal wiring bead of the present disclosure can be incorporated.
  • the IC package 200 comprises an interposer 220 to which one or more IC devices 201 , 202 , and 203 are attached on one side and one or more IC devices 204 and 205 are attached on the second side.
  • One or more of the metal wiring bead of the present disclosure can be incorporated in the interposer 220 .
  • FIG. 3 shows a one-layer embodiment of a metal wiring bead A according to an aspect of the present disclosure.
  • the metal wiring bead A has a convoluted wiring pattern that is formed in one of the three wiring layers 122 , 124 or 126 from the corresponding M 1 , M 2 or M 3 conducting material.
  • the convoluted wiring pattern of the metal wiring bead A has a serpentine-like portion A 1 that begins at first terminal segment A 2 and ends at a second terminal segment A 3 .
  • the serpentine-like portion A 1 is a wiring trace of the conductor material provided in a meandering serpentine-like pattern.
  • the two terminal segments A 2 and A 3 provide electrical connection to the functional power lines in the IC package.
  • the term “serpentine-like” is used to describe the generally winding shape represented by the portion A 1 where the metal wiring is winding back and forth similar to the shape formed by the body of a moving serpent.
  • FIG. 4 shows another one-layer embodiment of a metal wiring bead B.
  • the metal wiring bead B has a convoluted wiring pattern that is formed in one of the three wiring layers 122 , 124 or 126 from the corresponding M 1 , M 2 or M 3 conducting material.
  • the convoluted wiring pattern of the metal wiring bead B has a meandering loop portion B 1 that begins at a first terminal segment B 2 , follows a square or quadrilateral outline and loops back towards the first terminal segment and ends at a second terminal segment B 3 .
  • the conductive line tracing in the meandering loop portion B 1 meanders in right angles, but the meandering pattern of the conductive line trace can be in any shape.
  • the two terminal segments B 2 and B 3 are connected to the functional power lines in the IC package.
  • FIGS. 6A and 6B show another two-layer metal wiring bead embodiment D.
  • the metal wiring bead D has a convoluted wiring pattern having a quadrilateral outline that has a first set of a plurality of line segments D 1 formed from the M 1 conducting material in the first wiring layer 122 and a second set of a plurality of line segments D 2 formed from the M 2 conducting material in the second wiring layer 124 .
  • a plurality of vias D-via in the via layer 123 provide the electrical connection between the first set of line segments D 1 and the second set of line segments D 2 and form a serpentine-like convoluted pattern for the metal wiring bead D.
  • the first set of line segments D 1 and the second set of line segments D 2 are in a staggered arrangement as shown and the vias D-via connect each of the line segments in the first set D 1 and the second set D 2 to two line segments in the other set.
  • the line segment 10 in the first set D 1 is connected to two of the line segments 31 and 32 in the second set D 2 by the vias 21 and 22 .
  • the line segment 12 located at the corner of the square-shaped outline of the metal wiring bead D The only difference is that the line segment 12 has a bend in the middle of the segment to form the corner section of the metal wiring bead D.
  • the vias D-via are configured to extend not only in the Z-direction (i.e., the direction orthogonal to the plane of the wiring layers) but also extend along the direction parallel to the plane of the wiring layers. In the illustrated example of vias 21 and 22 , they extend along Y-direction for a distance of d to make the connection between the line segment 10 and the line segments 31 and 32 .
  • Two terminal segments D 3 and D 4 provide the electrical connection to the functional power lines for the IC package.
  • the terminal segment D 3 is formed from the M 1 conducting material in the first wiring layer 122 and the terminal segment D 4 is formed from the M 2 conducting material in the second wiring layer 124 .
  • FIG. 5B shows an isometric view illustration of the metal wiring bead D.
  • FIGS. 7A and 7B show another two-layer metal wiring bead embodiment E.
  • the metal wiring bead E has a convoluted wiring pattern that forms a serpentine-like that has a first set of a plurality of line segments E 1 formed from the M 1 conducting material in the first wiring layer 122 and a second set of a plurality of line segments E 2 formed from the M 2 conducting material in the second wiring layer 124 .
  • a plurality of vias E-via in the via layer 123 provide the electrical connection between the first set of line segments E 1 and the second set of line segments E 2 and form a serpentine-like convoluted pattern for the metal wiring bead E.
  • FIG. 8 shows a three-layer metal wiring bead embodiment F according to an aspect of the present disclosure.
  • the metal wiring bead F comprises a convoluted wiring pattern that forms a serpentine-like structure in each of the three wiring layers 122 , 124 , and 126 that are electrically connected in series.
  • a first serpentine-like portion F 1 is formed from the M 1 conductor material.
  • a second serpentine-like portion F 2 is formed from the M 2 conductor material.
  • a third serpentine-like portion F 3 is formed from the M 3 conductor material.
  • FIG. 9 shows another three-layer metal wiring bead embodiment G according to another aspect of the present disclosure.
  • the metal wiring bead G comprises a convoluted wiring pattern in each of the three wiring layers 122 , 124 , and 126 that are electrically connected in series.
  • a first convoluted wiring pattern G 1 is formed from the M 1 conductor material.
  • a second convoluted wiring pattern G 2 is formed from the M 2 conductor material.
  • a third convoluted wiring pattern G 3 is formed from the M 3 conductor material.
  • the electrical connection between the first convoluted wiring pattern G 1 and the second convoluted wiring pattern G 2 is provided by a via G-vial provided in the via layer 123 .
  • the electrical connection between the second convoluted wiring pattern G 2 and the third convoluted wiring pattern G 3 is provided by a via G-via 2 provided in the via layer 125 .
  • Two terminal segments G 4 and G 5 provide the electrical connection to the functional power lines for the IC package.
  • FIG. 10 shows a flow chart of a method for providing the metal wiring bead according to an embodiment.
  • the corresponding impedance specification for the metal wiring bead is determined. (See block 51 ). This is referred to herein as the desired impedance value.
  • a determination is made as to the wiring pattern (e.g.
  • the steps identified in the blocks 52 , 53 and 54 are repeated until a metal wiring bead design parameters with the desired impedance value is achieved. If the results of the simulation shows that the desired impedance value is achieved by the particular metal wiring bead design parameters, the simulation is complete and the design parameters can be incorporated into the manufacturing design data for the interposer for a 2.5D/3D IC package.
  • the bead element of the present disclosure can be employed in IC packages and in particular, to a multilayer interposer structure for 2.5D/3D multi-chip packaging technologies to eliminate or substantially reduce different power noise and suppress electromagnetic interference in communication system applications.
  • Integrated fan-out (InFO) packages also known as integrated fan-out wafer level package (InFO-WLP) have become popular in recent times.
  • InFO integrated fan-out
  • I/O input/output
  • package I/O pins can be formed in a redistribution layer (RDL) over the die.
  • RDL redistribution layer
  • the die is surrounded laterally by a medium, such as a molding compound, encapsulant, epoxy resin, or the like.
  • the RDL can extend laterally beyond the perimeter of the die.
  • the RDL layer comprises a patternable dielectric material, in which conductive patterns and conductive vias can be formed.
  • the antenna cavity structure provided according to some embodiments of the present disclosure may improve the reflection coefficient, the S11 parameter, of the integrated patch antenna in the InFO package, especially in high frequency applications that employ antenna efficiency at frequencies of 5.8 GHz and higher.
  • the antenna cavity structure also helps reduce the undesirable couplings of the antenna to the nearby circuits, and prevent the unwanted noise from the circuits from reaching the antenna.
  • an InFO package 300 comprises: a top-side redistribution wiring structure 400 ; a back-side redistribution wiring layer 500 ; a ground plane 510 provided in the back-side redistribution wiring layer; a molding compound layer 70 having a thickness and provided between the back-side redistribution wiring layer and the top-side redistribution wiring structure; an RF integrated circuit die 310 at least laterally embedded within the molding compound layer; one or more integrated patch antenna structure 427 provided in the top-side redistribution wiring structure, wherein the one or more integrated patch antenna structure is coupled to the RF integrated circuit die and configured to radiate electromagnetic radiation for wireless transmission or to receive electromagnetic radiation for wireless reception; one or more cavity sidewall structures 303 A provided within the molding compound layer and in electrical contact with the ground plane 510 and extending from the ground plane through the thickness of the molding compound layer 70 ; and an antenna cavity 327 provided within the molding compound layer under each of the one or more integrated patch antenna structure, wherein each of the antenna
  • FIG. 13 is a cross sectional view of an embodiment of an InFO package 300 according to an aspect of the present disclosure. The cross-section is taken through the section line A-A shown in the top-down view of the InFO package illustrated in FIG. 14 .
  • InFO packages such as the InFO package 300 can have a plurality of integrated circuit (IC) dies.
  • FIG. 13 shows a portion of InFO package 300 containing an RF IC die 310 .
  • the RF IC die 310 is embedded in a medium, such as a molding compound 70 .
  • the bottom side of the RF IC die 310 has a back-side redistribution layer RDL 500 ( FIG. 19 ) that can contain one or more conductor structures, such as conductor 510 .
  • RDL 500 FIG. 19
  • a top-side redistribution wiring structure 400 is provided on the top-side of the RF IC die 310 .
  • the RDL wiring patterns can include wiring patterns at least partially over the RF IC die 310 and/or wiring patterns at least partially over the molding compound 70 material.
  • the top-side redistribution wiring structure 400 generally comprises a plurality of redistribution layers each comprising a plurality of conductor structures.
  • the top-side redistribution wiring structure 400 provides electrical connection between the RF IC die 310 and the interconnection structures such as the solder bumps 600 on the top-side of the InFO package 300 .
  • the solder bumps 600 provide electrical interconnection to the next level packaging such as, for example, a printed circuit board (PCB) or an interposer.
  • PCB printed circuit board
  • the conductor structures 510 in the back-side redistribution layer 500 can also be electrically conductively connected to the interconnection structures such as the solder bumps 600 on the top-side of the InFO package 300 through the top-side redistribution wiring structure 400 .
  • the electrical connection between the conductor structures 510 in the back-side redistribution layer 500 and the top-side redistribution wiring structure 400 can be provided by one or more of through-insulator vias (TIVs), also known as through-InFO vias, 303 .
  • TIVs 303 are conductive metal structures that extend through the thickness of the medium (e.g., molding compound) 70 .
  • a dielectric layer 413 is provided over the RDL-1 412 .
  • second level conductors (RDL-2) 422 and second level vias (RDL-2 vias) 425 provide the interconnections.
  • a dielectric layer 423 is provided over the RDL-2 422 .
  • third top-side RDL layer 430 which is the last RDL layer, third level conductors (RDL- 3 ) 432 and under ball metal (UBM) pads 435 provide the interconnections.
  • the solder bumps 600 are formed on the UBM pads 435 .
  • a dielectric layer 433 is provided over the RDL-3 432 .
  • the InFO package 300 comprises one or more integrated patch antenna 427 electrically coupled to the RF IC die 310 by a feed line 428 .
  • a patch antenna is a microstrip antenna comprising a flat rectangular sheet or “patch” of metal, mounted over a larger sheet of metal called a ground plane.
  • the patch antenna is formed in one of the RDL layers.
  • Each integrated patch antenna 427 is provided with an antenna cavity structure 327 underneath the integrated patch antenna 427 .
  • the antenna cavity structure 327 is formed by a cavity sidewall 303 A that is connected to a ground plane 510 which forms the bottom side of the antenna cavity 327 .
  • the cavity sidewall 303 A comprises TIVs.
  • the cavity sidewall comprises one or more continuous elongated “slot vias”.
  • the ground plane 510 is a conductor structure in the back-side redistribution metal layer 500 that is electrically grounded when the InFO package 300 is installed into its intended application environment.
  • the ground plane 510 is electrically conductively connected to solder bumps 600 A by way of the TIV 303 and the corresponding top-side redistribution wiring structures, RDL-1 412 , RDL-1 via 415 , RDL-2 422 , RDL-2 via 425 , RDL-3 432 , and UBM pad 435 .
  • the ground plane 510 can be formed as a solid metal planar structure or any other suitable structure.
  • the ground plane 510 can be formed as a mesh or a set of electrically conductively connected parallel lines.
  • the antenna cavity sidewalls 303 A are formed from a conductive material.
  • the cavity sidewalls 303 A are formed from the same conductive metal as the TIVs 303 .
  • each of the cavity sidewalls 303 A can be formed as a single continuous solid wall structure connected on the bottom side by the ground plane 510 enclosing an area underneath the integrated patch antenna 427 .
  • FIG. 32A provides a schematic illustration of this example.
  • each of the cavity sidewalls 303 A can be formed of two or more continuous solid segments that together enclose an area underneath the integrated patch antenna 427 .
  • FIG. 32B provides a schematic illustration of this example.
  • a continuous solid segment extends an entire distance from one corner of the cavity sidewall structure to an adjacent corner of the cavity sidewall structure. The two or more solid segments can be separated by a spacing from about 10 ⁇ m.
  • the cavity sidewalls 303 A can be formed from a plurality of TIVs that together define the perimeter of the antenna cavity 327 .
  • the spacing between adjacent TIVs forming the cavity sidewalls is selected based on the wavelengths of the signals the antenna is intended to transmit during operation.
  • FIG. 32C provides a schematic illustration of this example. In some embodiments, the spacing between the TIVs are in a range from about 10 ⁇ m wide.
  • FIG. 15 is a schematic illustration of a top-down view of one of the patch antennas from FIG. 14 .
  • the insulator filled antenna cavity 327 defined by the cavity sidewall structures 303 A and the ground plane 510 is shown.
  • a plurality of TIV structures form the cavity sidewall structure 303 A.
  • sidewall structures comprising TIV's are conductively connected to the ground plane 510 , but the top ends of the TIV structures do not contact the patch antennal 427 .
  • FIG. 16 is a plot of the S11 parameter, the reflection coefficient, of the patch antenna 427 structure having the insulator filled antenna cavity 327 shown in FIG. 15 .
  • the 511 values were generated from a simulation of the patch antenna 427 structure shown in FIG. 15 .
  • the plot shows that the antenna efficiently radiates between about 11.5 GHz and 12.8 GHz. Therefore such antenna would be suitable for meeting the specifications of the future 4 th generation (5.8 GHz) and 5 th generation (38 GHz) high frequency RF transceivers in mobile communication applications.
  • the antenna cavity 327 can be filled with any one of a number of insulator materials compatible with InFO package processing and not limited by the insulator's dielectric constant.
  • the patch antenna structure of the present disclosure can be robustly implemented in a InFO package process using high-k or low-k materials.
  • one of the benefits of the integrated patch antenna 427 having the associated antenna insulator cavity 327 according to this disclosure is that these structures can be formed using the existing InFO package manufacturing process flow without interrupting the process flow or requiring retooling of the process equipment.
  • the InFo package manufacturing process can utilize 12 inch wafer fabrication processing tools, for example. Therefore, the InFO package having the integrated patch antenna 427 and the associated antenna insulator cavity 327 provides a low-cost solution for meeting more demanding antenna efficiency specifications of the future (e.g., 4 th and 5 th ) generation high frequency RF transceiver applications.
  • FIGS. 17 through 31 show cross-sectional views of intermediate stages in the manufacturing of an InFO package 300 structure in accordance with some exemplary embodiments.
  • a carrier 10 is provided, and an adhesive layer 20 is deposited on the carrier 10 .
  • the carrier 10 can be a blank glass carrier, a blank ceramic carrier, or the like.
  • the adhesive layer 20 can be formed of an adhesive such as a ultra-violet (UV) glue, Light-to-Heat Conversion (LTHC) glue, or the like, although other types of adhesive may be used.
  • UV ultra-violet
  • LTHC Light-to-Heat Conversion
  • the back-side buffer layer 30 is a dielectric layer, which can comprise a polymer.
  • the polymer can be, for example, polyimide, PolyBenzOxazole (PBO), BenzoCycloButene (BCB), Ajinomoto Buildup Film (ABF), Solder Resist film (SR), or the like.
  • the back-side buffer layer 30 is a planar layer having a uniform thickness, wherein the thickness may be greater than about 2 ⁇ m, and may be from about 2 ⁇ m to about 40 ⁇ m.
  • the top and the bottom surfaces of the back-side buffer layer 30 are also planar.
  • the back-side buffer layer 30 will act as the final protective insulator for the finished InFO package 300 .
  • ground plane structures 510 are formed in the back-side redistribution metal layer 500 .
  • the back-side redistribution metal layer 500 is formed of conductor metal such as Cu or Cu-based alloy and the ground plane structures 510 can be selectively deposited on the back-side buffer layer 30 by electroplating through a photoresist mask layer which is then removed. The intermediate photoresist mask formation and removal are not illustrated.
  • the ground plane structures 510 are formed by electroplated Cu that are about 7 ⁇ m thick. The Cu was plated over a Ti/Cu (1000/5000 ⁇ thick) seed layer.
  • a coating of photoresist 40 is applied over the ground plane structure 510 and the exposed portions of the back-side buffer layer 30 . Then, the photoresist 40 is patterned to form openings or recesses 45 in the photoresist 40 . Such patterning is done by a photolithography process. The recesses 45 expose some portions of the back-side redistribution metal layer 500 . The recesses 45 will be subsequently filled with conductive metal to make the TIVs 303 and cavity sidewalls 303 A. Thus, the shape of the recesses 45 will depend on whether recesses are for the TIVs 303 or the cavity sidewalls 303 A.
  • TIVs can be cylindrical in form or pillars having different polygonal cross-sectional shape.
  • recess 45 can be a hole or a trench depending on whether the cavity sidewall 303 A is formed from a plurality of TIVs, two or more solid segments, or a single solid wall-like structure.
  • the recesses 45 will have a depth that can form the TIVs and the cavity sidewalls 303 A with a desired height.
  • the recesses 45 will be sufficiently deep to form TIVs 303 having a height of about 120-250 ⁇ m.
  • the height of the TIVs 303 is determined by the thickness of the subsequently placed IC dies, such as the RF IC die 310 in the example InFO package 300 .
  • a thin seed layer of Ti/Cu (1000/5000 ⁇ thick) (not shown) is formed on the structure of FIG. 20 in preparation for electroplating deposition of the TIVs 303 and the cavity sidewalls 303 A so that the seed layer is covering the surfaces of the photoresist 40 and the exposed back-side redistribution metal layer 500 , such as the ground plane structure 510 at the bottom of the recesses 45 .
  • the metal features such as the TIVs 303 and the cavity sidewalls 303 A are formed by filling the recesses 45 in the photoresist 40 with conductive metal 60 by plating, which may be electro plating or electro-less plating, on the seed layer 50 .
  • the conductive metal 60 may comprise such conductive metals as copper, aluminum, tungsten, nickel, or alloys thereof.
  • any excess portion of the conductive metal 60 is removed by a process such as chemical mechanical polishing (CMP), exposing the tops of the recesses 45 and the photoresist layer 40 .
  • CMP chemical mechanical polishing
  • the photoresist 40 is removed and the resulting structure is shown in FIG. 23 .
  • the recesses 45 in the photoresist 40 now form the TIVs 303 and the cavity sidewalls 303 A structures.
  • FIG. 24 illustrates the placement of the RF IC die 310 on the back-side buffer layer 30 .
  • IC dies such as the RF IC die 30 can be adhered to the back-side buffer layer 30 using a die-attach-film (DAF) 36 .
  • the RF IC die 310 includes semiconductor substrate 35 (a silicon substrate, for example) whose back surface is in contact with the DAF 36 .
  • the RF IC die 310 includes metal pillars 315 (such as copper posts) that are formed as the top portions of the RF IC die 310 that electrically connects the RF IC die 310 to other conductive devices and interconnect structures in the InFO package 300 .
  • a dielectric layer 316 is formed at the top surface of the RF IC die 310 filling the spaces between the metal pillars 315 , with the metal pillars 315 having at least their lower portions in the dielectric layer 316 .
  • the top surface of the dielectric layer 316 can be level with the top surfaces of the metal pillars 315 , as shown in the RF IC die 310 .
  • a molding compound 70 is applied over the RF IC die 310 , the TIVs 303 , and the cavity sidewalls 303 A and cured.
  • the molding compound 70 fills the gaps between the RF IC die 310 , the TIVs 303 , and the cavity sidewalls 303 A, and may be in contact with any exposed portions of the back-side buffer layer 30 and the ground plane structure 510 .
  • the molding compound 70 may include a molding underfill, an epoxy, or a resin.
  • Some suitable molding compounds can be liquid epoxys, such as liquid epoxy containing fine granular silica, liquid glass (SiO 2 ) (spin on glass) or ceramics.
  • Molding compounds such as the liquid epoxy can be applied as a coating, similar to photoresists, then low temperature (about 180° C.) cured and hardened.
  • the molding compound has a dielectric constant k of 2.8-3.0.
  • Other embodiments include high-k or low-k molding materials.
  • the molding compound 70 provided in sufficient amount to embed the RF IC die 310 , the TIVs 303 , and the cavity sidewalls 303 A. At this stage, the top surface of the molding compound 70 is higher than the top ends of the metal pillars 315 on the RF IC die 310 , the TIVs 303 , and the cavity sidewalls 303 A.
  • a grinding step is performed to thin the molding compound 70 until the tops of the metal pillars 315 , the TIVs 303 , and the cavity sidewalls 303 A are exposed.
  • the grinding can be accomplished by CMP.
  • the resulting interim substrate structure 300 -I is shown in FIG. 26 .
  • the grinding leaves the top ends of the metal features, the metal pillars 315 , the TIVs 303 , and the cavity sidewalls 303 A, to be substantially level (coplanar) along the top surface 72 .
  • the grinding step can leave behind some metal residue such as metal particles on the top surface 72 . Accordingly, after the grinding step, a cleaning may be performed, for example, through a wet etching, to remove the metal residue.
  • the cavity sidewalls 303 A and their associated ground plane 510 define the antenna cavity 327 .
  • the molding compound at least laterally encapsulates the RF IC die 310 between a first surface 71 of the molding compound and a second surface 72 of the molding compound.
  • the one or more TIVs 303 and the one or more cavity sidewalls 303 A are in the molding compound and extend from the ground plane structure 510 to the second surface 72 of the molding compound, wherein the cavity sidewalls and their associated ground plane structure 510 define one or more antenna cavities 327 .
  • Forming the top-side redistribution wiring structure 400 is continued by patterning the dielectric insulation layer 81 and forming openings for vias which are then filled with conductor metal (e.g. copper) to form the RDL-1 vias 415 and completing the first top-side RDL layer 410 .
  • the top surface of the first top-side RDL layer 410 is ground and polished.
  • the second top-side RDL layer 420 is formed on the first top-side RDL layer 410 .
  • a layer of conductor metal e.g.
  • a dielectric insulation layer (e.g. PBO) 83 is then applied over the resulting structure. This structure is shown in FIG. 30 .
  • some of the second level conductor RDL-2 422 structures include the one or more patch antenna structures 427 according to the present disclosure.
  • the patch antenna structures 427 are formed to be positioned over the antenna cavity 327 defined by the cavity sidewalls 303 A and the ground plane 510 .
  • a dielectric insulation layer (e.g. PBO) 85 is then applied over the resulting structure. This structure is shown in FIG. 30 .
  • Forming the top-side redistribution wiring structure 400 is continued by patterning the dielectric insulation layer 85 and forming openings for under ball metal (UBM) pads 435 which are then filled with conductor metal (e.g. copper) to form the UBM pads 435 and completing the third top-side RDL layer 430 .
  • UBM under ball metal
  • conductor metal e.g. copper
  • FIG. 31 further shows the formation of the next level electrical interconnection structures 600 in accordance with some embodiments.
  • the electrical interconnection structures 600 are solder bumps attached to the exposed portions of the UBM pads 435 .
  • the solder bumps 600 can be formed by placing solder balls on the UBM pads 435 and then reflowing the solder balls.
  • the formation of the solder bumps 600 includes performing a plating step to form solder regions over the UBM pads 435 , and then reflowing the solder regions.
  • the electrical interconnection structures 600 can be metal pillars, or metal pillars and solder caps, which may also be formed through plating.
  • the RDL-1 412 , RDL-1 vias 415 , RDL-2 422 , RDL-2 vias 425 , RDL-3 432 , and UBM pads 435 can comprise a metal or a metal alloy including aluminum, copper, tungsten, and/or alloys thereof.
  • the dielectric insulation layers 81 , 83 , and 85 may comprise a polymer such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like.
  • the dielectric layers 81 , 83 , and 85 may include non-organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like.
  • the InFO package 300 is debonded from the carrier 10 .
  • the adhesive layer 20 is also cleaned from the InFO package 300 .
  • the resulting final InFO package 300 is shown in FIG. 13 .
  • FIGS. 33A-33B show a flow chart 700 of a method of manufacturing the InFO package 300 in accordance with some embodiments.
  • the adhesive layer 20 is deposited on the carrier 10 .
  • the back-side buffer layer 30 is formed over the adhesive layer 20 .
  • one or more of the ground plane structures 510 are formed on the back-side buffer layer.
  • a coating of photoresist 40 is applied over the ground plane structure 510 and the exposed portions of the back-side buffer layer 30 and patterned to form openings or recesses 45 in the photoresist 40 . (See block 708 ).
  • one or more TIVs 303 and one or more cavity sidewalls 303 A are formed by filling the recesses 45 with conductive metal 60 .
  • the excess portion of the conductive metal 60 is removed and planarized, exposing the tops of the recesses 45 , which are now filled with the conductive metal 60 , and the photoresist layer 40 .
  • the photoresist 40 is removed leaving behind the TIVs 303 and the cavity sidewalls 303 A structures.
  • the RF IC die 310 is placed on the back-side buffer layer 30 . (See block 716 ).
  • an encapsulating medium such as a molding compound is flowed over the RF IC die 310 , TIVs 303 and ground plane structures 510 .
  • An interim substrate structure 300 -I that comprises the RF IC die, the one or more TIVs, the one or more cavity sidewalls, and a molding compound 70 is formed by laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with the molding compound, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities. (See block 717 ).
  • the molding compound at least laterally encapsulates the RF IC die 310 between a first surface 71 of the molding compound and a second surface 72 of the molding compound.
  • the one or more TIVs 303 and the one or more cavity sidewalls 303 A are in the molding compound and extend from the ground plane structure 510 to the second surface 72 of the molding compound, wherein the cavity sidewalls and their associated ground plane structure 510 define one or more antenna cavities 327 .
  • a molding compound 70 is applied over the RF IC die 310 , the TIVs 303 , and the cavity sidewalls 303 A, filling the gaps between the RF IC die 310 , the TIVs 303 , and the cavity sidewalls 303 A, and cured. (See block 718 ).
  • the molding compound 70 is ground down until the tops of the metal pillars 315 , the TIVs 303 , and the cavity sidewalls 303 A are exposed, thus forming the interim substrate structure 300 -I. (See block 720 ).
  • the cavity sidewalls 303 A and their associated ground plane 510 define the antenna cavities 327 according to the present disclosure.
  • a top-side RDL wiring structure 400 that includes one or more integrated patch antenna structure 427 is formed.
  • the one or more integrated patch antenna structure is coupled to the RF IC die 310 and each of the one or more integrated patch antenna structure is positioned over one of the antenna cavities 327 .
  • the forming of the top-side RDL wiring structure 400 comprises forming the first top-side RDL layer 410 on the ground surface of the interim substrate structure, wherein the first top-side RDL layer 410 including the first level conductor RDL- 1 412 structures over the TIVs 303 and the metal pillars 315 of the RF IC die 310 . (See block 722 ).
  • the second top-side RDL layer 420 is formed on the first top-side RDL layer 410 , wherein the second top-side RDL layer 420 includes the second level conductor RDL-2 422 structures over the first top-side RDL layer 410 , the second level conductor RDL-2 422 structures including the one or more patch antenna structures 427 that are positioned over the antenna cavity 327 .
  • the third top-side RDL layer 430 is formed on the second top-side RDL layer 420 , wherein the third top-side RDL layer 430 includes the third level conductor RDL-3 432 structures including the UBM pads 435 . (See block 726 ).
  • the next level electrical interconnection structures 600 are formed on the UBM pads 435 . (See block 728 ).
  • the carrier 10 is removed, thus forming the InFO package 300 . (See block 730 ).
  • the InFO process is robust and, thus, the thickness of the InFO package 300 can be fabricated to be within a wide range of thickness.
  • the InFO package can be fabricated to have a thickness that is anywhere from 200 ⁇ m to 2.0 mm for the 5 th generation high frequency RF transceiver application.

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Abstract

A method for forming an integrated fan-out package includes depositing an adhesive layer on a carrier, forming a back-side buffer layer over the adhesive layer, forming a back-side redistribution metal layer on the back-side buffer layer, wherein the back-side redistribution metal layer includes one or more ground plane structures, forming one or more through-insulator vias (TIVs) and one or more cavity sidewalls on the one or more ground plane structures, placing a radio frequency (RF) integrated circuit (IC) die on the back-side buffer layer, laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with a molding compound, thus forming an interim substrate, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities, and forming a top-side redistribution (RDL) wiring structure on the interim substrate, the top-side RDL wiring structure including one or more integrated patch antenna structure, wherein the one or more integrated patch antenna structure is coupled to the RF IC die and each of the one or more integrated patch antenna structure is positioned over one of the antenna cavities.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This is a divisional application of U.S. patent application Ser. No. 15/056,030, filed on Feb. 29, 2016, which is a continuation-in-part of co-pending U.S. patent application Ser. No. 13/481,974, filed on May 29, 2012, now U.S. Pat. No. 9,275,950, issued on Mar. 1, 2016, which is incorporated by reference herein in its entirety.
FIELD
The present disclosure generally relates to a bead element employed in integrated circuit packaging.
BACKGROUND
Low Temperature Co-Fired Ceramic (LTCC) and printed circuit board (PCB) substrates can be used for integration of mm-wave antennas with RF integrated circuits (ICs) in high frequency applications but those packages have power consumption issues resulting from interconnect losses from chip to antenna through solder bumps or balls. Therefore, improved antenna structures integrated into packaging is desired.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view illustration of a portion of a 2.5D/3D IC package in which one or more of the metal wiring bead of the present disclosure can be incorporated according to some embodiments.
FIG. 2 is an illustration of an example of a 2.5D IC package in which one or more of the metal wiring bead according to some embodiments of the present disclosure can be incorporated.
FIG. 3 shows a one-layer metal wiring bead according to some embodiments.
FIG. 4 shows a one-layer metal wiring bead according to some embodiments
FIGS. 5A and 5B show two-layer metal wiring beads embodiments according to some embodiments.
FIGS. 6A and 6B show a two-layer metal wiring bead according to some embodiments.
FIGS. 7A and 7B show a two-layer metal wiring bead according to some embodiments.
FIG. 8 shows a three-layer metal wiring bead according to some embodiments.
FIG. 9 shows another three-layer metal wiring bead according to some embodiments.
FIG. 10 is a flow chart for a method for providing the metal wiring bead according to some embodiments.
FIG. 11 shows plots of R, XL, Z performance values from a simulation of a metal wiring bead according to some embodiments of the present disclosure.
FIG. 12A and 12B illustrate the relationship between the parameters Z, R, and XL (impedance, resistance, and reactance) according to some embodiments.
FIG. 13 is a cross-sectional view of an exemplary InFO package according to some embodiments of the present disclosure, where the cross-section is taken through the section line A-A shown in FIG. 14.
FIG. 14 is an illustration of a top-down view of the InFO package showing an arrangement of patch antennas according to some embodiments of the present disclosure.
FIG. 15 is an illustration of a top-down view of one of the patch antenna from FIG. 14 according to some embodiments.
FIG. 16 is a plot of the S11 parameter, the reflection coefficient, of the patch antenna structure of FIG. 15 according to some embodiments.
FIGS. 17 through 31 show cross-sectional views of intermediate stages in the manufacturing of an InFO package in accordance with some exemplary embodiments.
FIG. 32A is an illustration of an antenna cavity formed by a single solid wall structure according to some embodiments.
FIG. 32B is an illustration of an antenna cavity formed by two or more continuous solid segments according to some embodiments.
FIG. 32C is an illustration of an antenna cavity formed by a plurality of through-insulator vias (TIVs) according to some embodiments.
FIGS. 33A-33B show a flow chart of the method of manufacturing the InFO package in accordance with some embodiments.
All drawings are schematic and are not to scale.
DETAILED DESCRIPTION
This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
Some embodiments of the present disclosure relate to an impedance element, in particular, relates to an element which is used as a bead filter or a noise filter to eliminate power noise and suppress electromagnetic interference in integrated circuit (IC) devices.
Some embodiments of this disclosure include a multilayer interposer structure for 2.5D/3D applications that eliminates different power noise and suppress electromagnetic interference. Integrated fan-out (InFO) packages can be integrated with antenna structures such as patch antennas that are coupled to an RF IC die through a feed structure that is directly connected to the RF IC die. For example, one or more antenna can be integrated with the RF IC die through an integrated fan-out redistribution structures comprising a metallization layer (e.g. a redistribution layer) coupled to a package molding compound with the RF IC die embedded therein. As the advancing RF applications require increasingly higher frequency RF transceiver capabilities, improved InFO packages can meet higher frequency RF transceiver specifications.
Disclosed herein is a method for eliminating different power noise and suppressing electromagnetic interference (EMI) in 2.5D/3D integrated circuit (IC) packages used in communication system applications. According to an embodiment, one or more convoluted metal wiring beads having a convoluted shape are incorporated into the wiring structures of the multilayer interposer of a 2.5D/3D IC package. The convoluted metal wiring bead can be incorporated into the power lines in the IC package and function as a bead filter or a noise filter to eliminate power line noise. The metal wiring bead is configured to provide an appropriate impedance to meet the power noise reduction requirement of a particular IC package's requirement. Unlike many conventional impedance elements that are implemented as ferrite beads or discrete surface-mount devices such as ferromagnetic insulation chips, incorporating the impedance element into the multilayer interposer structure provides more compact solution and lower cost.
FIG. 1 is a cross-sectional view illustration of a portion of a 2.5D/3D IC package 100 in which one or more of the metal wiring bead of the present disclosure can be incorporated. The IC package 100 comprises an IC device 110 and an interposer 120 attached to the IC device. Generally, the IC device 110 can be encapsulated with a molding compound 130.
The interposer 120 comprises a multiple layers of wiring structures. In this example interposer 120, the multiple layers of wiring structures comprise a plurality of wiring layers 122, 124, and 126 and via layers 121, 123 and 125. The wiring layers 122, 124, and 126 each comprises various wiring structures formed from conductor materials M1, M2, M3, corresponding to the wiring layers 122, 124, 126 respectively, disposed in a dielectric material. The via layers 121, 123 and 125 each comprises a plurality of vias generally referred to herein as V1, V2, V3, respectively, disposed in a non-ferrite polymeric dielectric material. The vias provide the electrical connection between the wiring layers. The vias V1 in the first via layer 121 provide the electrical connection between the wiring structures of the first wiring layer 122 and the IC device 110. Generally, the conductor materials M1, M2, M3 are copper-based metal and the dielectric material is one or more types of polymers. The conductor materials M1, M2, and M3 generally are the same materials but they can be different.
According to an embodiment of the present disclosure, the metal wiring bead is provided in the interposer 120 of the IC package 100. The metal wiring bead can comprise a single layer pattern, a two-layer pattern or a three-layer pattern and can be formed in one or more of the plurality of metal wiring layers 122, 124, and 126.
FIG. 2 is a schematic illustration of an example of a 2.5D IC package 200 in which one or more of the metal wiring bead of the present disclosure can be incorporated. The IC package 200 comprises an interposer 220 to which one or more IC devices 201, 202, and 203 are attached on one side and one or more IC devices 204 and 205 are attached on the second side. One or more of the metal wiring bead of the present disclosure can be incorporated in the interposer 220.
FIG. 3 shows a one-layer embodiment of a metal wiring bead A according to an aspect of the present disclosure. The metal wiring bead A has a convoluted wiring pattern that is formed in one of the three wiring layers 122, 124 or 126 from the corresponding M1, M2 or M3 conducting material. The convoluted wiring pattern of the metal wiring bead A has a serpentine-like portion A1 that begins at first terminal segment A2 and ends at a second terminal segment A3. The serpentine-like portion A1 is a wiring trace of the conductor material provided in a meandering serpentine-like pattern. The two terminal segments A2 and A3 provide electrical connection to the functional power lines in the IC package. The term “serpentine-like” is used to describe the generally winding shape represented by the portion A1 where the metal wiring is winding back and forth similar to the shape formed by the body of a moving serpent.
FIG. 4 shows another one-layer embodiment of a metal wiring bead B. The metal wiring bead B has a convoluted wiring pattern that is formed in one of the three wiring layers 122, 124 or 126 from the corresponding M1, M2 or M3 conducting material. Unlike the metal wiring bead A shown in FIG. 3, the convoluted wiring pattern of the metal wiring bead B has a meandering loop portion B1 that begins at a first terminal segment B2, follows a square or quadrilateral outline and loops back towards the first terminal segment and ends at a second terminal segment B3. The conductive line tracing in the meandering loop portion B1 meanders in right angles, but the meandering pattern of the conductive line trace can be in any shape. The two terminal segments B2 and B3 are connected to the functional power lines in the IC package.
FIG. 5 shows two-layer metal wiring bead embodiments C and CC. The metal wiring bead C has a convoluted wiring pattern that has two convoluted segments C1 and C2 formed from the M1 conducting material in the first wiring layer 122 that are electrically connected in series by the connecting segment C3 that is formed from the M2 metal in the second metal wiring layer 124. Two terminal segments C4 and C5 provide the electrical connection to the functional power lines for the IC package. The terminal segments C4 and C5 are also formed from the M2 conducting material in the second metal wiring layer 124. Corresponding via structures (not shown) in the via layer 123 connects the convoluted segments C1 and C2 to the segments C3, C4 and C5.
The metal wiring bead CC has a convoluted wiring pattern that has two convoluted segments CC1 and CC2 formed from the M2 conducting material in the second wiring layer 124 that are connected in series by the connecting segment CC3 that is formed from the M1 conducting material in the first metal wiring layer 121. Two terminal segments CC4 and CC5 provide the electrical connection to the functional power lines for the IC package. The terminal segments CC4 and CC5 are also formed from the M1 conducting material in the first metal wiring layer 122. Corresponding via structures (not shown) in the via layer 123 connects the convoluted segments CC1 and CC2 to the segments CC3, CC4 and CC5. Because FIG. 4 is a plan view of the metal wiring beads C and CC, the via structures connecting the M1 conducting material structures with the M2 conducting material structures would be oriented orthogonal to the plane of the drawings and hidden between the connecting parts of the M1 and M2 conducting material structures.
FIGS. 6A and 6B show another two-layer metal wiring bead embodiment D. The metal wiring bead D has a convoluted wiring pattern having a quadrilateral outline that has a first set of a plurality of line segments D1 formed from the M1 conducting material in the first wiring layer 122 and a second set of a plurality of line segments D2 formed from the M2 conducting material in the second wiring layer 124. A plurality of vias D-via in the via layer 123 provide the electrical connection between the first set of line segments D1 and the second set of line segments D2 and form a serpentine-like convoluted pattern for the metal wiring bead D. The first set of line segments D1 and the second set of line segments D2 are in a staggered arrangement as shown and the vias D-via connect each of the line segments in the first set D1 and the second set D2 to two line segments in the other set. For example, referring to FIG. 6A, the line segment 10 in the first set D1 is connected to two of the line segments 31 and 32 in the second set D2 by the vias 21 and 22. The same is true for the line segment 12 located at the corner of the square-shaped outline of the metal wiring bead D. The only difference is that the line segment 12 has a bend in the middle of the segment to form the corner section of the metal wiring bead D. The vias D-via are configured to extend not only in the Z-direction (i.e., the direction orthogonal to the plane of the wiring layers) but also extend along the direction parallel to the plane of the wiring layers. In the illustrated example of vias 21 and 22, they extend along Y-direction for a distance of d to make the connection between the line segment 10 and the line segments 31 and 32. Two terminal segments D3 and D4 provide the electrical connection to the functional power lines for the IC package. The terminal segment D3 is formed from the M1 conducting material in the first wiring layer 122 and the terminal segment D4 is formed from the M2 conducting material in the second wiring layer 124. FIG. 5B shows an isometric view illustration of the metal wiring bead D.
FIGS. 7A and 7B show another two-layer metal wiring bead embodiment E. The metal wiring bead E has a convoluted wiring pattern that forms a serpentine-like that has a first set of a plurality of line segments E1 formed from the M1 conducting material in the first wiring layer 122 and a second set of a plurality of line segments E2 formed from the M2 conducting material in the second wiring layer 124. A plurality of vias E-via in the via layer 123 provide the electrical connection between the first set of line segments E1 and the second set of line segments E2 and form a serpentine-like convoluted pattern for the metal wiring bead E. The vias E-via extend at least 100 μm along the X or Y direction within the via layer (i.e. the directions parallel to the plane of the wiring layers), thereby comprising a substantial portion of the total length of the metal wiring bead E. In one embodiment, the extended vias comprise at least 50% of the total length of the metal wiring bead E. The first and second sets of line segments E1 and E2 have a curved configuration rather than being straight line segments. Two terminal segments E3 and E4 provide the electrical connection to the functional power lines for the IC package.
FIG. 8 shows a three-layer metal wiring bead embodiment F according to an aspect of the present disclosure. The metal wiring bead F comprises a convoluted wiring pattern that forms a serpentine-like structure in each of the three wiring layers 122, 124, and 126 that are electrically connected in series. In the first wiring layer 122, a first serpentine-like portion F1 is formed from the M1 conductor material. In the second wiring layer 124, a second serpentine-like portion F2 is formed from the M2 conductor material. In the third wiring layer 126, a third serpentine-like portion F3 is formed from the M3 conductor material. The electrical connection between the first serpentine-like portion F1 and the second serpentine-like portion F2 is provided by a via F-vial provided in the via layer 123. The electrical connection between the second serpentine-like portion F2 and the third serpentine-like portion F3 is provided by a via F-via2 provided in the via layer 125. Two terminal segments F4 and F5 provide the electrical connection to the functional power lines for the IC package.
FIG. 9 shows another three-layer metal wiring bead embodiment G according to another aspect of the present disclosure. The metal wiring bead G comprises a convoluted wiring pattern in each of the three wiring layers 122, 124, and 126 that are electrically connected in series. In the first wiring layer 122, a first convoluted wiring pattern G1 is formed from the M1 conductor material. In the second wiring layer 124, a second convoluted wiring pattern G2 is formed from the M2 conductor material. In the third wiring layer 126, a third convoluted wiring pattern G3 is formed from the M3 conductor material. The electrical connection between the first convoluted wiring pattern G1 and the second convoluted wiring pattern G2 is provided by a via G-vial provided in the via layer 123. The electrical connection between the second convoluted wiring pattern G2 and the third convoluted wiring pattern G3 is provided by a via G-via2 provided in the via layer 125. Two terminal segments G4 and G5 provide the electrical connection to the functional power lines for the IC package. As shown, the three convoluted wiring patterns G1, G2, and G3 have different size outlines, the first convoluted wiring pattern G1 having the smallest outline and the third convoluted wiring pattern G3 having the largest so that the second and the first convoluted wiring patterns G2 and G1 are nested within the outline of the third convoluted wiring pattern G3 when viewed from the top as shown in FIG. 8. This configuration is another example that provides sufficient metal length for the metal wiring bead G which will provide proper R (resistance) and XL (reactance) values for the bead.
FIG. 10 shows a flow chart of a method for providing the metal wiring bead according to an embodiment. First, based on a performance requirement defined for a particular IC package, the corresponding impedance specification for the metal wiring bead is determined. (See block 51). This is referred to herein as the desired impedance value. Then, a determination is made as to whether one, two or three layers of metal should be used to make the metal wiring bead for the particular IC package that will produce the desired impedance. (See block 52). One determines whether one, two or three layers of metal should be used depending on the metal wiring bead impedance value that is desired in a given application. Next, a determination is made as to the wiring pattern (e.g. a square, circle, etc.) of the metal wiring bead for the particular IC package that will produce the desired impedance. (See block 53). The particular wiring pattern is chosen that would provide the desired wiring bead impedance value. Before the design for the metal wiring bead is finalized and implemented into the manufacturing process for the interposer for the IC package, a computer simulation is conducted to verify whether the specified impedance is met by the determined number of metal layers and the wiring pattern for the metal wiring bead. (See block 54).
If the results of the simulation shows that the desired impedance value is not achieved by the particular metal wiring bead design parameters, then the steps identified in the blocks 52, 53 and 54 are repeated until a metal wiring bead design parameters with the desired impedance value is achieved. If the results of the simulation shows that the desired impedance value is achieved by the particular metal wiring bead design parameters, the simulation is complete and the design parameters can be incorporated into the manufacturing design data for the interposer for a 2.5D/3D IC package.
FIG. 11 shows plots of Z, R, and XL (impedance, resistance, and reactance) values at 102.5 MHz from a simulation of a metal wiring bead according to the present disclosure. The general relationship between the parameters Z, R, and XL used for such simulation calculations is well known in the art and is represented by the illustrations in FIGS. 12A and 12B.
The bead element of the present disclosure can be employed in IC packages and in particular, to a multilayer interposer structure for 2.5D/3D multi-chip packaging technologies to eliminate or substantially reduce different power noise and suppress electromagnetic interference in communication system applications.
Integrated fan-out (InFO) packages, also known as integrated fan-out wafer level package (InFO-WLP), have become popular in recent times. In an InFO package, fan out wirings between input/output (I/O) pins on the die and package I/O pins can be formed in a redistribution layer (RDL) over the die. The die is surrounded laterally by a medium, such as a molding compound, encapsulant, epoxy resin, or the like. The RDL can extend laterally beyond the perimeter of the die. The RDL layer comprises a patternable dielectric material, in which conductive patterns and conductive vias can be formed. InFO packages can provide significantly thinner packages with much tighter redistribution line pitches (10 μm) compared to other fan-out structures for die packaging technologies. InFO packages provide many advantages over packages such as FC-BGA (flip-chip ball grid array) packaging since passive devices such as inductors and capacitors can be formed beyond the perimeter of an IC die (e.g., over molding compound) for lower substrate loss and higher electrical performance. The smaller die form factor also leads to better thermal performance and thus a lower operating temperature for the same power budget. Alternatively, by taking advantage of the improved thermal performance, faster circuit operation speed can be achieved for the same temperature profile as FC-BGA.
According to some embodiments of the present disclosure, an InFO package having one or more integrated patch antenna is provided, where each integrated patch antenna incorporates an insulator filled antenna cavity structure for improved antenna performance and efficiency at high frequency applications.
The antenna cavity structure provided according to some embodiments of the present disclosure may improve the reflection coefficient, the S11 parameter, of the integrated patch antenna in the InFO package, especially in high frequency applications that employ antenna efficiency at frequencies of 5.8 GHz and higher. The antenna cavity structure also helps reduce the undesirable couplings of the antenna to the nearby circuits, and prevent the unwanted noise from the circuits from reaching the antenna.
The embodiments described below provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
A description of an InFO package and a method of forming the same are provided in accordance with some embodiments. The intermediate stages of forming the InFO package are illustrated. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
In some embodiments, as shown in FIG. 13, an InFO package 300 comprises: a top-side redistribution wiring structure 400; a back-side redistribution wiring layer 500; a ground plane 510 provided in the back-side redistribution wiring layer; a molding compound layer 70 having a thickness and provided between the back-side redistribution wiring layer and the top-side redistribution wiring structure; an RF integrated circuit die 310 at least laterally embedded within the molding compound layer; one or more integrated patch antenna structure 427 provided in the top-side redistribution wiring structure, wherein the one or more integrated patch antenna structure is coupled to the RF integrated circuit die and configured to radiate electromagnetic radiation for wireless transmission or to receive electromagnetic radiation for wireless reception; one or more cavity sidewall structures 303A provided within the molding compound layer and in electrical contact with the ground plane 510 and extending from the ground plane through the thickness of the molding compound layer 70; and an antenna cavity 327 provided within the molding compound layer under each of the one or more integrated patch antenna structure, wherein each of the antenna cavity is defined by a cavity sidewall structure and the ground plane and the antenna cavity is filled with the molding compound.
In some embodiments of the InFO package 300 one or more ground plane structures 510 are provided and each of the antenna cavity is defined by a cavity sidewall structure and one of the at least one or more ground plane structures.
FIG. 13 is a cross sectional view of an embodiment of an InFO package 300 according to an aspect of the present disclosure. The cross-section is taken through the section line A-A shown in the top-down view of the InFO package illustrated in FIG. 14. InFO packages such as the InFO package 300 can have a plurality of integrated circuit (IC) dies. FIG. 13 shows a portion of InFO package 300 containing an RF IC die 310.
The RF IC die 310 is embedded in a medium, such as a molding compound 70. The bottom side of the RF IC die 310 has a back-side redistribution layer RDL 500 (FIG. 19) that can contain one or more conductor structures, such as conductor 510. On the top-side of the RF IC die 310, a top-side redistribution wiring structure 400 is provided. The RDL wiring patterns can include wiring patterns at least partially over the RF IC die 310 and/or wiring patterns at least partially over the molding compound 70 material. The top-side redistribution wiring structure 400 generally comprises a plurality of redistribution layers each comprising a plurality of conductor structures. The top-side redistribution wiring structure 400 provides electrical connection between the RF IC die 310 and the interconnection structures such as the solder bumps 600 on the top-side of the InFO package 300. The solder bumps 600 provide electrical interconnection to the next level packaging such as, for example, a printed circuit board (PCB) or an interposer.
The conductor structures 510 in the back-side redistribution layer 500 can also be electrically conductively connected to the interconnection structures such as the solder bumps 600 on the top-side of the InFO package 300 through the top-side redistribution wiring structure 400. The electrical connection between the conductor structures 510 in the back-side redistribution layer 500 and the top-side redistribution wiring structure 400 can be provided by one or more of through-insulator vias (TIVs), also known as through-InFO vias, 303. The TIVs 303 are conductive metal structures that extend through the thickness of the medium (e.g., molding compound) 70.
In the illustrated example InFO package 300, the top-side redistribution wiring structure 400 comprises three top-side redistribution line (RDL) layers 410, 420, and 430. In other embodiments, different number of RDL layers can be included. Each RDL layer comprises RDLs and vias which are metal conductor features that provide the electrical interconnections through and within the top-side redistributon wiring structure 400. In some embodiments, the RDL lines and vias comprise copper. In the first top-side RDL layer 410, first level conductors (RDL-1) 412 and first level vias (RDL-1 vias) 415 provide the interconnections. In the first top-side RDL layer 410, a dielectric layer 413 is provided over the RDL-1 412. In the second top-side RDL layer 420, second level conductors (RDL-2) 422 and second level vias (RDL-2 vias) 425 provide the interconnections. In the second top-side RDL layer 420, a dielectric layer 423 is provided over the RDL-2 422. In the third top-side RDL layer 430, which is the last RDL layer, third level conductors (RDL-3) 432 and under ball metal (UBM) pads 435 provide the interconnections. The solder bumps 600 are formed on the UBM pads 435. In the third top-side RDL layer 430, a dielectric layer 433 is provided over the RDL-3 432.
The InFO package 300 comprises one or more integrated patch antenna 427 electrically coupled to the RF IC die 310 by a feed line 428. A patch antenna is a microstrip antenna comprising a flat rectangular sheet or “patch” of metal, mounted over a larger sheet of metal called a ground plane. In some embodiments, the patch antenna is formed in one of the RDL layers. Each integrated patch antenna 427 is provided with an antenna cavity structure 327 underneath the integrated patch antenna 427. The antenna cavity structure 327 is formed by a cavity sidewall 303A that is connected to a ground plane 510 which forms the bottom side of the antenna cavity 327. In some embodiments, the cavity sidewall 303A comprises TIVs. In other embodiments, the cavity sidewall comprises one or more continuous elongated “slot vias”.
Generally, a patch antenna includes a radiating patch on one side of a dielectric substrate which has a ground plane on the other side. The integrated patch antenna 427 can be provided in any shape. For example, the shape of the integrated patch antenna 427 can be provided in any shape, e.g. a circle, an ellipse, or any desired polygonal shape such as a triangle, a square, a rectangle, a pentagon, a hexagon, an octagon, etc. However, for a given RF application for the InFO package, a particular shape may be desirable for the integrated patch antenna 427 based on the particular RF signal transmission/reception specifications imposed by that RF application. For example, in some intended applications, a square shaped patch antenna may be advantageous compared to other shapes.
The ground plane 510 is a conductor structure in the back-side redistribution metal layer 500 that is electrically grounded when the InFO package 300 is installed into its intended application environment. For example, in some embodiments, the ground plane 510 is electrically conductively connected to solder bumps 600A by way of the TIV 303 and the corresponding top-side redistribution wiring structures, RDL-1 412, RDL-1 via 415, RDL-2 422, RDL-2 via 425, RDL-3 432, and UBM pad 435. The ground plane 510 can be formed as a solid metal planar structure or any other suitable structure. For example, in some embodiments, the ground plane 510 can be formed as a mesh or a set of electrically conductively connected parallel lines.
The antenna cavity sidewalls 303A are formed from a conductive material. In the example InFO package 300, the cavity sidewalls 303A are formed from the same conductive metal as the TIVs 303. When the InFO package 300 is installed into its intended application environment, the solder bumps 600A are connected to electrical ground and, in turn, the ground plane 510 and the cavity sidewall 303A become grounded.
In some embodiments, each of the cavity sidewalls 303A can be formed as a single continuous solid wall structure connected on the bottom side by the ground plane 510 enclosing an area underneath the integrated patch antenna 427. FIG. 32A provides a schematic illustration of this example. In other embodiments, each of the cavity sidewalls 303A can be formed of two or more continuous solid segments that together enclose an area underneath the integrated patch antenna 427. FIG. 32B provides a schematic illustration of this example. On each side of the cavity sidewall structure, a continuous solid segment extends an entire distance from one corner of the cavity sidewall structure to an adjacent corner of the cavity sidewall structure. The two or more solid segments can be separated by a spacing from about 10 μm. In other embodiments, the cavity sidewalls 303A can be formed from a plurality of TIVs that together define the perimeter of the antenna cavity 327. The spacing between adjacent TIVs forming the cavity sidewalls is selected based on the wavelengths of the signals the antenna is intended to transmit during operation. FIG. 32C provides a schematic illustration of this example. In some embodiments, the spacing between the TIVs are in a range from about 10 μm wide.
The cavity sidewalls 303A and the ground plane 510 can be formed to have any shape for its perimeter outline. In some embodiments, the cavity sidewalls 303A and the ground plane 510 are configured to have perimeter outline shapes that match the perimeter outline of the integrated patch antenna 427. Thus, if the integrated patch antenna 427 is square shaped, the cavity sidewalls 303A and the ground plane 510 will also be provided to have a square shaped outline that is of the appropriate size to match the size of the integrated patch antenna 427.
FIG. 14 a schematic illustration of a top-down view of the InFO package 300. The RF IC die 310 is shown in the center that is connected to four patch antennas 427. Antenna feed lines 428 connect the patch antennas 427 to the RF IC die 310. The ground plane 510 positioned below the patch antennas 427 can be seen. The antenna cavities 327 and the cavity sidewalls 303A are underneath the patch antennas 427 between the patch antennas 427 and the ground plane 510 and thus are not visible in this top-down view.
FIG. 15 is a schematic illustration of a top-down view of one of the patch antennas from FIG. 14. The insulator filled antenna cavity 327 defined by the cavity sidewall structures 303A and the ground plane 510 is shown. In this example, a plurality of TIV structures form the cavity sidewall structure 303A. In some embodiments, sidewall structures comprising TIV's are conductively connected to the ground plane 510, but the top ends of the TIV structures do not contact the patch antennal 427.
FIG. 16 is a plot of the S11 parameter, the reflection coefficient, of the patch antenna 427 structure having the insulator filled antenna cavity 327 shown in FIG. 15. The 511 values were generated from a simulation of the patch antenna 427 structure shown in FIG. 15. The plot shows that the antenna efficiently radiates between about 11.5 GHz and 12.8 GHz. Therefore such antenna would be suitable for meeting the specifications of the future 4th generation (5.8 GHz) and 5th generation (38 GHz) high frequency RF transceivers in mobile communication applications.
The antenna cavity 327 can be filled with any one of a number of insulator materials compatible with InFO package processing and not limited by the insulator's dielectric constant. Thus, the patch antenna structure of the present disclosure can be robustly implemented in a InFO package process using high-k or low-k materials.
As described below, one of the benefits of the integrated patch antenna 427 having the associated antenna insulator cavity 327 according to this disclosure is that these structures can be formed using the existing InFO package manufacturing process flow without interrupting the process flow or requiring retooling of the process equipment. The InFo package manufacturing process can utilize 12 inch wafer fabrication processing tools, for example. Therefore, the InFO package having the integrated patch antenna 427 and the associated antenna insulator cavity 327 provides a low-cost solution for meeting more demanding antenna efficiency specifications of the future (e.g., 4th and 5th) generation high frequency RF transceiver applications.
Referring to FIGS. 17 through 31, an example of a process of forming the InFO package 300 is described. FIGS. 17 through 31 show cross-sectional views of intermediate stages in the manufacturing of an InFO package 300 structure in accordance with some exemplary embodiments. Referring to FIG. 17, a carrier 10 is provided, and an adhesive layer 20 is deposited on the carrier 10. The carrier 10 can be a blank glass carrier, a blank ceramic carrier, or the like. The adhesive layer 20 can be formed of an adhesive such as a ultra-violet (UV) glue, Light-to-Heat Conversion (LTHC) glue, or the like, although other types of adhesive may be used.
Referring to FIG. 18, a back-side buffer layer 30 is formed over the adhesive layer 20. The back-side buffer layer 30 is a dielectric layer, which can comprise a polymer. The polymer can be, for example, polyimide, PolyBenzOxazole (PBO), BenzoCycloButene (BCB), Ajinomoto Buildup Film (ABF), Solder Resist film (SR), or the like. The back-side buffer layer 30 is a planar layer having a uniform thickness, wherein the thickness may be greater than about 2 μm, and may be from about 2 μm to about 40 μm. The top and the bottom surfaces of the back-side buffer layer 30 are also planar. The back-side buffer layer 30 will act as the final protective insulator for the finished InFO package 300.
Next, one or more of the ground plane structures 510 are formed in the back-side redistribution metal layer 500. The back-side redistribution metal layer 500 is formed of conductor metal such as Cu or Cu-based alloy and the ground plane structures 510 can be selectively deposited on the back-side buffer layer 30 by electroplating through a photoresist mask layer which is then removed. The intermediate photoresist mask formation and removal are not illustrated. In this example, the ground plane structures 510 are formed by electroplated Cu that are about 7 μm thick. The Cu was plated over a Ti/Cu (1000/5000 Å thick) seed layer.
Referring to FIG. 20, a coating of photoresist 40 is applied over the ground plane structure 510 and the exposed portions of the back-side buffer layer 30. Then, the photoresist 40 is patterned to form openings or recesses 45 in the photoresist 40. Such patterning is done by a photolithography process. The recesses 45 expose some portions of the back-side redistribution metal layer 500. The recesses 45 will be subsequently filled with conductive metal to make the TIVs 303 and cavity sidewalls 303A. Thus, the shape of the recesses 45 will depend on whether recesses are for the TIVs 303 or the cavity sidewalls 303A. For example, if a particular recess is intended for forming a TIV 303, that recess 45 will be a hole appropriately shaped to form the TIV 303. TIVs can be cylindrical in form or pillars having different polygonal cross-sectional shape. If a particular recess is intended for forming a cavity sidewall 303A, that recess 45 can be a hole or a trench depending on whether the cavity sidewall 303A is formed from a plurality of TIVs, two or more solid segments, or a single solid wall-like structure. The recesses 45 will have a depth that can form the TIVs and the cavity sidewalls 303A with a desired height. In typical InFO packages, the recesses 45 will be sufficiently deep to form TIVs 303 having a height of about 120-250 μm. The height of the TIVs 303 is determined by the thickness of the subsequently placed IC dies, such as the RF IC die 310 in the example InFO package 300.
Referring to FIG. 21, a thin seed layer of Ti/Cu (1000/5000 Å thick) (not shown) is formed on the structure of FIG. 20 in preparation for electroplating deposition of the TIVs 303 and the cavity sidewalls 303A so that the seed layer is covering the surfaces of the photoresist 40 and the exposed back-side redistribution metal layer 500, such as the ground plane structure 510 at the bottom of the recesses 45. Next, the metal features such as the TIVs 303 and the cavity sidewalls 303A are formed by filling the recesses 45 in the photoresist 40 with conductive metal 60 by plating, which may be electro plating or electro-less plating, on the seed layer 50. The conductive metal 60 may comprise such conductive metals as copper, aluminum, tungsten, nickel, or alloys thereof.
Next, referring to FIG. 22, any excess portion of the conductive metal 60 is removed by a process such as chemical mechanical polishing (CMP), exposing the tops of the recesses 45 and the photoresist layer 40. The recesses are now filled with the conductive metal 60.
Next, the photoresist 40 is removed and the resulting structure is shown in FIG. 23. The recesses 45 in the photoresist 40 now form the TIVs 303 and the cavity sidewalls 303A structures.
FIG. 24 illustrates the placement of the RF IC die 310 on the back-side buffer layer 30. IC dies such as the RF IC die 30 can be adhered to the back-side buffer layer 30 using a die-attach-film (DAF) 36. The RF IC die 310 includes semiconductor substrate 35 (a silicon substrate, for example) whose back surface is in contact with the DAF 36. The RF IC die 310 includes metal pillars 315 (such as copper posts) that are formed as the top portions of the RF IC die 310 that electrically connects the RF IC die 310 to other conductive devices and interconnect structures in the InFO package 300. A dielectric layer 316 is formed at the top surface of the RF IC die 310 filling the spaces between the metal pillars 315, with the metal pillars 315 having at least their lower portions in the dielectric layer 316. In some embodiments, the top surface of the dielectric layer 316 can be level with the top surfaces of the metal pillars 315, as shown in the RF IC die 310.
Referring to FIG. 25, a molding compound 70 is applied over the RF IC die 310, the TIVs 303, and the cavity sidewalls 303A and cured. The molding compound 70 fills the gaps between the RF IC die 310, the TIVs 303, and the cavity sidewalls 303A, and may be in contact with any exposed portions of the back-side buffer layer 30 and the ground plane structure 510. The molding compound 70 may include a molding underfill, an epoxy, or a resin. Some suitable molding compounds can be liquid epoxys, such as liquid epoxy containing fine granular silica, liquid glass (SiO2) (spin on glass) or ceramics. Molding compounds such as the liquid epoxy can be applied as a coating, similar to photoresists, then low temperature (about 180° C.) cured and hardened. In some embodiments, the molding compound has a dielectric constant k of 2.8-3.0. Other embodiments include high-k or low-k molding materials. The molding compound 70 provided in sufficient amount to embed the RF IC die 310, the TIVs 303, and the cavity sidewalls 303A. At this stage, the top surface of the molding compound 70 is higher than the top ends of the metal pillars 315 on the RF IC die 310, the TIVs 303, and the cavity sidewalls 303A.
Next, a grinding step is performed to thin the molding compound 70 until the tops of the metal pillars 315, the TIVs 303, and the cavity sidewalls 303A are exposed. The grinding can be accomplished by CMP. The resulting interim substrate structure 300-I is shown in FIG. 26. The grinding leaves the top ends of the metal features, the metal pillars 315, the TIVs 303, and the cavity sidewalls 303A, to be substantially level (coplanar) along the top surface 72. The grinding step can leave behind some metal residue such as metal particles on the top surface 72. Accordingly, after the grinding step, a cleaning may be performed, for example, through a wet etching, to remove the metal residue. The cavity sidewalls 303A and their associated ground plane 510 define the antenna cavity 327. In the interim substrate structure 300-I, the molding compound at least laterally encapsulates the RF IC die 310 between a first surface 71 of the molding compound and a second surface 72 of the molding compound. The one or more TIVs 303 and the one or more cavity sidewalls 303A are in the molding compound and extend from the ground plane structure 510 to the second surface 72 of the molding compound, wherein the cavity sidewalls and their associated ground plane structure 510 define one or more antenna cavities 327.
Next, referring to FIG. 27, the first level conductor RDL-1 412 is formed by first forming a first top-side RDL layer 410. Forming the first top-side RDL layer 410 comprises depositing a layer of conductor metal (e.g. copper) 80 over the top surface 70A by plating, which may be electro plating or electro-less plating. In order to enable the electro plating, a very thin seed layer of Ti/Cu (1000/5000 Å thick) (not shown) is first deposited on the top surface 70A. Next, the layer of conductor metal 80 is patterned and etched, leaving behind the first level conductor RDL-1 412 structures over the TIVs 303 and the metal pillars 315 of the RF IC die 310. Then, a dielectric insulation layer (e.g. PBO) 81 is applied over the resulting structure. The dielectric insulation layer 81 is about 4.5 μm thick. This structure is shown in FIG. 28.
Forming the top-side redistribution wiring structure 400 is continued by patterning the dielectric insulation layer 81 and forming openings for vias which are then filled with conductor metal (e.g. copper) to form the RDL-1 vias 415 and completing the first top-side RDL layer 410. The top surface of the first top-side RDL layer 410 is ground and polished. Then the second top-side RDL layer 420 is formed on the first top-side RDL layer 410. In order to form the second top-side RDL layer 420, a layer of conductor metal (e.g. copper) is deposited over the first top-side RDL layer 410 then patterned and etched, leaving behind the second level conductor RDL-2 422 structures over the first top-side RDL layer 410. A dielectric insulation layer (e.g. PBO) 83 is then applied over the resulting structure. This structure is shown in FIG. 30.
As shown in FIG. 29 and as mentioned above, some of the second level conductor RDL-2 422 structures include the one or more patch antenna structures 427 according to the present disclosure. The patch antenna structures 427 are formed to be positioned over the antenna cavity 327 defined by the cavity sidewalls 303A and the ground plane 510.
Forming the top-side redistribution wiring structure 400 is continued by patterning the dielectric insulation layer 83 and forming openings for vias which are then filled with conductor metal (e.g. copper) to form the RDL-2 vias 425 and completing the second top-side RDL layer 420. The top surface of the second top-side RDL layer 420 is ground and polished. Then the third top-side RDL layer 430 is formed on the second top-side RDL layer 420. In order to form the third top-side RDL layer 430, a layer of conductor metal (e.g. copper) is deposited over the second top-side RDL layer 420 then patterned and etched, leaving behind the third level conductor RDL-3 432 structures over the second top-side RDL layer 420. A dielectric insulation layer (e.g. PBO) 85 is then applied over the resulting structure. This structure is shown in FIG. 30.
Forming the top-side redistribution wiring structure 400 is continued by patterning the dielectric insulation layer 85 and forming openings for under ball metal (UBM) pads 435 which are then filled with conductor metal (e.g. copper) to form the UBM pads 435 and completing the third top-side RDL layer 430. This structure is shown in FIG. 31.
FIG. 31 further shows the formation of the next level electrical interconnection structures 600 in accordance with some embodiments. In this embodiment, the electrical interconnection structures 600 are solder bumps attached to the exposed portions of the UBM pads 435. The solder bumps 600 can be formed by placing solder balls on the UBM pads 435 and then reflowing the solder balls. In alternative embodiments, the formation of the solder bumps 600 includes performing a plating step to form solder regions over the UBM pads 435, and then reflowing the solder regions. In other embodiments the electrical interconnection structures 600 can be metal pillars, or metal pillars and solder caps, which may also be formed through plating.
The RDL-1 412, RDL-1 vias 415, RDL-2 422, RDL-2 vias 425, RDL-3 432, and UBM pads 435 can comprise a metal or a metal alloy including aluminum, copper, tungsten, and/or alloys thereof.
In some embodiments, the dielectric insulation layers 81, 83, and 85 may comprise a polymer such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. Alternatively, the dielectric layers 81, 83, and 85 may include non-organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like.
Next, the InFO package 300 is debonded from the carrier 10. The adhesive layer 20 is also cleaned from the InFO package 300. The resulting final InFO package 300 is shown in FIG. 13.
FIGS. 33A-33B show a flow chart 700 of a method of manufacturing the InFO package 300 in accordance with some embodiments. Referring to block 702, the adhesive layer 20 is deposited on the carrier 10. Next, the back-side buffer layer 30 is formed over the adhesive layer 20. (See block 704). Next, one or more of the ground plane structures 510 are formed on the back-side buffer layer. (See block 706). Next, a coating of photoresist 40 is applied over the ground plane structure 510 and the exposed portions of the back-side buffer layer 30 and patterned to form openings or recesses 45 in the photoresist 40. (See block 708). Next, one or more TIVs 303 and one or more cavity sidewalls 303A are formed by filling the recesses 45 with conductive metal 60. (See block 710). Next, the excess portion of the conductive metal 60 is removed and planarized, exposing the tops of the recesses 45, which are now filled with the conductive metal 60, and the photoresist layer 40. (See block 712). Next, the photoresist 40 is removed leaving behind the TIVs 303 and the cavity sidewalls 303A structures. (See block 714). Next, the RF IC die 310 is placed on the back-side buffer layer 30. (See block 716).
Next, an encapsulating medium, such as a molding compound is flowed over the RF IC die 310, TIVs 303 and ground plane structures 510. An interim substrate structure 300-I that comprises the RF IC die, the one or more TIVs, the one or more cavity sidewalls, and a molding compound 70 is formed by laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with the molding compound, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities. (See block 717). In the interim substrate structure 300-I, the molding compound at least laterally encapsulates the RF IC die 310 between a first surface 71 of the molding compound and a second surface 72 of the molding compound. The one or more TIVs 303 and the one or more cavity sidewalls 303A are in the molding compound and extend from the ground plane structure 510 to the second surface 72 of the molding compound, wherein the cavity sidewalls and their associated ground plane structure 510 define one or more antenna cavities 327.
To form the interim substrate structure 300-I, a molding compound 70 is applied over the RF IC die 310, the TIVs 303, and the cavity sidewalls 303A, filling the gaps between the RF IC die 310, the TIVs 303, and the cavity sidewalls 303A, and cured. (See block 718). Next, the molding compound 70 is ground down until the tops of the metal pillars 315, the TIVs 303, and the cavity sidewalls 303A are exposed, thus forming the interim substrate structure 300-I. (See block 720). At this point, the cavity sidewalls 303A and their associated ground plane 510 define the antenna cavities 327 according to the present disclosure.
Next, a top-side RDL wiring structure 400 that includes one or more integrated patch antenna structure 427 is formed. (See block 721). As mentioned above, the one or more integrated patch antenna structure is coupled to the RF IC die 310 and each of the one or more integrated patch antenna structure is positioned over one of the antenna cavities 327. The forming of the top-side RDL wiring structure 400 comprises forming the first top-side RDL layer 410 on the ground surface of the interim substrate structure, wherein the first top-side RDL layer 410 including the first level conductor RDL-1 412 structures over the TIVs 303 and the metal pillars 315 of the RF IC die 310. (See block 722). Next, the second top-side RDL layer 420 is formed on the first top-side RDL layer 410, wherein the second top-side RDL layer 420 includes the second level conductor RDL-2 422 structures over the first top-side RDL layer 410, the second level conductor RDL-2 422 structures including the one or more patch antenna structures 427 that are positioned over the antenna cavity 327. (See block 724). Next, the third top-side RDL layer 430 is formed on the second top-side RDL layer 420, wherein the third top-side RDL layer 430 includes the third level conductor RDL-3 432 structures including the UBM pads 435. (See block 726). Next, the next level electrical interconnection structures 600 are formed on the UBM pads 435. (See block 728). Next, the carrier 10 is removed, thus forming the InFO package 300. (See block 730).
The InFO process is robust and, thus, the thickness of the InFO package 300 can be fabricated to be within a wide range of thickness. For example, the InFO package can be fabricated to have a thickness that is anywhere from 200 μm to 2.0 mm for the 5th generation high frequency RF transceiver application.
Although the subject matter has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments, which may be made by those skilled in the art.

Claims (20)

What is claimed is:
1. A method comprising:
forming an integrated fan-out package comprising:
depositing an adhesive layer on a carrier;
forming a back-side buffer layer over the adhesive layer;
forming a back-side redistribution metal layer on the back-side buffer layer, wherein the back-side redistribution metal layer includes one or more ground plane structures;
forming one or more through-insulator vias (TIVs) and one or more cavity sidewalls on the one or more ground plane structures;
placing a radio frequency (RF) integrated circuit (IC) die on the back-side buffer layer;
laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with a molding compound, thus forming an interim substrate, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities; and
forming a top-side redistribution (RDL) wiring structure on the interim substrate, the top-side RDL wiring structure including one or more integrated patch antenna structure, wherein the one or more integrated patch antenna structure is coupled to the RF IC die and each of the one or more integrated patch antenna structure is positioned over one of the antenna cavities.
2. The method of claim 1, wherein forming the top-side RDL wiring structure comprises:
forming a first top-side RDL layer on the interim substrate structure, wherein the first top-side RDL layer includes first level RDL conductor structures over the TIVs and the RF IC die; and
forming a second top-side RDL layer on the first top-side RDL layer, wherein the second top-side RDL layer includes second level RDL conductor structures over the first top-side RDL layer, wherein the second level RDL conductor structures includes the one or more patch antenna structures.
3. The method of claim 2, further comprising:
forming a third top-side RDL layer on the second top-side RDL layer, wherein the third top-side RDL layer includes third level RDL conductor structures, wherein the third level RDL conductor structures including one or more under ball metal (UBM) pads.
4. The method of claim 3, further comprising forming solder ball interconnection structures on the UBM pads.
5. The method of claim 4, further comprising removing the carrier.
6. The method of claim 1, wherein forming one or more TIVs and one or more cavity sidewalls on the one or more ground plane structures comprises:
applying a coating of photoresist over the one or more ground plane structure and any exposed portions of the back-side buffer layer;
patterning the photoresist to form recesses;
filling the recesses with a conductive metal to form the one or more TIVs and the one or more cavity sidewalls;
removing and planarizing a portion of the conductive metal exposing the tops of the recesses, and the photoresist layer, wherein the recesses are now filled with the conductive metal; and
removing the photoresist leaving behind the TIVs and the cavity sidewalls structures.
7. The method of claim 6, wherein forming the top-side RDL wiring structure comprises:
forming a first top-side RDL layer on the interim substrate structure, wherein the first top-side RDL layer includes first level RDL conductor structures over the TIVs and the RF IC die; and
forming a second top-side RDL layer on the first top-side RDL layer, wherein the second top-side RDL layer includes second level RDL conductor structures over the first top-side RDL layer, wherein the second level RDL conductor structures includes the one or more patch antenna structures.
8. The method of claim 7, further comprising:
forming a third top-side RDL layer on the second top-side RDL layer, wherein the third top-side RDL layer includes third level RDL conductor structures, wherein the third level RDL conductor structures including one or more under ball metal (UBM) pads.
9. The method of claim 8, further comprising forming solder ball interconnection structures on the UBM pads.
10. The method of claim 9, further comprising removing the carrier.
11. A method comprising:
forming an integrated fan-out package comprising:
depositing an adhesive layer on a carrier;
forming a back-side buffer layer over the adhesive layer;
forming a back-side redistribution metal layer on the back-side buffer layer, wherein the back-side redistribution metal layer includes one or more ground plane structures;
forming one or more through-insulator vias (TIVs) and one or more cavity sidewalls on the one or more ground plane structures;
placing a radio frequency (RF) integrated circuit (IC) die on the back-side buffer layer;
laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with a molding compound, wherein the laterally encapsulating comprises:
applying the molding compound over the RF IC die, the one or more TIVs, and the one or more cavity sidewalls;
curing the molding compound; and
grinding the molding compound until tops of the TIVs, the cavity sidewalls, and metal pillars on the RF IC die are exposed, thus forming an interim substrate structure, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities; and
forming a top-side redistribution (RDL) wiring structure on the interim substrate, the top-side RDL wiring structure including one or more integrated patch antenna structure,
wherein the one or more integrated patch antenna structure is coupled to the RF IC die and each of the one or more integrated patch antenna structure is positioned over one of the antenna cavities.
12. The method of claim 11, wherein forming the top-side RDL wiring structure comprises:
forming a first top-side RDL layer on the ground surface of the interim substrate structure, wherein the first top-side RDL layer includes first level RDL conductor structures over the TIVs and the RF IC die; and
forming a second top-side RDL layer on the first top-side RDL layer, wherein the second top-side RDL layer includes second level RDL conductor structures over the first top-side RDL layer, wherein the second level RDL conductor structures includes the one or more patch antenna structures.
13. The method of claim 12, further comprising:
forming a third top-side RDL layer on the second top-side RDL layer, wherein the third top-side RDL layer includes third level RDL conductor structures, wherein the third level RDL conductor structures including one or more under ball metal (UBM) pads.
14. The method of claim 13, further comprising forming solder ball interconnection structures on the UBM pads.
15. The method of claim 14, further comprising removing the carrier.
16. A method comprising:
forming an integrated fan-out package comprising:
depositing an adhesive layer on a carrier;
forming a back-side buffer layer over the adhesive layer;
forming a back-side redistribution metal layer on the back-side buffer layer, wherein the back-side redistribution metal layer includes one or more ground plane structures;
applying a coating of photoresist over the one or more ground plane structure and any exposed portions of the back-side buffer layer;
patterning the photoresist to form recesses;
filling the recesses with a conductive metal to form the one or more through-insulator vias (TIVs) and one or more cavity sidewalls;
removing and planarizing a portion of the conductive metal exposing the tops of the recesses, and the photoresist layer, wherein the recesses are now filled with the conductive metal;
removing the photoresist leaving behind the TIVs and the cavity sidewalls structures;
placing a radio frequency (RF) integrated circuit (IC) die on the back-side buffer layer;
laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with a molding compound, thus forming an interim substrate, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities; and
forming a top-side redistribution (RDL) wiring structure on the interim substrate, the top-side RDL wiring structure including one or more integrated patch antenna structure, wherein the one or more integrated patch antenna structure is coupled to the RF IC die and each of the one or more integrated patch antenna structure is positioned over one of the antenna cavities.
17. The method of claim 16, wherein forming the top-side RDL wiring structure comprises:
forming a first top-side RDL layer on the interim substrate structure, wherein the first top-side RDL layer includes first level RDL conductor structures over the TIVs and the RF IC die; and
forming a second top-side RDL layer on the first top-side RDL layer, wherein the second top-side RDL layer includes second level RDL conductor structures over the first top-side RDL layer, wherein the second level RDL conductor structures includes the one or more patch antenna structures.
18. The method of claim 17, further comprising:
forming a third top-side RDL layer on the second top-side RDL layer, wherein the third top-side RDL layer includes third level RDL conductor structures, wherein the third level RDL conductor structures including one or more under ball metal (UBM) pads.
19. The method of claim 18, further comprising forming solder ball interconnection structures on the UBM pads.
20. The method of claim 19, further comprising removing the carrier.
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180158787A1 (en) * 2016-12-02 2018-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US20180315706A1 (en) * 2017-04-26 2018-11-01 Taiwan Semiconductor Manufacturing Company Limited Integrated Fan-Out Package with 3D Magnetic Core Inductor
US20190304934A1 (en) * 2018-03-27 2019-10-03 Nxp B.V. Multi-die and antenna array device
US10460959B2 (en) * 2018-03-15 2019-10-29 Powertech Technology Inc. Package structure and manufacturing method thereof
US20200212536A1 (en) * 2018-12-31 2020-07-02 Texas Instruments Incorporated Wireless communication device with antenna on package
US10734279B2 (en) * 2017-05-09 2020-08-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
US11069633B2 (en) * 2018-01-10 2021-07-20 Siliconware Precision Industries Co., Ltd. Electronic package
US11239175B2 (en) 2019-06-21 2022-02-01 Samsung Electronics Co., Ltd. Semiconductor package
TWI757674B (en) * 2018-12-28 2022-03-11 台灣積體電路製造股份有限公司 Package and package method thereof
US11362426B2 (en) 2018-06-21 2022-06-14 Samsung Electronics Co., Ltd Antenna module comprising cavity
US11362429B2 (en) 2020-09-24 2022-06-14 Apple Inc. Electronic devices having antennas with loaded dielectric apertures
US11532867B2 (en) 2018-12-28 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous antenna in fan-out package

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160163634A1 (en) * 2014-10-03 2016-06-09 Edward Seymour Power reduced computing
TWI562275B (en) * 2014-11-27 2016-12-11 Advance Process Integrate Technology Ltd Process of forming waferless interposer
US20170040266A1 (en) 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
US9953936B2 (en) * 2015-10-30 2018-04-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10128203B2 (en) * 2016-02-02 2018-11-13 Taiwan Semiconductor Manufacturing Company Ltd. Fan-out package structure, antenna system and associated method
US10062648B2 (en) 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
KR102019352B1 (en) * 2016-06-20 2019-09-09 삼성전자주식회사 Fan-out semiconductor package
US9741690B1 (en) 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US10037951B2 (en) * 2016-11-29 2018-07-31 Cyntec Co., Ltd. Semiconductor package with antenna
US10593634B2 (en) 2016-12-30 2020-03-17 Analog Devices, Inc. Packaged devices with integrated antennas
US10396432B2 (en) * 2017-01-23 2019-08-27 Samsung Electro-Mechanics Co., Ltd. Antenna-integrated radio frequency module
US10354964B2 (en) 2017-02-24 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated devices in semiconductor packages and methods of forming same
US10522492B2 (en) * 2017-06-05 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor package and semiconductor process
US10186492B1 (en) * 2017-07-18 2019-01-22 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US11394103B2 (en) 2017-07-18 2022-07-19 Samsung Electro-Mechanics Co., Ltd. Antenna module and manufacturing method thereof
KR102019952B1 (en) * 2017-07-18 2019-09-11 삼성전기주식회사 Antenna module and manufacturing method thereof
US10461034B2 (en) 2017-07-26 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10134685B1 (en) * 2017-07-27 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of fabricating the same
US10700024B2 (en) * 2017-08-18 2020-06-30 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR102400748B1 (en) 2017-09-12 2022-05-24 삼성전자 주식회사 Electronic device including interposer
US10411328B2 (en) 2017-09-15 2019-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Patch antenna structures and methods
US11024979B2 (en) * 2017-09-29 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. 3D IC antenna array with laminated high-k dielectric
CN107706521B (en) * 2017-10-25 2023-11-17 盛合晶微半导体(江阴)有限公司 Fan-out type antenna packaging structure and preparation method thereof
CN107742778A (en) * 2017-10-25 2018-02-27 中芯长电半导体（江阴）有限公司 Fan-out-type antenna packages structure and preparation method thereof
US10700410B2 (en) * 2017-10-27 2020-06-30 Mediatek Inc. Antenna-in-package with better antenna performance
KR102019354B1 (en) * 2017-11-03 2019-09-09 삼성전자주식회사 Antenna module
DE102018106038A1 (en) 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. INTEGRATED CIRCUIT PACKAGES AND METHOD FOR THE PRODUCTION THEREOF
US11410918B2 (en) * 2017-11-15 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making an integrated circuit package including an integrated circuit die soldered to a bond pad of a carrier
KR102028714B1 (en) * 2017-12-06 2019-10-07 삼성전자주식회사 Antenna module and manufacturing method thereof
KR102025906B1 (en) * 2017-12-06 2019-11-04 삼성전자주식회사 Antenna module
TWI663781B (en) * 2017-12-26 2019-06-21 國家中山科學研究院 Multi-frequency antenna packaging structure
KR102022353B1 (en) * 2018-01-18 2019-09-18 삼성전기주식회사 Antenna module
KR102003840B1 (en) * 2018-03-12 2019-07-25 삼성전자주식회사 Antenna module
US11296038B2 (en) 2018-04-03 2022-04-05 Corning Incorporated Precision structured glass article having EMI shielding and methods for making the same
US11764117B2 (en) 2018-04-03 2023-09-19 Corning Incorporated Hermetically sealed optically transparent wafer-level packages and methods for making the same
US11189905B2 (en) 2018-04-13 2021-11-30 International Business Machines Corporation Integrated antenna array packaging structures and methods
CN108417982B (en) * 2018-05-09 2024-03-08 盛合晶微半导体(江阴)有限公司 Antenna packaging structure and packaging method
US11024954B2 (en) 2018-05-14 2021-06-01 Mediatek Inc. Semiconductor package with antenna and fabrication method thereof
US20190348747A1 (en) 2018-05-14 2019-11-14 Mediatek Inc. Innovative air gap for antenna fan out package
US11043730B2 (en) 2018-05-14 2021-06-22 Mediatek Inc. Fan-out package structure with integrated antenna
US11894322B2 (en) * 2018-05-29 2024-02-06 Analog Devices, Inc. Launch structures for radio frequency integrated device packages
US11424196B2 (en) 2018-06-01 2022-08-23 Analog Devices, Inc. Matching circuit for integrated circuit die
US10490479B1 (en) * 2018-06-25 2019-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. Packaging of semiconductor device with antenna and heat spreader
DE102019112940B4 (en) 2018-06-29 2022-09-29 Infineon Technologies Ag Semiconductor devices with cavities in an encapsulation material and related manufacturing processes
US11081453B2 (en) 2018-07-03 2021-08-03 Mediatek Inc. Semiconductor package structure with antenna
US10804188B2 (en) * 2018-09-07 2020-10-13 Intel Corporation Electronic device including a lateral trace
US11417615B2 (en) 2018-11-27 2022-08-16 Analog Devices, Inc. Transition circuitry for integrated circuit die
US11502402B2 (en) * 2019-03-15 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated patch antenna having insulating substrate with antenna cavity and high-K dielectric
EP3719841B1 (en) * 2019-04-01 2022-02-16 Detection Technology Oy Radiation sensor element and method
US11430750B2 (en) * 2019-05-29 2022-08-30 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an antenna formed over a foaming agent filled cavity in a support layer
US11088098B2 (en) * 2019-08-12 2021-08-10 Viasat, Inc. Integrated structures with antenna elements and IC chips employing edge contact connections
US11749625B2 (en) * 2020-04-17 2023-09-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure including one or more antenna structures
KR20210157595A (en) 2020-06-22 2021-12-29 삼성전자주식회사 Semiconductor package
KR20220015193A (en) * 2020-07-30 2022-02-08 삼성전자주식회사 Semiconductor package
US20220278032A1 (en) * 2021-02-26 2022-09-01 Intel Corporation Nested interposer with through-silicon via bridge die
US20220407205A1 (en) * 2021-06-16 2022-12-22 Intel Corporation Contactless communication using a waveguide extending through a substrate core
US20230090365A1 (en) * 2021-09-23 2023-03-23 Texas Instruments Incorporated Fan-out package with antenna
US11744021B2 (en) 2022-01-21 2023-08-29 Analog Devices, Inc. Electronic assembly
US20230402408A1 (en) * 2022-06-08 2023-12-14 Nxp Usa, Inc. Semiconductor device with enclosed cavity and method therefor
CN116888734A (en) * 2022-10-24 2023-10-13 广东省科学院半导体研究所 Fan-out type packaging structure and preparation method thereof

Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100193935A1 (en) 2009-01-30 2010-08-05 Infineon Technologies Ag Integrated antennas in wafer level package
US20100219513A1 (en) 2007-03-09 2010-09-02 Nanyang Technological University Integrated circuit structure and a method of forming the same
US7852281B2 (en) 2008-06-30 2010-12-14 Intel Corporation Integrated high performance package systems for mm-wave array applications
US7943404B2 (en) 2008-08-07 2011-05-17 International Business Machines Corporation Integrated millimeter wave antenna and transceiver on a substrate
US8269671B2 (en) 2009-01-27 2012-09-18 International Business Machines Corporation Simple radio frequency integrated circuit (RFIC) packages with integrated antennas
US8407890B2 (en) 2010-01-25 2013-04-02 Freescale Semiconductor Inc. Method of manufacting an electronic device module with integrated antenna structure
US8451618B2 (en) 2010-10-28 2013-05-28 Infineon Technologies Ag Integrated antennas in wafer level package
US20140110856A1 (en) 2012-10-19 2014-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Wafer Level Package Structure
US8759950B2 (en) 2011-05-05 2014-06-24 Intel Corporation Radio- and electromagnetic interference through-silicon vias for stacked-die packages, and methods of making same
US20140184460A1 (en) 2013-01-03 2014-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna structures
US20150048471A1 (en) 2012-03-02 2015-02-19 Robert Bosch Gmbh Semiconductor module having an integrated waveguide for radar signals
US20150061148A1 (en) 2013-08-30 2015-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. 3d ic with serial gate mos device, and method of making the 3d ic
US20150069623A1 (en) 2013-09-11 2015-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer
US20150084814A1 (en) * 2012-03-14 2015-03-26 Israel Aerospace Industries Ltd. Phased array antenna
US20150102502A1 (en) 2013-09-11 2015-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Structure with Openings in Buffer Layer
US20150198662A1 (en) 2014-01-10 2015-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out wafer architecture and test method
US20150364830A1 (en) * 2014-06-13 2015-12-17 Freescale Semiconductor, Inc. Integrated circuit package with radio frequency coupling structure
US9431369B2 (en) 2012-12-13 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna apparatus and method
US9496593B2 (en) 2011-02-21 2016-11-15 Siklu Communication ltd. Enhancing operation of laminate waveguide structures using an electrically conductive fence
US9548279B2 (en) 2013-09-25 2017-01-17 Kabushiki Kaisha Toshiba Connection member, semiconductor device, and stacked structure

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100219513A1 (en) 2007-03-09 2010-09-02 Nanyang Technological University Integrated circuit structure and a method of forming the same
US7852281B2 (en) 2008-06-30 2010-12-14 Intel Corporation Integrated high performance package systems for mm-wave array applications
US7943404B2 (en) 2008-08-07 2011-05-17 International Business Machines Corporation Integrated millimeter wave antenna and transceiver on a substrate
US8269671B2 (en) 2009-01-27 2012-09-18 International Business Machines Corporation Simple radio frequency integrated circuit (RFIC) packages with integrated antennas
US20100193935A1 (en) 2009-01-30 2010-08-05 Infineon Technologies Ag Integrated antennas in wafer level package
US8407890B2 (en) 2010-01-25 2013-04-02 Freescale Semiconductor Inc. Method of manufacting an electronic device module with integrated antenna structure
US8451618B2 (en) 2010-10-28 2013-05-28 Infineon Technologies Ag Integrated antennas in wafer level package
US20130241059A1 (en) 2010-10-28 2013-09-19 Infineon Technologies Ag Integrated Antennas in Wafer Level Package
US9496593B2 (en) 2011-02-21 2016-11-15 Siklu Communication ltd. Enhancing operation of laminate waveguide structures using an electrically conductive fence
US8759950B2 (en) 2011-05-05 2014-06-24 Intel Corporation Radio- and electromagnetic interference through-silicon vias for stacked-die packages, and methods of making same
US20150048471A1 (en) 2012-03-02 2015-02-19 Robert Bosch Gmbh Semiconductor module having an integrated waveguide for radar signals
US20150084814A1 (en) * 2012-03-14 2015-03-26 Israel Aerospace Industries Ltd. Phased array antenna
US20140110856A1 (en) 2012-10-19 2014-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Wafer Level Package Structure
US9431369B2 (en) 2012-12-13 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna apparatus and method
US20140184460A1 (en) 2013-01-03 2014-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna structures
US20150061148A1 (en) 2013-08-30 2015-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. 3d ic with serial gate mos device, and method of making the 3d ic
US20150102502A1 (en) 2013-09-11 2015-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Structure with Openings in Buffer Layer
US20150069623A1 (en) 2013-09-11 2015-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer
US9548279B2 (en) 2013-09-25 2017-01-17 Kabushiki Kaisha Toshiba Connection member, semiconductor device, and stacked structure
US20150198662A1 (en) 2014-01-10 2015-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out wafer architecture and test method
US20150364830A1 (en) * 2014-06-13 2015-12-17 Freescale Semiconductor, Inc. Integrated circuit package with radio frequency coupling structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Tsai, C.H. et al., "Array Antenna Integrated Fan-out Wafer Level Packaging (InFO-WLP) for Millimeter Wave System Applications", 2013 IEEE International Electron Devices Meeting (IEDM), Dec. 2013, pp. 25.1.1.-25.1.4.

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163824B2 (en) * 2016-12-02 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10304790B2 (en) * 2016-12-02 2019-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating an integrated fan-out package
US20180158787A1 (en) * 2016-12-02 2018-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US20180315706A1 (en) * 2017-04-26 2018-11-01 Taiwan Semiconductor Manufacturing Company Limited Integrated Fan-Out Package with 3D Magnetic Core Inductor
US11688685B2 (en) 2017-04-26 2023-06-27 Taiwan Semiconductor Manufacturing Company Limited Integrated fan-out package with 3D magnetic core inductor
US10923417B2 (en) * 2017-04-26 2021-02-16 Taiwan Semiconductor Manufacturing Company Limited Integrated fan-out package with 3D magnetic core inductor
US11295979B2 (en) * 2017-05-09 2022-04-05 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
US10734279B2 (en) * 2017-05-09 2020-08-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
US11069633B2 (en) * 2018-01-10 2021-07-20 Siliconware Precision Industries Co., Ltd. Electronic package
US10460959B2 (en) * 2018-03-15 2019-10-29 Powertech Technology Inc. Package structure and manufacturing method thereof
US20190304934A1 (en) * 2018-03-27 2019-10-03 Nxp B.V. Multi-die and antenna array device
US10593635B2 (en) * 2018-03-27 2020-03-17 Nxp B.V. Multi-die and antenna array device
US11362426B2 (en) 2018-06-21 2022-06-14 Samsung Electronics Co., Ltd Antenna module comprising cavity
TWI757674B (en) * 2018-12-28 2022-03-11 台灣積體電路製造股份有限公司 Package and package method thereof
US11532867B2 (en) 2018-12-28 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous antenna in fan-out package
US11996606B2 (en) 2018-12-28 2024-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous antenna in fan-out package
US20200212536A1 (en) * 2018-12-31 2020-07-02 Texas Instruments Incorporated Wireless communication device with antenna on package
US11239175B2 (en) 2019-06-21 2022-02-01 Samsung Electronics Co., Ltd. Semiconductor package
US11362429B2 (en) 2020-09-24 2022-06-14 Apple Inc. Electronic devices having antennas with loaded dielectric apertures

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