CN107689333B - 半导体封装件及其形成方法 - Google Patents
半导体封装件及其形成方法 Download PDFInfo
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- CN107689333B CN107689333B CN201710543411.9A CN201710543411A CN107689333B CN 107689333 B CN107689333 B CN 107689333B CN 201710543411 A CN201710543411 A CN 201710543411A CN 107689333 B CN107689333 B CN 107689333B
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- photoresist
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- seed layer
- integrated circuit
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Classifications
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Abstract
一种方法实施例包括在晶种层上方形成图案化的第一光刻胶。图案化的第一光刻胶中的第一开口暴露晶种层。该方法还包括在晶种层上且在第一开口中镀第一导电材料,去除图案化的第一光刻胶,并且在去除图案化的第一光刻胶之后,在第一导电材料上方形成图案化的第二光刻胶。图案化的第二光刻胶中的第二开口暴露第一导电材料的部分。该方法还包括在第二开口中且在第一导电材料上镀第二导电材料,去除图案化的第二光刻胶,并且在去除图案化的第二光刻胶之后,在第一导电材料和第二导电材料周围沉积介电层。本发明的实施例还涉及半导体封装件及其形成方法。
Description
技术领域
本发明的实施例涉及半导体封装件及其形成方法。
背景技术
由于许多电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的不断提高,半导体产业经历了快速增长。在大多数情况下,集成密度的提高是由最小部件尺寸的反复减小引起的,这允许将更多的组件集成到给定区域中。随着对缩小电子器件的需求的增长,已经出现了对更小和更具创造性的半导体管芯封装技术的需求。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中,在底部半导体封装件的顶部上堆叠顶部半导体封装件以提供高水平的集成密度和组件密度。PoP技术通常使得能够在印刷电路板(PCB)上生产具有增强的功能和小占用面积的半导体器件。
发明内容
本发明的实施例提供了一种形成半导体封装件的方法,包括:在晶种层上方形成图案化的第一光刻胶,其中,所述图案化的第一光刻胶中的第一开口暴露所述晶种层;在所述第一开口中且在所述晶种层上镀第一导电材料;去除所述图案化的第一光刻胶;在去除所述图案化的第一光刻胶之后,在所述第一导电材料的侧壁上方且沿着所述第一导电材料的所述侧壁形成图案化的第二光刻胶,其中,所述图案化的第二光刻胶的第二开口暴露所述第一导电材料的部分;在所述第二开口中且在所述第一导电材料上镀第二导电材料;去除所述图案化的第二光刻胶;在去除所述图案化的第二光刻胶之后,去除所述晶种层的暴露部分;以及在所述第一导电材料和所述第二导电材料周围沉积介电层。
本发明的另一实施例提供了一种形成半导体封装件的方法,包括:将集成电路管芯密封在密封剂中;在所述密封剂和所述集成电路管芯上方沉积第一光刻胶;在所述第一光刻胶中图案化第一开口以暴露第一导电材料;在所述第一开口中镀导电通孔,其中,所述导电通孔电连接至所述集成电路管芯;去除所述第一光刻胶;在所述导电通孔周围沉积第一聚合物层,其中,所述第一聚合物层和所述第一光刻胶包括不同的材料;以及平坦化所述第一聚合物层,使得所述第一聚合物层和所述导电通孔的顶面齐平。
本发明的又一实施例提供了一种半导体封装件,包括:集成电路管芯;密封剂,设置在所述集成电路管芯周围;贯通孔,延伸穿过所述密封剂;以及再分布结构,位于所述集成电路管芯和所述密封剂上方,其中,所述再分布结构的金属化图案包括:导线,设置在介电层中并且电连接至所述集成电路管芯,其中,所述介电层接触所述密封剂的顶面;以及导电通孔,位于所述导线上方且电连接至所述导线,其中,所述导电通孔的顶面与所述介电层的顶面齐平。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1至图36示出根据一些实施例的形成半导体器件封装件的各个中间阶段。
图37至图40示出根据一些其他实施例的形成半导体器件封装件的各个中间阶段。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
各个实施例提供了在半导体封装件的再分布层(RDL)中形成诸如导线和/或通孔的导电部件的方法。尽管相对于特定的上下文(例如,具有扇出RDL的集成扇出(InFO)封装件)描述了各个实施例,但是各种导电部件制造方法可以应用于器件的发现导电部件的任何区域中的其他封装件。各个实施例可以提供一个或多个以下非限制性优势:通过使用较高分辨率的光刻胶来限定导电通孔的形状的较小的导电通孔;较低的制造成本;减少的聚合物层分辨率窗口问题;再分布层中的改进的平坦性等。
图1至图36示出根据一些实施例的在用于形成第一封装件结构的工艺期间的中间步骤的截面图。图1示出载体衬底100和形成在载体衬底100上的释放层102。分别示出用于形成第一封装件和第二封装件的第一封装件区域600和第二封装件区域602。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆,从而使得多个封装件可以同时形成在载体衬底100上。释放层102可以由聚合物基材料形成,释放层可以与载体衬底100一起从在后续步骤中将要形成的上面的结构中去除。在一些实施例中,释放层102是诸如光热转换(LTHC)释放涂层的环氧树脂基热释放材料,该材料在被加热时失去其粘性。在其他实施例中,释放层102可为紫外线(UV)胶,其在暴露于UV光时失去其粘性。释放层102可以以液体形式分配并且被固化,可以是层压在载体衬底100上的层压膜等。可使释放层102的顶面齐平并且顶面可具有高度的共面性。
在图2中,形成介电层104和金属化图案106。如图2所示,在释放层102上形成介电层104。介电层104的底面可以与释放层102的顶面接触。在一些实施例中,介电层104由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其他实施例中,介电层104由诸如氮化硅的氮化物;诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等的氧化物形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺来形成介电层104。
在介电层104上形成金属化图案106。作为实例,为了形成金属化图案106,在介电层104上方形成晶种层(未示出)。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。例如,晶种层可以包括钛、铜、钼、钨、氮化钛、钛钨、它们的组合等。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中且在晶种层的暴露的部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括例如铜、钛、钨、铝等的金属。然后,去除光刻胶以及晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案106。
介电层104和金属化图案106可以称为背侧再分布结构110。如所示出的,背侧再分布结构110包括一个介电层104和一个金属化图案106。在其他实施例中,背侧再分布结构110可以包括介电层、金属化图案和通孔的任何数量。
例如,在实施例中,在金属化图案106和介电层104上可选地形成额外的介电层(未示出)。在一些实施例中,额外的介电层由聚合物形成,该聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,额外的介电层由诸如氮化硅的氮化物;诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。可以通过旋涂、层压、CVD等或它们的组合来形成额外的介电层。然后图案化额外的介电层以形成开口以暴露金属化图案106的部分。当介电层是光敏材料时,诸如通过将介电层暴露于光的可接受的工艺实施图案化,或者例如,通过使用各向异性蚀刻的蚀刻来实施图案化。后续形成的导电部件可以通过形成在额外的介电层的开口中的导电通孔电连接至金属化图案106。
通过重复用于形成金属化图案106和可选的额外的介电层(未示出)的工艺,可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料的金属化图案的形成期间形成通孔。可选地,可使用下文中关于图9至图32所描述的实施例通孔形成工艺来形成通孔。通孔可以因此互连且电连接各个金属化图案。
另外,在图3中,形成贯通孔112。作为形成贯通孔112的实例,在例如介电层104和金属化图案106的背侧再分布结构110上方形成晶种层。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。例如,晶种层可以包括钛、铜、钼、钨、氮化钛、钛钨、它们的组合等。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于贯通孔112。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中且在晶种层的暴露的部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括例如铜、钛、钨、铝等的金属。去除光刻胶以及晶种层的在其上未形成导电材料的部分。通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成贯通孔112。在其他实施例中,省略了晶种层,并且金属化图案106用作用于形成贯通孔112的晶种层。
在图4中,集成电路管芯114通过粘合剂116粘附至背侧再分布结构110。例如,粘合剂116可以粘附至金属化图案106的顶面,并且粘合剂116可以沿着金属化图案106的侧壁进一步延伸。在其他实施例中,例如当额外的介电层(未示出)可选地形成在金属化图案106上方时,粘合剂116可以粘附至可选的额外的介电层的顶面。
如图4所示,在第一封装件区域600和第二封装件区域602的每个中均粘附两个集成电路管芯114,并且在其他实施例中,可以在每个区域中粘附或多或少的集成电路管芯114。例如,在实施例中,可以在每个区域中仅粘附一个集成电路管芯114。集成电路管芯114可以是逻辑管芯(例如,中央处理单元、微控制器等)、存储器管芯(例如,动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、功率管理管芯(例如,功率管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如,数字信号处理(DSP)管芯)、前端管芯(例如,模拟前端(AFE)管芯)等或它们的组合。此外,在一些实施例中,集成电路管芯114可以具有不同的尺寸(例如,不同的高度和/或表面积),并且在其他实施例中,集成电路管芯114可以具有相同的尺寸(例如,相同的高度和/或表面积)。
在粘附至介电层104之前,集成电路管芯114可以根据可接受的制造工艺来处理以在集成电路管芯114中形成集成电路。例如,每个集成电路管芯114包括诸如掺杂或未掺杂的硅的半导体衬底118或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括:其他半导体材料,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。还可以使用诸如多层或梯度衬底的其他衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上并且可以通过互连结构120互连以形成集成电路,互连结构124由例如半导体衬底118上的一个或多个介电层中的金属化图案形成。
集成电路管芯114还包括诸如铝焊盘的焊盘122,制造至该焊盘的外部连接。焊盘122位于可以称为集成电路管芯114的对应的有源侧上。钝化膜124位于集成电路管芯114上且位于焊盘122的部分上。开口穿过钝化膜124至焊盘122。诸如导电柱(例如,包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中并且机械和电连接至对应的焊盘122。例如,可以通过镀等形成管芯连接件126。管芯连接件126电连接集成电路管芯114的对应的集成电路。
介电材料128位于集成电路管芯114的有源侧上(诸如位于钝化膜124和管芯连接件126上)。介电材料128横向密封管芯连接件126,并且介电材料128与对应的集成电路管芯114横向上共末端。介电材料128可以是诸如PBO、聚酰亚胺、BCB等的聚合物;诸如氮化硅等的氮化物;诸如氧化硅、PSG、BSG、BPSG等的氧化物等;或它们的组合,并且例如可以通过旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯114的背侧上并且将集成电路管芯114粘附至诸如示出的金属化图案106的背侧再分布结构110。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。可以对诸如对应的半导体晶圆的背侧的集成电路管芯114的背侧施加粘合剂116或可以在载体衬底100的表面上方施加粘合剂116。可以通过诸如锯切或切割来分割集成电路管芯114,并且使用例如拾取和放置工具通过粘合剂116将集成电路管芯粘附至介电层104。
在图5中,在各个组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等,并且可以通过压缩模制、传递模制等来施加。在固化之后,密封剂130可以经受研磨工艺以暴露贯通孔112和管芯连接件126。在研磨工艺之后,贯通孔112、管芯连接件126和密封剂130的顶面是共面的。在一些实施例中,例如,如果贯通孔112和管芯连接件126已经暴露,则可以省略研磨。
在图6至图8中,形成前侧再分布结构144。如图8将要示出的,前侧再分布结构144包括金属化图案132、136、140和141以及介电层134、138和142。首先参考图6,在密封剂130、贯通孔112和管芯连接件126上形成金属化图案132和介电层134。金属化图案132可以包括导线132A和导电通孔132B。在密封剂130、贯通孔112和管芯连接件126上直接形成导线132A。例如,在导线132A和贯通孔112/管芯连接件126之间可以没有中间互连部件(例如,其他导线和/或通孔)。取决于期望的布局设计,导线132A可以提供电路由以将电信号(例如,去往/来自贯通孔112和/或管芯连接件126)路由至不同的物理位置。在导线132A上方形成导电通孔132B,并且导电通孔132B允许电信号传递到上层,例如上部金属化图案136、140和141(参见图7和图8)。在金属化图案132周围形成介电层134。在一些实施例中,介电层134由聚合物形成,聚合物是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层134由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG)等形成。可以使用诸如在图9至图17、图18至图20、图21至图23和/或图24至图32的实施例中描述的工艺的任何合适的形成工艺形成金属化图案132和介电层134。
参考图7,在金属化图案132和介电层134上方形成金属化图案136和介电层138。金属化图案136包括导线136A和导电通孔136B。可以在金属化图案132和介电层134上直接形成导线136A。例如,在导线136A和金属化图案132的导电通孔132B之间没有中间互连部件(例如,其他导线和/或通孔)。取决于期望的布局设计,导线136A可以提供电路由以将电信号(例如,去往/来自导电通孔132B)路由至不同的物理位置。在导线136A上方形成导电通孔136B,并且导电通孔136B允许电信号传递至上层,例如上部金属化图案140和141(参见图8)。在金属化图案136周围形成介电层138。在一些实施例中,介电层138由聚合物形成,聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层138由诸如氮化硅的氮化物;诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。可以使用诸如在图9至图17、图18至图20、图21至图23和/或图24至图32的实施例中描述的工艺的任何合适的形成工艺形成金属化图案136和介电层138。
参考图8,在金属化图案136和介电层138上方形成金属化图案140、金属化图案141和介电层142。金属化图案140包括可以在金属化图案136和介电层138上直接形成的导线。例如,在金属化图案140的导线和金属化图案136的导电通孔136B之间没有中间互连部件(例如,其他导线和/或通孔)。取决于期望的布局设计,金属化图案140的导线可以提供电路由以将电信号(例如,去往/来自导电通孔136B)路由至不同的物理位置。
还如图8所示出的,在金属化图案140上形成金属化图案141。金属化图案141用于连接至导电连接件148和/或表面安装器件(SMD)146(参见图33),并且可以称为凸块下金属(UBM)141。在示出的实施例中,UBM 141形成为贯穿介电层142至金属化图案140的开口。
在金属化图案140和UBM 141周围形成介电层142。在一些实施例中,介电层142由聚合物形成,聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层142由诸如氮化硅的氮化物;诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。可以使用诸如在图9至图17、图18至图20、图21至图23和/或图24至图32的实施例中描述的工艺的任何合适的形成工艺形成金属化图案140、UBM141和介电层142。
图9至17示出在介电层(例如,介电层134、138和/或142)中形成金属化图案(例如,金属化图案132、136、140和/或141)的各种中间步骤。参考图9,示出衬底150。衬底150可以是直接位于后续形成的金属化图案/介电层下面的任何层。例如,衬底150可以包括介电层中的金属化图案。可选地,衬底150可包括至集成电路管芯、密封剂和贯通孔的管芯连接件。在又一其他实施例中,衬底150可以包括任何合适的材料的组合,这取决于封装件设计。
仍如图9所示,在衬底150上方形成晶种层152。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。例如,晶种层152可以包括钛、铜、钼、钨、氮化钛、钛钨、它们的组合等。在一些实施例中,晶种层包括钛层152A和钛层152A上方的铜层152B。例如,可以使用PVD等形成晶种层152。在一些实施例中,衬底150的顶面(例如,其上形成晶种层152的表面)大致共面。当在衬底150的顶面上沉积晶种层152时,晶种层152的顶面可采用衬底150的顶面的轮廓。例如,晶种层152可以具有大致共面的顶面。
在图10和图11中,在晶种层152上形成和图案化第一掩模154。在一些实施例中,第一掩模是光刻胶并且在下文中可以称为第一光刻胶154。通过旋涂,第一光刻胶154可以形成为毯式层(参见图10)。在沉积第一光刻胶154之后,例如,可以通过图案化的光掩模将第一光刻胶154暴露于UV光或另一辐射源。然后可以显影第一光刻胶154,并且根据使用的是正性抗蚀剂还是负性抗蚀剂来去除第一光刻胶154的曝光或未曝光部分。在图11中示出所得的图案化的第一光刻胶156,其示出了具有延伸穿过其中的开口157的图案化的第一光刻胶156。图案化的第一光刻胶156的图案对应于金属化图案的导线158(参见图12)。开口157延伸穿过图案化的第一光刻胶156并且暴露晶种层152。
随后,在图12中,在图案化的第一光刻胶156(参见图11)的开口157中且在晶种层152的暴露的部分上形成导电材料(导线158的部分)。可以通过诸如电镀或化学镀等的镀形成导线158。导线158可以包括例如铜、钛、钨、铝等的金属。然后,如图12所示,通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除图案化的第一光刻胶156。导线158可以对应于图6至图8的导线132A、导线136A和/或金属化图案140。例如,可以使用类似于本文中所描述的导线158的工艺来形成导线132A、导电线136A和/或金属化图案140。
一旦去除图案化的第一光刻胶156,在晶种层152和导线158上方沉积第二掩模160。在一些实施例中,第二掩模是光刻胶并且在下文中可以称为第二光刻胶160。通过旋涂,第二光刻胶160可以形成为毯式层(参见图13)。在沉积第二光刻胶160之后,例如,可以通过图案化的光掩模将第二光刻胶160暴露于UV光或另一辐射源。然后可以显影第二光刻胶160,并且根据使用的是正性抗蚀剂还是负性抗蚀剂来去除第二光刻胶160的曝光或未曝光部分。在图15中示出具有延伸穿过其的开口161的所得的图案化的第二光刻胶162。图案化的第二光刻胶162的图案对应于金属化图案的导电通孔164(参见图15)。开口161延伸穿过图案化的第二光刻胶162并且暴露导线158。
在一些实施例中,图案化的第二光刻胶162和/或图案化的第一光刻胶156的材料可以支持相对高分辨率的光刻图案化,这允许形成相对细间距的开口。例如,在实施例中,每个开口161的宽度可以小于约1μm。通过采用高分辨率的光刻胶材料,开口161中的后续形成的部件(例如,导电通孔164,参见图15)可具有较小的尺寸。因此,可以有利地增加金属化部件的密度。在一些实施例中,图案化的第一光刻胶156和/或图案化的第二光刻胶162可以包括诸如三聚氰胺树脂、脲醛树脂、胍胺树脂、甘脲-甲醛树脂、琥珀酰胺-甲醛树脂、亚乙基脲-甲醛树脂和它们的组合的氨基化合物。
后续地,在图15中,在开口161(参见图14)中和导线158的暴露部分上形成导电材料(例如,导电通孔164)。形成导电通孔164使用导线158作为晶种层,而不为导电通孔164沉积单独的晶种层,这允许以相对低的制造成本来形成导电通孔164。可以通过诸如电镀或化学镀等的镀形成导电通孔164。导电通孔164可以包括例如铜、钛、钨、铝等的金属。然后,如图15所示,通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除图案化的第二光刻胶162。导电通孔164可以对应于图6至图8的导电通孔132B、导电通孔136B和/或UBM 141。例如,可以使用类似于本文所描述的导电通孔164的工艺来形成导电通孔136B、导电通孔132B和/或UBM 141。
在去除图案化的第二光刻胶162之后,诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)来去除晶种层152的暴露部分。晶种层152的剩余部分和导电材料形成包括导线158和导电通孔164的金属化图案。
在图16和图17中,在导线158和导电通孔164周围沉积介电层166。在一些实施例中,介电层166由聚合物形成,聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层166由诸如氮化硅的氮化物;诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。可通过旋涂、层压、CVD等或它们的组合形成介电层166。在介电层166包括光敏材料的实施例中,介电层166可以包括与第一光刻胶154(参见图10)和/或第二光刻胶160(参见图13)不同类型的材料。例如,第一光刻胶154和/或第二光刻胶160可比介电层166支持更高分辨率的光刻工艺。
如图16所示,可以首先形成介电层166以完全覆盖导线158和导电通孔164的顶面。后续地,可以对介电层166施加CMP或其他合适的平坦化工艺,以使介电层166的顶面齐平并暴露导电通孔164。介电层166可以对应于图6至图8的介电层134、介电层138和/或介电层142。例如,可以使用类似于介电层166的工艺来形成介电层134、介电层138和/或介电层142。随后地,可以在介电层166和导电通孔164上方形成额外的部件。例如,可以通过重复图9至图17中描述的工艺在介电层166上方形成位于介电层中的额外的金属化图案。
在图9至图17的工艺中,图案化的第二光刻胶162(参见图14)中的开口161与导线158对准,从而使得图案化的第二光刻胶162仅暴露导线158的顶面。在其他实施例中,图案化的第二光刻胶162暴露导线158的顶面以及导线158的侧壁。
例如,图18至图20示出根据一些实施例的形成金属化图案的各个中间步骤。在图18中,在导线158上方形成图案化的第二光刻胶162。图18的各种部件可以类似于图14中的部件,其中类似的参考标号表示使用类似的工艺(诸如,图9至图14中描述的那些工艺)形成的类似的元件。
如图18所示,在图案化的第二光刻胶162中形成开口168。开口168暴露导线158的顶面以及侧壁,并且可以通过导线158的材料以及图案化的第二光刻胶162的材料限定开口168的底面。在图18中,开口168仅部分地延伸穿过图案化的第二光刻胶162。例如,在开口168的底面和晶种层152的顶面之间设置图案化的第二光刻胶162的部分。例如,可以通过在光刻工艺期间控制曝光条件(例如,聚焦、能量等)来控制开口168的深度。
后续地,在图19中,在图案化的第二光刻胶162(参见图18)的开口168中且在导线158的暴露部分上形成导电材料(导电通孔170)。形成导电通孔170使用导线158作为晶种层,而不为导电通孔170沉积单独的晶种层,这允许以相对低的制造成本来形成导电通孔170。可以通过诸如电镀或化学镀等的镀来形成导电通孔170。导电通孔170可以包括例如铜、钛、钨、铝等的金属。然后,如图19所示,通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除图案化的第二光刻胶162。导电通孔170可以对应于图6至图8的导电通孔132B、导电通孔136B和/或UBM 141。例如,可以使用类似于本文所描述的导电通孔170的工艺来形成导电通孔132B、导电通孔136B和/或UBM 141。
后续地,通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除图案化的第二光刻胶162。在去除图案化的第二光刻胶162之后,诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)来去除晶种层152的暴露部分。晶种层的剩余部分和导电材料形成包括导线158和导电通孔170的金属化图案。
由于开口168的位置(参见图18),导电通孔170的位置同样可以不同于导电通孔164(参见图17)。例如,导电通孔170仅可以部分地与下面的导线158重叠,并且导电通孔170的部分可以比下面的导线158突出并延伸得更远。
后续地,如图20所示,在导线158和导电通孔170周围沉积介电层166。可以沉积介电层166以覆盖导线158和导电通孔170。在沉积之后,可以对介电层166施加CMP或其他平坦化工艺以暴露导电通孔170并且改进介电层166的顶面的平坦性。可以在导电通孔170的底面和直接位于介电层166的下面的层(例如,衬底150)之间设置介电层166的部分。后续地,可以在介电层166和导电通孔170上方形成额外的部件。例如,可以通过重复图18至图20中描述的工艺在介电层166上方形成位于介电层中的额外的金属化图案。
图21至图23示出根据一些其他实施例的形成金属化图案的各个中间步骤。在图21中,在导线158上方形成图案化的第二光刻胶162。图21的各个部件类似于图14中的部件,其中类似的参考标号表示使用类似的工艺(诸如,图9至图14中描述的那些工艺)形成的类似的元件。
如图21所示,在图案化的第二光刻胶162中形成开口174。开口174暴露导线158的顶面以及侧壁,并且可以通过导线158的材料以及晶种层152的材料来限定开口168的底面。与开口168(参见图18)不同,开口174完全延伸穿过图案化的第二光刻胶162以暴露晶种层152。例如,可以通过在光刻工艺期间控制曝光条件(例如,聚焦、能量等)来控制开口174的深度。
后续地,在图22中,在图案化的第二光刻胶162的开口174(参见图21)中且在导线158和晶种层152的暴露部分上形成导电材料(导电通孔176)。使用导电线158和晶种层152作为晶种层形成导电通孔176,而不为导电通孔176沉积单独的晶种层。这允许以相对低的制造成本来形成导电通孔176。可以通过诸如电镀或化学镀等的镀形成导电通孔176。导电通孔176可以包括例如铜、钛、钨、铝等的金属。然后,如图22所示,通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除图案化的第二光刻胶162。通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除图案化的第二光刻胶162。导电通孔176可以对应于图6至图8的导电通孔132B、导电通孔136B和/或UBM 141。例如,可以使用类似于本文所描述的导电通孔176的工艺来形成导电通孔132B、导电通孔136B和/或UBM 141。
后续地,通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除图案化的第二光刻胶162。在去除图案化的第二光刻胶162之后,诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)来去除晶种层152的暴露部分。晶种层的剩余部分和导电材料形成包括导线158和导电通孔176的金属化图案。
由于开口174(参见图21)的位置,导电通孔176的位置同样可以不同于导电通孔164(参见图17)或导电通孔170(参见图19)。例如,导电通孔176可以设置在导线158的边缘处,并且沿着导电通孔176的侧壁延伸的线也可以沿着导线158的侧壁延伸。
后续地,如图23所示,在导线158和导电通孔176周围沉积介电层166。可以沉积介电层166以覆盖导线158和导电通孔176。在沉积之后,可以对介电层166施加CMP或其他平坦化工艺以暴露导电通孔176并且改进介电层166的顶面的平坦性。后续地,可以在介电层166和导电通孔176上方形成额外的部件。例如,可以通过重复图21至图23中描述的工艺在介电层166上方形成位于介电层中的额外的金属化图案。
图24至32示出根据一些其他实施例的在介电层(例如,介电层134、138和/或142)中形成金属化图案(例如,金属化图案132、136、140和/或141)的各个中间步骤。参考图24,示出衬底150。衬底150可以是直接位于后续形成的金属化图案/介电层下面的任何层。例如,衬底150可以包括介电层中的金属化图案。可选地,衬底150可包括至集成电路管芯、密封剂和贯通孔的连接件。在又一其他实施例中,衬底150可以包括任何合适的材料。
仍如图24所示,在衬底150上方形成晶种层180。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。例如,晶种层180可以包括钛、铜、钼、钨、氮化钛、钛钨、它们的组合等。在一些实施例中,晶种层包括钛层180A和钛层180A上方的铜层180B。例如,可以使用PVD等形成晶种层180。
在图25中,在晶种层180上形成图案化的第一光刻胶182。通过旋涂,图案化的第一光刻胶182可以形成为毯式层光刻胶材料。在一些实施例中,图案化的第一光刻胶182可以包括三聚氰胺树脂、脲醛树脂、胍胺树脂、甘脲-甲醛树脂、琥珀酰胺-甲醛树脂、亚乙基脲-甲醛树脂和它们的组合的氨基化合物。在沉积光刻胶材料之后,例如,通过图案化的光掩模将光刻胶材料160暴露于UV光或另一辐射源。然后可以显影光刻胶材料160,并且根据使用的是正性抗蚀剂还是负性抗蚀剂来去除光刻胶材料的曝光或未曝光部分。在图25中示出所得的图案化的第一光刻胶182,其示出了具有延伸穿过其中的开口184的图案化的第一光刻胶182。图案化的第一光刻胶182的图案对应于金属化图案的导电通孔186(见图26)。开口184延伸穿过图案化的第一光刻胶182并暴露晶种层180。
后续地,在图26中,在图案化的第一光刻胶182的开口184(参见图25)中且在晶种层180的暴露部分上形成导电材料(导电通孔186)。可以通过诸如电镀或化学镀等的镀来形成导电通孔186。导电通孔186可以包括例如铜、钛、钨、铝等的金属。然后,如图26所示,通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除图案化的第一光刻胶182。导电通孔186可以对应于图6至图8的导电通孔132B、导电通孔136B和/或UBM 141。例如,可以使用类似于本文所描述的导电通孔186的工艺来形成导电通孔132B、导电通孔136B和/或UBM141。
如图27所示,一旦去除图案化的第一光刻胶182,在导电通孔186周围沉积介电层188。在一些实施例中,介电层188由聚合物形成,聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层188由诸如氮化硅的氮化物、诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。在介电层188包括光敏材料的实施例中,介电层188可以包括与图案化的第一光刻胶182(参见图25)不同类型的材料。例如,图案化的第一光刻胶182可比介电层188支持更高分辨率的光刻工艺。
可通过旋涂、层压、CVD等或它们的组合形成介电层188。如图27所示,可以首先形成介电层188以完全覆盖导电通孔186的顶面。后续地,如图28所示,可以对介电层188施加CMP或其他合适的平坦化工艺,以使介电层188的顶面齐平并暴露导电通孔186。
后续地,在图29至图31中,在介电层188和导电通孔186上方形成导线158。导线158可以电连接至下面的导电通孔186。形成导线158可以包括与图9至图12中所描述的类似的工艺,其中类似的参考标号表示类似的元件。在形成导线158之后,例如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层152的暴露部分。晶种层的剩余部分和导电材料形成包括导线158的金属化图案。
接下来,如图32所示,在导线158周围沉积介电层166。沉积介电层166以覆盖导线158。在沉积之后,可以对介电层166施加CMP或其他平坦化工艺以暴露导电158并且改进介电层166的顶面的平坦性。随后,可在介电层166和导线158上方形成额外的部件。例如,可以通过重复图24至图32中描述的工艺在介电层166上方形成位于介电层中的额外的金属化图案。
图33至图36示出根据一些实施例的在用于进一步形成第一封装件和用于将其他封装结构附接至第一封装件的工艺期间的中间步骤的截面图。可使用本文所描述的各种实施例工艺在前侧再分布结构144中形成金属化图案之后实施图33至36的工艺。
参考图33,在UBM 141上形成导电连接件148。导电连接件148可以是BGA连接件、焊球、金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件148可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中,通过通常使用的诸如蒸发、电镀、印刷焊料转移、球放置等方法首先形成焊料层来形成导电连接件148。一旦在结构上形成焊料层,可实施回流,以将材料成形为期望的凸块形状。在另一个实施例中,导电连接件148是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以没有焊料并且具有大致垂直的侧壁。在一些实施例中,在金属柱连接件148的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括通过电镀工艺形成的镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合。
如图33进一步示出的,还可以在UBM 141上形成表面安装器件(SMD)146。SMD 146可以包括诸如电容器、电阻器、电感器、它们的组合等的无源器件。可以通过再分布结构144中的金属化图案将SMD 146电连接至集成电路管芯114。
在图34中,实施载体衬底脱粘以使载体衬底100与背侧再分布结构(例如,介电层104)分离(脱粘)。根据一些实施例,脱粘包括将诸如激光或UV光的光投射到释放层102上,从而使得释放层102在光的热量下分解,并且可以去除载体衬底100。然后将该结构翻转并放置在胶带190上。
如图34进一步示出的,穿过介电层104形成开口以暴露金属化图案106的部分。例如,可以使用激光钻孔、蚀刻等形成开口。
在图35中,通过沿着例如相邻的区域600和602之间的划线区锯切来实施切割工艺。锯切从第二封装件区域602分割第一封装件区域600。
图35示出所得的分割的封装件200,其可以来自第一封装件区域600或第二封装件区域602的一个。封装件200还可以称为集成扇出(InFO)封装件200。
图36示出包括封装件200(可以称为第一封装件200)、第二封装件300和衬底400的封装结构500。第二封装件300包括衬底302和连接至衬底302的一个或多个堆叠管芯308(308A和308B)。衬底302可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中,还可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、它们的组合等的化合物材料。额外地,衬底302可以是绝缘体上硅(SOI)衬底。通常,SOI衬底包括诸如外延的硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。在一个可选实施例中,衬底302是基于诸如玻璃纤维增强的树脂芯的绝缘芯。一种示例性芯材料是诸如FR4的玻璃纤维树脂。芯材料的可选材料包括双马来酰亚胺-三嗪(BT)树脂,或者可选地,其他印刷电路板(PCB)材料或膜。诸如味之素构建膜(ABF)或其他层压件的构建膜可用于衬底302。
衬底302可以包括有源和无源器件(在图28中未示出)。本领域中的普通技术人员将意识到,诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于产生用于半导体封装件300的设计的结构和功能需求。可以使用任何合适的方法来形成器件。
衬底302还可以包括金属化层(未示出)和贯通孔306。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由介电材料(例如,低k介电材料)和具有互连导电材料层的通孔的导电材料(例如,铜)的交替层形成,并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)来形成。在一些实施例中,衬底302大致没有有源和无源器件。
衬底302可以具有位于衬底302的第一侧上的接合焊盘303以连接至堆叠管芯308,以及位于衬底302的第二侧上的接合焊盘304以连接至导电连接件314,衬底302的第二侧与衬底302的第一侧相对。在一些实施例中,通过在衬底302的第一侧和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成接合焊盘303和304。凹槽形成为允许接合焊盘303和304嵌入到介电层中。在其他实施例中,省略凹槽,因为接合焊盘303和304可以形成在介电层上。在一些实施例中,接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层层(未示出)。可以在薄晶种层上方沉积接合焊盘303和304的导电材料。通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中,接合焊盘303和304的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中,接合焊盘303和304是包括诸如钛层、铜层和镍层的三层导电材料的UBM。然而,本领域的普通技术人员将意识到,存在诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置的材料和层的许多合适的布置,这些都适用于UBM 303和304的形成。可用于UBM 303和304的任何合适的材料或材料层旨在完全包括在本申请的范围内。在一些实施例中,贯通孔306延伸穿过衬底302并且将至少一个接合焊盘303连接至至少一个接合焊盘304。
在示出的实施例中,堆叠管芯308通过接合线310连接至衬底302,尽管可以使用诸如导电凸块的其他连接。在实施例中,堆叠管芯308是堆叠的存储器管芯。例如,堆叠的存储器管芯可以包括诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4、非易失性存储器或类似的存储器模块的低功率(LP)双数据速率(DDR)存储器模块等。。
在一些实施例中,由模制材料312密封堆叠管芯308和接合线310。例如,可以使用压缩模制将模制材料312模制在堆叠管芯308和接合线310上。在一些实施例中,模制材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化步骤以固化模制材料312,其中固化可以是热固化、UV固化等或它们的组合。
在一些实施例中,将堆叠管芯310和接合线310埋入模制材料312中,并且在固化模制材料312之后,实施诸如研磨的平坦化步骤以去除模制材料312的多余的部分并且为第二封装件300提供大致平坦的表面。
在形成第二封装件300之后,通过导电连接件314、接合焊盘304和金属化图案106的方式将封装件300接合至第一封装件200。在一些实施例中,堆叠存储器管芯308可通过接合线310、接合焊盘303和304、贯通孔306、导电连接件314和贯通孔112连接至集成电路管芯114。
导电连接件314类似于上文中描述的导电连接件148,并且本文中不重复描述,尽管导电连接件314和148不需要相同。在一些实施例中,在接合导电连接件314之前,利用诸如免洗焊剂的焊剂(未示出)涂覆导电连接件314。导电连接件314可以浸入焊剂中,或焊剂可以喷射到导电连接件314上。在另一实施例中,可以将焊剂施加到金属化图案106的表面。
在一些实施例中,在用第二封装件300附接至第一封装件200之后剩余的环氧树脂焊剂的环氧树脂部分的至少一些回流导电连接件314之前,导电连接件314可以具有形成在其上的环氧树脂焊剂(未示出)。剩余的环氧树脂部分可以用作底部填充物以减少应力并保护由于回流导电连接件314而产生的接头。在一些实施例中,底部填充物(未示出)可以形成在第二封装件300和第一封装件200之间并且围绕导电连接件314。底部填充物可以在附接第二封装件300之后通过毛细管流动工艺形成,或可以在附接第二封装件300之前通过合适的沉积方法形成。
第二封装件300与第一封装件200之间的接合可以是焊料接合或直接金属至金属(诸如铜至铜或锡至锡)接合。在实施例中,第二封装件300通过回流工艺接合至第一封装件200。在该回流工艺期间,导电连接件314与接合焊盘304和金属化图案106接触,以将第二封装件300物理地且电连接至第一封装件200。在接合工艺之后,可以在金属化图案106和导电连接件314的界面处并且还在导电连接件314和接合焊盘304之间的界面处(未示出)形成IMC(未示出)。
半导体封装件500包括安装到衬底400的封装件200和300。衬底400可以称为封装衬底400。使用导电连接件148将封装件200安装至封装衬底400。
封装衬底400可以由诸如硅、锗、金刚石等的半导体材料制成。可选地,还可以使用化合物材料,诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、它们的组合等。额外地,封装衬底400可以是SOI衬底。通常,SOI衬底包括诸如外延的硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中,封装衬底400是基于诸如玻璃纤维增强的树脂芯的绝缘芯。一种示例性芯材料是诸如FR4的玻璃纤维树脂。用于芯材料的可选材料包括双马来酰亚胺-三嗪BT树脂,或者可选地,其他PCB材料或膜。诸如味之素构建膜(ABF)或其他层压件的构建膜可用于封装衬底400。
封装衬底400可以包括有源和无源器件(在图36中未示出)。本领域中的普通技术人员将意识到,诸如晶体管、电容器、电阻器、它们的组合等的多种器件可以用于产生用于半导体封装件500的设计的结构和功能需求。可以使用任何合适的方法来形成器件。
封装衬底400还可以包括位于金属化层和通孔(未示出)以及位于通孔和金属化层上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由介电材料(例如,低k介电材料)和具有互连导电材料层的通孔的导电材料(例如,铜)的交替层形成,并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)来形成。在一些实施例中,封装衬底400大致没有有源和无源器件。
在一些实施例中,可以回流导电连接件148以将封装件200附接至接合焊盘402。导电连接件148将衬底400(包括衬底400中的金属化层)电和/或物理连接至第一封装件200。
在用封装件200附接至衬底400之后剩余的环氧树脂焊剂的环氧树脂部分的至少一些回流导电连接件148之前,导电连接件148可以具有形成在其上的环氧树脂焊剂(未示出)。剩余的环氧树脂部分可以用作底部填充物以减少应力并保护由于回流导电连接件148而产生的接头。在一些实施例中,底部填充物(未示出)可以形成在第一封装件200和衬底400之间并且围绕导电连接件148。底部填充物可以在附接封装件200之后通过毛细管流动工艺形成,或者可以在附接封装件200之前通过合适的沉积方法形成。
在图1至图36的实施例中,示出后RDL形成工艺。例如,在第一封装件200中设置集成电路管芯114之后,在集成电路管芯114上方形成再分布结构144。在其他实施例中,在形成RDL(有时称为先RDL工艺)之后,集成电路管芯114可接合至封装部件。例如,图37至图40示出根据一些可选实施例的制造半导体封装件的各个中间阶段的截面图。
在图37中,在附接集成电路管芯114之前,在载体衬底100上方形成再分布结构144。用于形成再分布结构144的工艺可以大致类似于图1至图36中描述的工艺,其中类似的参考标号表示类似的元件。
在形成再分布结构144之后,如图38所示,在再分布结构144上形成导电柱700。作为形成导电柱700的实例,在再分布结构144上方形成晶种层(未示出)。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于导电柱700。图案化形成了穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括例如铜、钛、钨、铝等金属。然后,去除光刻胶以及晶种层的其上未形成导电材料的部分。通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成导电柱700。
在图39中,使用诸如翻转芯片接合的合适的接合工艺将集成电路管芯114接合至再分布结构144。可以使用导电连接件702将集成电路管芯114接合至导电柱700。导电连接器702可以包括微凸块(μbump)、C4凸块、BGA球等。集成电路管芯114可以包括与上文中关于图4的集成电路管芯114描述的类似的部件,其中类似的参考标号表示类似的元件。
后续地,在图40中,在各个组件上形成密封剂704。密封剂704可以是模塑料、环氧树脂等,并且可以通过压缩模制、传递模制等来施加。在集成电路114周围且在集成电路管芯114和再分布结构144之间分配密封剂704。在固化之后,密封剂704可以可选地经历研磨工艺以暴露出集成电路管芯114。在一些实施例中,可以省略研磨。在形成密封剂704之后,可以从载体100脱黏各个部件,并且可以沿着划线(例如,设置在相邻的封装区域600和602之间)施加切割工艺。可在再分布结构144的相对侧上(例如,在金属化图案132上)形成导电连接件(未示出)。导电连接件可用于将分割的封装件接合至诸如其他集成电路管芯、器件封装件、封装衬底、内插器、主板、它们的组合等的其他封装部件。
因此,如上文中所描述的,各个实施例提供了形成半导体封装件的再分布结构中的诸如导线和/或通孔的导电部件的方法。实施例工艺可以使用光刻胶限定导电通孔的图案来形成导电通孔。因为在形成导电通孔之后后续去除光刻胶,用于光刻胶的材料的选择不限于适合包括在成品封装件中的介电材料。例如,可以选择光刻胶的材料以支持相对高分辨率的光刻,这允许形成细间距的导电通孔。实施例导电通孔可具有约1μm或更小的宽度,但还可以形成其他尺寸的通孔。在去除光刻胶之后,在通孔周围形成介电层,并且选择介电层的材料以向设置在其中的再分布图案提供结构支撑和绝缘。尽管介电层还可以包括光敏材料,但是介电层可以不支持与用于限定导电通孔的光刻胶一样高的分辨率的图案化。因此,各个实施例可以提供一个或多个以下非限制性优势:通过使用较高分辨率的光刻胶来限定导电通孔的形状的较小的导电通孔;降低的制造成本;减少的聚合物层分辨率窗口问题;再分布层中的改进的平坦性;增加的金属化图案的密度等。
根据实施例,一种方法包括在晶种层上方形成图案化的第一光刻胶。图案化的第一光刻胶中的第一开口暴露晶种层。该方法还包括在晶种层上且在第一开口中镀第一导电材料,去除图案化的第一光刻胶,并且在去除图案化的第一光刻胶之后,在第一导电材料的侧壁上方且沿着第一导电材料的侧壁形成图案化的第二光刻胶。图案化的第二光刻胶中的第二开口暴露第一导电材料的部分。该方法还包括在第二开口中且在第一导电材料上镀第二导电材料,去除图案化的第二光刻胶,并且在去除图案化的第二光刻胶之后,去除晶种层的暴露部分。该方法还包括在第一导电材料和第二导电材料周围沉积介电层。
在上述方法中,还包括平坦化所述介电层,使得所述介电层的顶面与所述第二导电材料的顶面齐平。
在上述方法中,其中,所述图案化的第二光刻胶的光敏材料设置在所述第二导电材料的底面和所述晶种层之间。
在上述方法中,其中,所述第二开口还暴露所述晶种层的部分。
在上述方法中,还包括在集成电路管芯上方且在密封所述集成电路管芯的密封剂上沉积所述晶种层。
在上述方法中,还包括:在载体衬底上方沉积所述晶种层;以及在沉积所述晶种层之后,使用翻转芯片接合工艺接合位于所述介电层上方的集成电路管芯。
在上述方法中,还包括:在载体衬底上方沉积所述晶种层;以及在沉积所述晶种层之后,使用翻转芯片接合工艺接合位于所述介电层上方的集成电路管芯,还包括密封所述集成电路管芯,其中,密封所述集成电路管芯包括在所述集成电路管芯的底面和所述介电层之间分配密封剂。
在上述方法中,其中,所述介电层包括光敏聚合物,并且其中,所述图案化的第二光刻胶比所述光敏聚合物支持更高分辨率的光刻工艺。
根据另一实施例,该方法包括:将集成电路管芯密封在密封剂中;在密封剂和集成电路管芯上方沉积第一光刻胶;在第一光刻胶中图案化第一开口以暴露第一导电材料,并且在第一开口中镀导电通孔。导电通孔电连接至集成电路管芯。该方法还包括去除第一光刻胶并在导电通孔周围沉积第一聚合物层。第一聚合物层和第一光刻胶包括不同的材料。第一光刻胶比第一聚合物层支持更高分辨率的光刻。该方法还包括平坦化第一聚合物层,从而使得第一聚合物层的顶面和导电通孔大致齐平。
在上述方法中,其中,所述第一导电材料是导线,其中,沉积所述第一聚合物层还包括沿着所述导线的侧壁沉积所述第一聚合物层。
在上述方法中,其中,所述第一导电材料是导线,其中,沉积所述第一聚合物层还包括沿着所述导线的侧壁沉积所述第一聚合物层,还包括:在所述集成电路管芯和所述密封剂上方沉积第二光刻胶;在所述第二光刻胶中图案化第二开口;在所述第二开口中镀所述导线,其中,所述导线电连接至所述集成电路管芯;以及去除所述第二光刻胶,其中,在去除所述第二光刻胶之后沉积所述第一光刻胶。
在上述方法中,其中,沉积所述第一聚合物层包括在所述导电通孔的底面下方沉积所述第一聚合物层的部分。
在上述方法中,其中,所述第一导电材料是第一晶种层,并且其中,所述方法还包括:在平坦化所述第一聚合物层之后,在所述第一聚合物层和所述导电通孔上方沉积第二晶种层;在所述第二晶种层上方沉积第二光刻胶;在所述第二光刻胶中图案化暴露所述第二晶种层的第二开口;在所述第二开口中镀导线并且所述导线电连接至所述导电通孔;以及在所述导线周围沉积第二聚合物层。
在上述方法中,其中,所述第一导电材料是第一晶种层,并且其中,所述方法还包括:在平坦化所述第一聚合物层之后,在所述第一聚合物层和所述导电通孔上方沉积第二晶种层;在所述第二晶种层上方沉积第二光刻胶;在所述第二光刻胶中图案化暴露所述第二晶种层的第二开口;在所述第二开口中镀导线并且所述导线电连接至所述导电通孔;以及在所述导线周围沉积第二聚合物层,还包括平坦化所述第二聚合物层,使得所述第二聚合物层和所述导线的顶面齐平。
根据又一实施例,半导体封装件包括集成电路管芯、设置在集成电路管芯周围的密封剂,延伸穿过密封剂的贯通孔,以及位于集成电路管芯和密封剂上方的再分布结构。再分布结构的金属化图案包括设置在介电层中并电连接至集成电路管芯的导线。介电层接触密封剂的顶面。金属化图案进一步包括位于导线上方并电连接至导线的导电通孔。导电通孔的顶面与介电层的顶面大致齐平。
在上述半导体封装件中,其中,所述介电层的部分设置在所述导电通孔的底面下方。
在上述半导体封装件中,其中,沿着所述导线的侧壁延伸的线还沿着所述导电通孔的侧壁延伸。
在上述半导体封装件中,其中,所述介电层与所述导线的底面齐平,并且其中,没有其他导电部件设置在所述介电层和沿着与所述介电层的所述顶面垂直的线的所述密封剂之间。
在上述半导体封装件中,其中,所述再分布结构的额外的金属化图案包括与所述导电通孔的所述顶面形成界面的额外的导线。
在上述半导体封装件中,其中,所述导线包括位于导电材料下方的晶种层,并且其中,所述晶种层的顶面共面。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (20)
1.一种形成半导体封装件的方法,包括:
提供衬底;
在所述衬底上方形成金属化图案;
通过粘合剂将集成电路管芯的第一侧粘附至所述金属化图案,其中,所述粘合剂沿着所述所述金属化图案的侧壁延伸;
在所述集成电路管芯的第二侧的上方且在密封所述集成电路管芯的密封剂上沉积晶种层,其中,所述第一侧和所述第二侧相对;
在所述晶种层上方形成图案化的第一光刻胶,其中,所述图案化的第一光刻胶中的第一开口暴露所述晶种层;
在所述第一开口中且在所述晶种层上镀第一导电材料;
去除所述图案化的第一光刻胶;
在去除所述图案化的第一光刻胶之后,在所述第一导电材料的侧壁上方且沿着所述第一导电材料的所述侧壁形成图案化的第二光刻胶,其中,所述图案化的第二光刻胶的第二开口暴露所述第一导电材料的顶面的部分、所述第一导电材料的侧壁和所述晶种层的部分;
在所述第二开口中且在所述第一导电材料的侧壁和顶面上以及所述晶种层上镀第二导电材料;
去除所述图案化的第二光刻胶;
在去除所述图案化的第二光刻胶之后,去除所述晶种层的暴露部分;以及
在所述第一导电材料和所述第二导电材料周围沉积介电层,
其中,所述第二导电材料与所述第一导电材料的侧壁以及所述晶种层的部分直接接触。
2.根据权利要求1所述的方法,还包括平坦化所述介电层,使得所述介电层的顶面与所述第二导电材料的顶面齐平。
3.根据权利要求1所述的方法,其中,所述图案化的第二光刻胶的光敏材料设置在所述晶种层上。
4.根据权利要求1所述的方法,其中,去除所述晶种层的所述暴露部分使得所述晶种层的一侧端部与所述第二导电材料的一侧端部对齐。
5.根据权利要求1所述的方法,其中,所述介电层包括氧化物。
6.根据权利要求1所述的方法,还包括:
在所述介电层和所述第二导电材料上方形成额外的导电连接件。
7.根据权利要求6所述的方法,还包括密封所述集成电路管芯,其中,密封所述集成电路管芯包括在所述集成电路管芯的底面和所述介电层之间分配密封剂。
8.根据权利要求1所述的方法,其中,所述介电层包括光敏聚合物,并且其中,所述图案化的第二光刻胶比所述光敏聚合物支持更高分辨率的光刻工艺。
9.一种形成半导体封装件的方法,包括:
提供衬底;
在所述衬底上方形成金属化图案;
通过粘合剂将集成电路管芯的第一侧粘附至所述金属化图案,其中,所述粘合剂沿着所述所述金属化图案的侧壁延伸;
将所述集成电路管芯密封在密封剂中;
在所述密封剂和所述集成电路管芯的第二侧的上方沉积第一晶种层,其中,所述第一侧和所述第二侧相对;
在所述第一晶种层上沉积第一光刻胶;
在所述第一光刻胶中图案化第一开口以暴露第一导电材料和所述第一晶种层;
在所述第一开口中镀导电通孔,其中,所述导电通孔位于所述第一导电材料的侧壁和顶面上以及所述第一晶种层上,并且所述导电通孔电连接至所述集成电路管芯;
去除所述第一光刻胶;
在所述导电通孔周围沉积第一聚合物层,其中,所述第一聚合物层和所述第一光刻胶包括不同的材料;以及
平坦化所述第一聚合物层,使得所述第一聚合物层和所述导电通孔的顶面齐平,
其中,所述导电通孔与所述第一导电材料的侧壁和所述第一晶种层的顶面直接接触。
10.根据权利要求9所述的方法,其中,所述第一导电材料是导线,其中,沉积所述第一聚合物层还包括沿着所述导线的一侧侧壁沉积所述第一聚合物层。
11.根据权利要求10所述的方法,还包括:
在所述集成电路管芯和所述密封剂上方沉积第二光刻胶;
在所述第二光刻胶中图案化第二开口;
在所述第二开口中镀所述导线,其中,所述导线电连接至所述集成电路管芯;以及
去除所述第二光刻胶,其中,在去除所述第二光刻胶之后沉积所述第一光刻胶。
12.根据权利要求9所述的方法,其中,沉积所述第一聚合物层包括在所述导电通孔的一侧侧壁沉积所述第一聚合物层的部分。
13.根据权利要求9所述的方法,其中,所述方法还包括:
在平坦化所述第一聚合物层之后,在所述第一聚合物层和所述导电通孔上方沉积第二晶种层;
在所述第二晶种层上方沉积第二光刻胶;
在所述第二光刻胶中图案化暴露所述第二晶种层的第二开口;
在所述第二开口中镀导线并且所述导线电连接至所述导电通孔;以及
在所述导线周围沉积第二聚合物层。
14.根据权利要求13所述的方法,还包括平坦化所述第二聚合物层,使得所述第二聚合物层和所述导线的顶面齐平。
15.一种半导体封装件,包括:
集成电路管芯;
背侧再分布结构,位于所述集成电路管芯的第一侧上;
粘合层,位于所述集成电路管芯与所述背侧再分布结构之间,其中,所述粘合层接触所述背侧再分布结构中的金属化图案的表面和侧壁;
密封剂,设置在所述集成电路管芯周围;
贯通孔,延伸穿过所述密封剂;以及
前侧再分布结构,位于所述集成电路管芯的第二侧和所述密封剂上方,其中,所述第一侧和所述第二侧相对,所述前侧再分布结构的金属化图案包括:
晶种层,设置在介电层中并且电连接至所述集成电路管芯,其中,所述介电层接触所述密封剂的顶面;
导线,设置在所述晶种层的顶面上;以及
导电通孔,位于所述导线上方且电连接至所述导线,其中,所述导电通孔的顶面与所述介电层的顶面齐平,并且所述导电通孔与所述导线的第一侧壁和顶面以及所述晶种层的顶面直接接触,所述导电通孔的一侧末端与所述晶种层的第一侧末端对齐。
16.根据权利要求15所述的半导体封装件,其中,所述介电层与所述晶种层的底面齐平。
17.根据权利要求15所述的半导体封装件,其中,所述导线的第二侧壁与所述晶种层的第二侧末端对齐,其中,所述导线的第一侧壁与所述导线的第二侧壁相对,所述晶种层的第一侧末端与所述晶种层的第二侧末端相对。
18.根据权利要求15所述的半导体封装件,其中,所述介电层的部分设置在所述导电通孔的顶面与所述导线的顶面之间。
19.根据权利要求15所述的半导体封装件,其中,所述前侧再分布结构的额外的金属化图案包括与所述导电通孔的所述顶面形成界面的额外的导线。
20.根据权利要求15所述的半导体封装件,其中,所述介电层包括氧化物。
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CN107689333A (zh) | 2018-02-13 |
TW201816897A (zh) | 2018-05-01 |
US10340206B2 (en) | 2019-07-02 |
US20190096790A1 (en) | 2019-03-28 |
US11417604B2 (en) | 2022-08-16 |
US20220352086A1 (en) | 2022-11-03 |
US20180040546A1 (en) | 2018-02-08 |
TWI731045B (zh) | 2021-06-21 |
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