TW201816897A - 半導體封裝中的密集型重佈線層以及其形成方法 - Google Patents

半導體封裝中的密集型重佈線層以及其形成方法 Download PDF

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TW201816897A
TW201816897A TW106107933A TW106107933A TW201816897A TW 201816897 A TW201816897 A TW 201816897A TW 106107933 A TW106107933 A TW 106107933A TW 106107933 A TW106107933 A TW 106107933A TW 201816897 A TW201816897 A TW 201816897A
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photoresist
layer
patterned
dielectric layer
conductive
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TW106107933A
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TWI731045B (zh
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余振華
郭宏瑞
蔡惠榕
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台灣積體電路製造股份有限公司
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明實施例提供一種半導體封裝中的密集型重佈線層的形成方法，其包含在晶種層上方形成經圖案化第一光阻。經圖案化第一光阻中的第一開口暴露晶種層。形成方法更包含：在晶種層上的第一開口中鍍覆第一導電材料；移除經圖案化第一光阻；以及在移除經圖案化第一光阻之後在第一導電材料上方形成經圖案化第二光阻。經圖案化第二光阻中的第二開口暴露第一導電材料的一部分。形成方法更包含：在第一導電材料上的第二開口中鍍覆第二導電材料；移除經圖案化第二光阻；以及在移除經圖案化第二光阻之後圍繞第一導電材料以及第二導電材料沈積介電層。

Description

半導體封裝中的密集型重佈線層以及其形成方法
本發明實施例是有關於一種半導體封裝中的密集型重佈線層以及其形成方法。
半導體行業因多種電子組件（例如，電晶體、二極體、電阻器、電容器等）的整合密度的改良而快速發展。主要地，整合密度的改良源自於最小特徵大小的反覆減小，其允許較多組件整合至一個給定區域內。隨著對於縮小電子元件的需求增長，對於較小且較創造性的半導體晶粒的封裝技術的需要已出現。此類封裝系統的實例為疊層封裝（Package-on-Package；PoP）技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝的頂部上，以提供高整合度以及高組件密度。PoP技術大致上實現具有增強的功能性以及於印刷電路板（printed circuit board；PCB）上具有較小的佔據面積之半導體元件的生產。
本發明實施例提供一種半導體封裝中的密集型重佈線層的形成方法，其包括以下步驟。在晶種層上方形成經圖案化第一光阻，其中經圖案化第一光阻中的第一開口暴露晶種層。在晶種層上的第一開口中鍍覆第一導電材料。移除經圖案化第一光阻。在移除經圖案化第一光阻之後，在第一導電材料的側壁上方且沿側壁形成經圖案化第二光阻，其中經圖案化第二光阻中的第二開口暴露第一導電材料的一部分。在第一導電材料上的第二開口中鍍覆第二導電材料。移除經圖案化第二光阻。在移除經圖案化第二光阻之後，移除晶種層的經暴露部分。圍繞第一導電材料以及第二導電材料沈積介電層。
以下揭露內容提供用於實施本發明實施例的不同特徵的許多不同實施方式或實例。下文描述組件以及配置的特定實例以簡化本發明實施例。當然，此等組件以及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含直接接觸地形成第一特徵以及第二特徵的實施方式，且亦可包含額外特徵可形成於第一特徵與第二特徵之間，使得第一特徵與第二特徵可不直接接觸的實施方式。另外，本發明實施例可在各種實例中重複參考數字及/或字母。此重複是出於簡化以及清楚的目的，且本身並不指示所論述的各種實施方式及/或組態之間的關係。
另外，為了易於描述，可在本文中使用諸如「在……下」、「在……下方」、「下部」、「在……上方」、「上部」以及類似者的空間相對術語以描述如諸圖中所說明的一個元件或特徵與另一元件或特徵的關係。除諸圖中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。元件可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞同樣可相應地進行解釋。
各種實施方式提供在半導體封裝的重佈線層（redistribution layer；RDL）中形成導電特徵（諸如，導電線及/或通孔）的方法。儘管關於特定上下文（例如，具有扇出型RDL的整合扇出型（integrated fan-out；InFO）封裝）描述各種實施方式，但各種導電特徵的製造方法可應用於其他封裝元件中出現於任一區域內的導電特徵。各種實施方式可提供至少一種以下非限制性優點：藉由使用較高解析度光阻以定義較小導通孔之導通孔的形狀、降低製造成本、減小聚合物層解析度窗口問題、重佈線層中的改良的平坦度以及類似者。
圖1至圖36為根據一些本發明實施例於形成第一封裝結構的過程之中間步驟的剖面示意圖。請參考圖1，提供載體基板100以及形成於載體基板100上的釋放層102。在圖1中，分別示出用於形成第一封裝以及第二封裝的第一封裝區600以及第二封裝區602。
載體基板100可為玻璃載體基板、陶瓷載體基板或類似者。載體基板100可為晶圓（wafer），使得多個封裝可同時形成於載體基板100上。釋放層102可由聚合物類材料形成，可將其連同載體基板100一起自於後續步驟中形成的上覆結構移除。在一些實施方式中，釋放層102為在加熱時損失其黏著性質的環氧樹脂類熱釋放材料（epoxy-based thermal-release material），諸如，光-熱轉換（light-to-heat-conversion；LTHC）釋放塗層。在其他實施方式中，釋放層102可為在暴露於紫外線（ultra-violet；UV）光時損失其黏著性質的UV膠。釋放層102可例如以液體形態分配（dispensed）並固化，可為疊層至載體基板100上的疊層膜或為類似者。釋放層102的頂部表面可經水平化且可具有高度共面性（high degree of coplanarity）。
在圖2中，形成介電層104以及金屬化圖案106。如圖2所示，介電層104形成於釋放層102上。介電層104的底部表面可與釋放層102的頂部表面接觸。在一些實施方式中，介電層104由諸如聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺（polyimide；PI）、苯環丁烷（benzocyclobutene；BCB）或類似者的聚合物形成。在其他實施方式中，介電層104由氮化物（例如氮化矽）或氧化物（例如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽酸鹽玻璃（borosilicate glass；BSG）、摻硼磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG）或類似者）而形成。介電層104可透過任何可接受的沈積製程來形成，舉例來說，旋轉塗佈、化學氣相沈積（chemical vapor deposition；CVD）、疊層（laminating）、類似者或其組合。
金屬化圖案106形成於介電層104上。作為形成金屬化圖案106的實例，晶種層（未繪示）形成於介電層104上方。在一些實施方式中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成之多個子層的複合層。舉例而言，晶種層可包括鈦、銅、鉬、鎢、氮化鈦、鎢化鈦、其組合或類似者。在一些實施方式中，晶種層包括鈦層以及位在鈦層上方的銅層。可例如藉由使用PVD或類似的製程來形成晶種層。接著，在晶種層上形成並圖案化光阻。光阻可藉由旋轉塗佈或類似的製程形成且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案106。圖案化光阻形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中且形成於晶種層之經暴露的部分上。導電材料可藉由鍍覆而形成，舉例來說，電鍍、化學鍍或類似的製程。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。接著，移除於其上方未形成有導電材料的部分光阻以及晶種層。可藉由可接受的灰化（ashing）或剝離（stripping）製程來移除光阻，諸如，使用氧電漿或類似者。一旦光阻被移除，可透過使用可接受的蝕刻製程（如濕式或乾式蝕刻）來移除晶種層之經暴露的部分。晶種層以及導電材料的剩餘部分形成金屬化圖案106。
介電層104以及金屬化圖案106可被稱作背側重佈線結構（back-side redistribution structure）110。如上說明，背側重佈線結構110包含一個介電層104以及一個金屬化圖案106。在其他實施方式中，背側重佈線結構110可包含任何數目個介電層、金屬化圖案以及通孔。
舉例而言，在一個實施方式中，額外介電層（未繪示）視情況可選擇性地形成於金屬化圖案106以及介電層104上。在一些實施方式中，額外介電層由聚合物形成，聚合物可為感光性材料，諸如，PBO、聚醯亞胺、BCB或類似者，且經圖案化後可作為微影罩幕來使用。在其他實施方式中，介電層可由氮化物（諸如氮化矽）、氧化物（諸如氧化矽、PSG、BSG、BPSG）或類似者而形成。可透過旋轉塗佈、疊層、CVD、類似者或其組合來形成額外介電層。接著，圖案化額外介電層以形成開口來暴露金屬化圖案106的一部分。圖案化可藉由可接受的製程，諸如，在介電層為感光性材料時將介電層暴露於光或示例如通過使用非等向性蝕刻進行蝕刻。隨後，已形成的導電特徵可經由形成於額外介電層的開口中的導通孔電性連接至金屬化圖案106。
可藉由重複執行形成金屬化圖案106以及視情況選用的額外介電層（未繪示）的製程而在背側重佈線結構110中形成一或多個額外金屬化圖案以及介電層。在形成金屬化圖案期間，可藉由在下方之介電層的開口中形成金屬化圖案的晶種層以及導電材料而形成通孔。或者，可使用如下文關於圖9至圖32所描述的實施方式之通孔形成製程來形成通孔。通孔可因此互連且電耦接各種金屬化圖案。
此外，在圖3中，形成穿孔112。作為形成穿孔112的實例，晶種層形成於背側重佈線結構110（例如，介電層104以及金屬化圖案106）上方。在一些實施方式中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成的多個子層的複合層。舉例而言，晶種層可包括鈦、銅、鉬、鎢、氮化鈦、鎢化鈦、其組合或類似者。在一些實施方式中，晶種層包括鈦層以及位在鈦層上方的銅層。可例如藉由使用PVD或類似的製程來形成晶種層。在晶種層上形成並圖案化光阻。光阻可藉由旋轉塗佈或類似者形成且可暴露於光以用於圖案化。光阻的圖案對應於穿孔112。圖案化光阻形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中且形成於晶種層的經暴露的部分上。導電材料可藉由鍍覆而形成，諸如電鍍、化學鍍或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。移除未於其上方形成有導電材料的部分光阻及晶種層。可藉由可接受的灰化或剝離製程來移除光阻，諸如使用氧電漿或類似者。一旦光阻被移除，可通過使用可接受的蝕刻製程（如濕式或乾式蝕刻）移除晶種層之經暴露的部分。晶種層以及導電材料的剩餘部分形成穿孔112。在其他實施方式中，晶種層被省略，而將金屬化圖案106做為用於形成穿孔112的晶種層。
在圖4中，積體電路晶粒114藉由黏著劑116黏附於背側重佈線結構110。舉例而言，黏著劑116可黏附於金屬化圖案106的頂部表面，且黏著劑116可沿金屬化圖案106的側壁進一步延伸。在其他實施方式中，諸如，當額外介電層（未繪示）視情況而選擇性地形成於金屬化圖案106上方時，黏著劑116可黏附於視情況選用的額外介電層的頂部表面。
如圖4所示，兩個積體電路晶粒114黏附於第一封裝區600以及第二封裝區602中的每一者中，且在其他實施方式中，亦可將較多或較少之積體電路晶粒114的數量黏附於上述每一區中。舉例而言，在一個實施方式中，僅一個積體電路晶粒114可黏附於每一區中。積體電路晶粒114可為邏輯晶粒（例如，中央處理單元、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory；DRAM）晶粒、靜態隨機存取記憶體（static random access memory；SRAM）晶粒等）、功率管理晶粒（例如，功率管理積體電路（power management integrated circuit；PMIC）晶粒）、射頻（radio frequency；RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system；MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing；DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end；AFE）晶粒）、類似者或其組合。又，在一些實施方式中，積體電路晶粒114可為不同大小（例如，不同高度及/或表面積），且在其他實施方式中，積體電路晶粒114可為相同大小（例如，相同高度及/或表面積）。
在積體電路晶粒114黏附至介電層108之前，可根據可適用的製造製程來處理積體電路晶粒114，以在積體電路晶粒114中形成積體電路。舉例而言，每一個積體電路晶粒114各自包含半導體基板118，諸如經摻雜或未經摻雜的矽或是絕緣層上半導體（semiconductor-on-insulator；SOI）基板的主動層。半導體基板可包含其他半導體材料，諸如鍺（germanium）、化合物半導體（包含碳化矽（silicon carbide）、砷化鎵（gallium arsenic）、磷化鎵（gallium phosphide）、磷化銦（indium phosphide）、砷化銦（indium arsenide）及/或銻化銦（indium antimonide））、合金半導體（包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP）或其組合。亦可使用其他基板，例如多層基板或梯度基板（gradient substrate）。諸如電晶體、二極體、電容器、電阻器等的元件可形成於半導體基板118中及/或形成於半導體基板118上，並例如可透過與形成於半導體基板118上的一或多個介電層中的金屬化圖案之互連結構120互連，以形成積體電路。
積體電路晶粒114更包括接墊122（諸如，鋁墊），並以其進行外部連接。接墊122配置於被稱作積體電路晶粒114的各別之主動側上。鈍化膜124位在積體電路晶粒114上且位在部分接墊122上。開口穿過鈍化膜124直至接墊122。晶粒連接件126例如是導電柱（例如，包括諸如銅的金屬）位在穿過鈍化膜124的開口中，並機械性地且電性地耦接至各別之接墊122。可透過例如鍍覆或類似之製程來形成晶粒連接件126。晶粒連接件126電耦接積體電路晶粒114的各別之積體電路。
介電材料128在積體電路晶粒114的主動側上，例如在鈍化膜124以及晶粒連接件126上。介電材料128側向地密封晶粒連接件126，且介電材料128與各別積體電路晶粒114側向地共端。介電材料128可為聚合物（例如PBO、聚醯亞胺、BCB或類似者）、氮化物（例如氮化矽或類似者）、氧化物（例如氧化矽、PSG、BSG、BPSG或類似者）、類似者或其組合，且可例如藉由旋轉塗佈、疊層、CVD或類似者形成。
黏著劑116位在積體電路晶粒114的背側上，且將積體電路晶粒114黏附至背側重佈線結構110，例如金屬化圖案106。黏著劑116可為任何適合的黏著劑、環氧樹脂、晶粒貼合膜（die attach film；DAF）或類似者。黏著劑116可塗覆於積體電路晶粒114的背側（諸如，塗覆於各別半導體晶圓的背側）或可塗覆於載體基板100的表面上方。藉由執行鋸割或切割製程可使積體電路晶粒114單體化，且藉由使用取放工具（pick-and-place tool）可透過黏著劑116將積體電路晶粒114黏附至介電層104。
在圖5中，密封體130形成於各種組件上。密封體130可為模製化合物（molding compound）、環氧樹脂或類似者，且可藉由壓縮模製（compression molding）、轉移模製（transfer molding）或類似者予以塗覆。在固化之後，密封體130可經歷研磨製程以暴露穿孔112以及晶粒連接件126。在研磨製程之後，穿孔112的頂部表面、晶粒連接件126的頂部表面與密封體130的頂部表面為共平面（coplanar）。在一些實施方式中，例如，若已暴露穿孔112以及晶粒連接件126，則可省略研磨步驟。
在圖6至圖8中，形成前側重佈線結構（front-side residstribution structure）144。如將在圖8中所示，前側重佈線結構144包含金屬化圖案132、136、140以及141，以及介電層134、138以及142。首先參考圖6，金屬化圖案132以及介電層134形成於密封體130、穿孔112以及晶粒連接件126上。金屬化圖案132包含導電線132A以及導通孔132B。導電線132A可直接形成於密封體130、穿孔112以及晶粒連接件126上。舉例而言，在導電線132A與穿孔112/晶粒連接件126之間可能不存在中間互連特徵（例如，其他導電線及/或通孔）。依據所需要之佈局設計，導電線132A可提供電佈線以將電訊號（例如，至/自穿孔112及/或晶粒連接件126）佈線至不同實體位置。導通孔132B形成於導電線132A上方，且導通孔132B允許電訊號傳遞至上方的膜層，例如，上方的金屬化圖案136、140以及141（見圖7以及圖8）。形成圍繞金屬化圖案132的介電層134。在一些實施方式中，介電層134由聚合物形成，聚合物可為感光性材料，諸如，PBO、聚醯亞胺、BCB或類似者，且經圖案化後可作為微影罩幕來使用。在其他實施方式中，介電層134可由氮化物（諸如氮化矽）、氧化物（諸如氧化矽、PSG、BSG、BPSG）或類似者而形成。金屬化圖案132以及介電層134可使用任何適合的形成製程予以形成，諸如，於圖9至圖17、圖18至圖20、圖21至圖23及/或圖24至圖32之實施方式中所描述的製程。
參考圖7，金屬化圖案136以及介電層138形成於金屬化圖案132以及介電層134上方。金屬化圖案136包含導電線136A以及導通孔136B。導電線136A可直接形成於金屬化圖案132以及介電層134上。舉例而言，在導電線136A與金屬化圖案132的導通孔132B之間可能不存在中間互連特徵（例如，其他導電線及/或通孔）。依據所需要之佈局設計，導電線136A可提供電佈線以將電訊號（例如，至/自導通孔132B）佈線至不同實體位置。導通孔136B形成於導電線136A上方，且導通孔136B允許電訊號傳遞至上方的膜層，例如，上方的金屬化圖案140以及141（見圖8）。形成圍繞金屬化圖案136的介電層138。在一些實施方式中，介電層138由聚合物形成，聚合物可為感光性材料，諸如，PBO、聚醯亞胺、BCB或類似者，且經圖案化後可作為微影罩幕來使用。在其他實施方式中，介電層138可由氮化物（諸如氮化矽）、氧化物（諸如氧化矽、PSG、BSG、BPSG）或類似者而形成。金屬化圖案136以及介電層138可使用任何適合的形成製程予以形成，諸如，於圖9至圖17、圖18至圖20、圖21至圖23及/或圖24至圖32之實施方式中所描述的製程。
參考圖8，金屬化圖案140、金屬化圖案141以及介電層142形成於金屬化圖案136以及介電質138上方。金屬化圖案140包含導電線，導電線可直接形成於金屬化圖案136以及介電層138上。舉例而言，在金屬化圖案140的導電線與金屬化圖案136的導通孔136B之間可能不存在中間互連特徵（例如，其他導電線及/或通孔）。依據所需要之佈局設計，金屬化圖案140的導電線可提供電佈線以將電訊號（例如，至/自導通孔136B）佈線至不同實體位置。
亦由圖8所示，金屬化圖案141形成於金屬化圖案140上。金屬化圖案141用以耦接至導電連接件148及/或表面安裝元件（surface mount device；SMD）146（見圖33），且可被稱作凸塊下金屬（under bump metallurgy；UBM）141。在一個實施方式中，藉由介電層142中的開口延伸至金屬化圖案140來形成UBM 141。
形成圍繞金屬化圖案140以及UBM 141的介電層142。在一些實施方式中，介電層142由聚合物形成，聚合物可為感光性材料，諸如，PBO、聚醯亞胺、BCB或類似者，且經圖案化後可作為微影罩幕來使用。在其他實施方式中，介電層142可由氮化物（諸如氮化矽）、氧化物（諸如氧化矽、PSG、BSG、BPSG）或類似者而形成。金屬化圖案140、UBM 141以及介電層142可使用任何適合的形成製程予以形成，諸如，於圖9至圖17、圖18至圖20、圖21至圖23及/或圖24至圖32之實施方式中所描述的製程。
圖9至圖17為在介電層（例如，介電層134、138及/或142）中形成金屬化圖案（例如，金屬化圖案132、136、140及/或141）的各種中間步驟。參考圖9，提供基板150。基板150可為緊接著隨後形成的金屬化圖案/介電層之下的任何層。舉例而言，基板150可包含位於介電層中的金屬化圖案。或者，基板150可包含至積體電路晶粒、密封體以及穿孔的晶粒連接件。在其他實施方式中，依據封裝設計，基板150可包含任何適合的材料組合。
如圖9所示，晶種層152形成於基板150上方。在一些實施方式中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成之多個子層的複合層。舉例而言，晶種層152可包括鈦、銅、鉬、鎢、氮化鈦、鎢化鈦、其組合或類似者。在一些實施方式中，晶種層包括鈦層152A以及位在鈦層152A上方的銅層152B。可例如藉由使用PVD或類似的製程來形成晶種層152。在一些實施方式中，基板150頂部表面（例如，其上形成有晶種層152的表面）為實質上共面的。當晶種層152沈積於基板150的頂部表面上時，晶種層152的頂部表面可具有基板150的頂部表面的輪廓。舉例而言，晶種層152可具有亦實質上共面的頂部表面。
在圖10以及圖11中，第一罩幕154形成且被圖案化於晶種層152上。在一些實施方式中，第一罩幕為光阻且可在下文中被稱作第一光阻154。第一光阻154可藉由旋轉塗佈形成為毯狀層（blanket layer）（見圖10）。在沈積第一光阻154之後，第一光阻154可暴露於例如是穿過經圖案化光罩的UV光或另一輻射源。接著，使第一光阻154顯影，並依據使用的是正型光阻還是負型光阻而移除第一光阻154的經暴露或者未經暴露之部分。所得之經圖案化第一光阻156示於圖11中，其中經圖案化第一光阻156具有延伸穿過（extend through）其之開口157。經圖案化第一光阻156的圖案對應於金屬化圖案的導電線158（見圖12）。開口157延伸穿過經圖案化第一光阻156且暴露出晶種層152。
隨後，在圖12中，導電材料（導電線158的一部分）形成於經圖案化第一光阻156（見圖11）的開口157中以及晶種層152的經暴露之部分上。導電線158可藉由鍍覆形成，諸如電鍍、化學鍍或類似的製程。導電線158可包括金屬，如銅、鈦、鎢、鋁或類似者。接著，如圖12所示，藉由可接受的灰化或剝離製程，例如使用氧電漿或類似的製程來移除經圖案化第一光阻156。導電線158可對應於圖6至圖8的導電線132A、導電線136A及/或金屬化圖案140。舉例而言，導電線132A、導電線136A及/或金屬化圖案140可使用類似於如本文中所描述之用於形成導電線158的製程而形成。
一旦經圖案化第一光阻156被移除，沈積第二罩幕160於晶種層152以及導電線158上方。在一些實施方式中，第二罩幕為光阻且可在下文中被稱作第二光阻160。第二光阻160可藉由旋轉塗佈形成為毯狀層（見圖13）。在沈積第二光阻160之後，第二光阻160可暴露於例如是穿過經圖案化光罩的UV光或另一輻射源。接著，使第二光阻160顯影，並依據使用的是正型光阻還是負型光阻而移除第二光阻160的經暴露抑或未經暴露部分。所得之經圖案化第二光阻162示於圖15中，其中所得之經圖案化第二光阻162具有延伸穿過其之開口161。經圖案化第二光阻162的圖案對應於金屬化圖案的導通孔164（見圖15）。開口161延伸穿過經圖案化第二光阻162且暴露出導電線158。
在一些實施方式中，經圖案化第二光阻162及/或經圖案化第一光阻156的材料可支援相對高解析度的微影圖案化，而允許形成相對精密間距的開口。舉例而言，在一個實施方式中，每一個開口161的寬度可小於約1 µm。藉由使用高解析度光阻材料，開口161中的隨後形成的特徵（例如，導通孔164，見圖15）可具有較小尺寸。因此，可有利地增大金屬化特徵的密度。在一些實施方式中，經圖案化第一光阻156及/或經圖案化第二光阻162可包括胺基化合物（amino compounds），諸如，三聚氰胺樹脂（melamine resins）、尿素樹脂（urea resins）、胍胺樹脂（guanamine resins）、甘脲甲醛樹脂（glycoluril-formaldehyde resins）、丁二醯胺甲醛樹脂（-formaldehyde resins）、乙烯尿素甲醛樹脂（ethylene urea-formaldehyde resins）及其組合。
隨後，在圖15中，導電材料（例如，導通孔164）形成於開口161（見圖14）中以及導電線158的經暴露之部分上。將導電線158用作晶種層形成導通孔164，而不沈積用於導通孔164的單獨晶種層，此允許以相對低製造成本形成導通孔164。導通孔164可藉由鍍覆形成，諸如，電鍍、化學鍍或類似的製程。導通孔164可包括金屬，如銅、鈦、鎢、鋁或類似者。接著，如圖15所示，藉由可接受的灰化或剝離製程，例如使用氧電漿或類似的製程來移除經圖案化第二光阻162。導通孔164可對應於圖6至圖8的導通孔132B、導通孔136B及/或UBM 141。舉例而言，導通孔132B、導通孔136B及/或UBM 141可使用如類似於本文中所描述的導通孔164的製程來形成。
在移除了經圖案化第二光阻162之後，可通過使用可接受的蝕刻製程（如濕式或乾式蝕刻）來移除晶種層152之經暴露的部分。晶種層152以及導電材料的剩餘部分形成包括導電線158以及導通孔164的金屬化圖案。
在圖16以及圖17中，圍繞導電線158以及導通孔164沈積介電層166。在一些實施方式中，介電層166由聚合物形成，聚合物可為感光性材料，諸如，PBO、聚醯亞胺、BCB或類似者，且經圖案化後可作為微影罩幕來使用。在其他實施方式中，介電層166可由氮化物（諸如氮化矽）、氧化物（諸如氧化矽、PSG、BSG、BPSG）或類似者而形成。介電層166可藉由旋轉塗佈、疊層、CVD、類似者或其組合形成。在介電層166包括感光性材料的實施方式中，介電層166可包括與第一光阻154（見圖10）及/或第二光阻160（見圖13）不同種類型的材料。舉例而言，第一光阻154及/或第二光阻160可支援比介電層166更高解析度的微影製程。
先形成介電層166以完全覆蓋導電線158以及導通孔164的頂部表面，如圖16所示。隨後，可將CMP或其他適合的平坦化製程應用於介電層166，以水平化介電層166的頂部表面及暴露出導通孔164。介電層166可對應於圖6至圖8的介電層134、介電層138及/或介電層142。舉例而言，介電層134、介電層138及/或介電層142可使用類似於介電層166的製程來形成。隨後，額外特徵可形成於介電層166以及導通孔164上方。舉例而言，可藉由重複圖9至圖17中所描述的製程在介電層166上方形成介電層中的額外金屬化圖案。
在圖9至圖17的製程中，經圖案化第二光阻162中的開口161（見圖14）與導電線158對準，以使得經圖案化第二光阻162僅暴露導電線158的頂部表面。在其他實施方式中，經圖案化第二光阻162暴露導電線158的頂部表面以及導電線158的側壁。
舉例而言，圖18至圖20為根據一些實施方式的形成金屬化圖案的各種中間步驟。在圖18中，經圖案化第二光阻162形成於導電線158上方。圖18的各種特徵可類似於圖14中的特徵，在所述圖式中以類似的符號說明表示使用類似製程（例如在圖9至圖14中所描述的各式製程）所形成的類似元件。
如由圖18說明，開口168形成於經圖案化第二光阻162中。開口168暴露導電線158的頂部表面以及側壁，且開口168的底部表面可由導電線158的材料以及經圖案化第二光阻162的材料界定。在圖18中，開口168僅部分地延伸穿過（partially extend through）經圖案化第二光阻162。舉例而言，經圖案化第二光阻162的部分配置於開口168的底部表面與晶種層152的頂部表面之間。開口168的深度例如可藉由在微影形成過程中控制暴露條件（例如，聚焦、能量或類似者）來控制。
隨後，在圖19中，導電材料（導通孔170）形成於經圖案化第二光阻162的開口168（見圖18）中以及導電線158的經暴露之部分上。將導電線158用作晶種層形成導通孔170，而不沈積用於導通孔170的單獨晶種層，此允許以相對低製造成本形成導通孔170。導通孔170可藉由鍍覆形成，諸如，電鍍、化學鍍或類似者。導通孔170可包括金屬，如銅、鈦、鎢、鋁或類似者。接著，如圖19所示，藉由可接受的灰化或剝離製程，諸如，使用氧電漿或類似的製程來移除圖案化第二光阻162。導通孔170可對應於圖6至圖8的導通孔132B、導通孔136B及/或UBM 141。舉例而言，導通孔132B、導通孔136B及/或UBM 141可使用如類似於本文中所描述的導通孔170的製程來形成。
隨後，藉由可接受的灰化或剝離製程，諸如，使用氧電漿或類似的製程來移除經圖案化第二光阻162。在移除了經圖案化第二光阻162之後，可通過使用可接受蝕刻製程（如濕式或乾式蝕刻）來移除晶種層152之經暴露的部分。晶種層以及導電材料的剩餘部分形成包括導電線158以及導通孔170的金屬化圖案。
由於開口168的位置（見圖18），導通孔170的位置可同樣地不同於導通孔164（見圖17）。舉例而言，導通孔170可僅部分地與下方的導電線158重疊，且導通孔170的部分可懸垂且比下方的導電線158延伸得更遠。
隨後，如圖20所示，圍繞導電線158以及導通孔170沈積介電層166。介電層166可經沈積以覆蓋導電線158以及導通孔170。在沈積之後，可將CMP或其他平坦化製程應用於介電層166，以暴露導通孔170以及改良介電層166的頂部表面的平坦度。介電層166的一部分可配置於導通孔170的底部表面及緊接在介電層166之下的層（例如，基板150）之間。隨後，額外特徵可形成於介電層166以及導通孔170上方。舉例而言，可藉由重複圖18至圖20中所描述的製程在介電層166上方形成介電層中的額外金屬化圖案。
圖21至圖23為根據一些其他實施方式之形成金屬化圖案的各種中間步驟。在圖21中，經圖案化第二光阻162形成於導電線158上方。圖21的各種特徵可類似於圖14中的特徵，在所述圖式中以類似的符號說明表示使用類似製程（諸如，在圖9至圖14中所描述的彼等製程）所形成的類似元件。
如圖21所示，開口174形成於經圖案化第二光阻162中。開口174暴露導電線158的頂部表面以及側壁，且開口168的底部表面可由導電線158的材料以及晶種層152的材料界定。不同於開口168（見圖18），開口174完全延伸穿過（extend completely through）經圖案化第二光阻162以暴露晶種層152。開口174的深度例如可藉由在微影形成過程中控制暴露條件（例如，聚焦、能量或類似者）來控制。
隨後，在圖22中，導電材料（導通孔176）形成於經圖案化第二光阻162的開口174（見圖21）中、導電線158之經暴露的部分以及晶種層152之經暴露的部分上。將導電線158以及晶種層152用作晶種層形成導通孔176，而不沈積用於導通孔176的單獨晶種層。此允許以相對低製造成本形成導通孔176。導通孔176可藉由鍍覆形成，諸如，電鍍、化學鍍或類似者。導通孔176可包括金屬，如銅、鈦、鎢、鋁或類似者。接著，如圖22所示，藉由可接受的灰化或剝離製程，諸如，使用氧電漿或類似的製程來移除圖案化第二光阻162。導通孔176可對應於圖6至圖8的導通孔132B、導通孔136B及/或UBM 141。舉例而言，導通孔132B、導通孔136B及/或UBM 141可使用如類似於本文中所描述的導通孔176的製程來形成。
隨後，藉由可接受的灰化或剝離製程，諸如，使用氧電漿或類似的製程來移除經圖案化第二光阻162。在移除了經圖案化第二光阻162之後，可通過使用可接受的蝕刻製程（如濕式或乾式蝕刻）來移除晶種層152之經暴露的部分。晶種層以及導電材料的剩餘部分形成包括導電線158以及導通孔176的金屬化圖案。
由於開口174的位置（見圖21），導通孔176的位置可同樣地不同於導通孔164（見圖17）或導通孔170（見圖19）。舉例而言，導通孔176可配置於導電線158的邊緣處，且沿導通孔176的側壁延伸的線亦可沿導電線158的側壁延伸。
隨後，如圖23所示，圍繞導電線158以及導通孔176沈積介電層166。介電層166可經沈積以覆蓋導電線158以及導通孔176。在沈積之後，可將CMP或其他平坦化製程應用於介電層166，以暴露導通孔176以及改良介電層166的頂部表面的平坦度。隨後，額外特徵可形成於介電層166以及導通孔176上方。舉例而言，可藉由重複圖21至圖23中所描述的製程在介電層166上方形成介電層中的額外金屬化圖案。
圖24至圖32為根據一些其他實施方式的在介電層（例如，介電層134、138及/或142）中形成金屬化圖案（例如，金屬化圖案132、136、140及/或141）的各種中間步驟。參考圖24，提供基板150。基板150可為緊接著在隨後形成的金屬化圖案/介電層之下的任何層。舉例而言，基板150可包含介電層中的金屬化圖案。或者，基板150可包含至積體電路晶粒、密封體以及穿孔的連接件。在其他實施方式中，基板150可包含任何適合的材料。
如圖24說所示，晶種層180形成於基板150上方。在一些實施方式中，晶種層為金屬層，金屬層可為包括單層或由不同材料形成的多個子層的複合層。舉例而言，晶種層180可包括鈦、銅、鉬、鎢、氮化鈦、鎢化鈦、其組合或類似者。在一些實施方式中，晶種層包括鈦層180A以及在鈦層180A上方的銅層180B。可例如藉由使用PVD或類似的製程來形成晶種層180。
在圖25中，經圖案化第一光阻182形成於晶種層180上。經圖案化第一光阻182可藉由旋轉塗佈形成為光阻材料的毯狀層。在一些實施方式中，經圖案化第一光阻182可包括胺基化合物，諸如，三聚氰胺樹脂、尿素樹脂、胍胺樹脂、甘脲甲醛樹脂、丁二醯胺甲醛樹脂、乙烯尿素甲醛樹脂以及其組合。在沈積光阻材料之後，可將光阻材料暴露於例如是穿過經圖案化光罩的UV光或另一輻射源。接著，使光阻材料顯影，並依據使用的是正型光阻還是負型光阻而移除光阻材料的經暴露或者未經暴露之部分。所得之經圖案化第一光阻182示於圖25中，其中經圖案化第一光阻182具有延伸穿過其之開口184。經圖案化第一光阻182的圖案對應於金屬化圖案的導通孔186（見圖26）。開口184延伸穿過經圖案化第一光阻182且暴露出晶種層180。
隨後，在圖26中，導電材料（導通孔186）形成於經圖案化第一光阻182的開口184（見圖25）中以及晶種層180之經暴露的部分。導通孔186可藉由鍍覆形成，諸如，電鍍、化學鍍或類似者。導通孔186可包括金屬，如銅、鈦、鎢、鋁或類似者。接著，如圖26所示，藉由可接受的灰化或剝離製程，例如使用氧電漿或類似的製程來移除經圖案化第一光阻182。導通孔186可對應於圖6至圖8的導通孔132B、導通孔136B及/或UBM 141。舉例而言，導通孔132B、導通孔136B及/或UBM 141可使用如類似於本文中所描述的導通孔186的製程來形成。
一旦經圖案化第一光阻182被移除，則圍繞導通孔186沈積介電層188，如圖27所示。在一些實施方式中，介電層188由聚合物形成，聚合物可為感光性材料，諸如，PBO、聚醯亞胺、BCB或類似者，且經圖案化後可作為微影罩幕來使用。在其他實施方式中，介電層188可由氮化物（諸如氮化矽）、氧化物（諸如氧化矽、PSG、BSG、BPSG）或類似者而形成。在介電層188包括感光性材料的實施方式中，介電層188可包括與經圖案化第一光阻182（見圖25）不同種類型的材料。舉例而言，經圖案化第一光阻182可支援比介電層188更高解析度的微影製程。
介電層188可藉由旋轉塗佈、疊層、CVD、類似的製程或其組合而形成。先形成介電層188以完全覆蓋導通孔182的頂部表面，如圖27所示。隨後，可將CMP或其他適合的平坦化製程應用於介電層188，以水平化介電層188的頂部表面及暴露出導通孔186，如圖28所示。
隨後，在圖29至圖31中，導電線158形成於介電層188以及導通孔186上方。導電線158可電性連接至下方的導通孔186。形成導電線158的製程可包含與在圖9至圖12中所描述之類似的製程，在所述圖式中以類似符號說明表示類似元件。在形成導電線158之後，可通過使用可接受的蝕刻製程（如濕式或乾式蝕刻）來移除晶種層152之經暴露的部分。晶種層以及導電材料的剩餘部分形成包括導電線158的金屬化圖案。
接著，如圖32所示，圍繞導電線158沈積介電層166。介電層166可經沈積以覆蓋導電線158。在沈積之後，可將CMP或其他平坦化製程應用於介電層166，以暴露導電線158以及改良介電層166的頂部表面的平坦度。隨後，額外特徵可形成於介電層166以及導電線158上方。舉例而言，可藉由重複圖24至圖32中所描述的製程在介電層166上方形成介電層中的額外金屬化圖案。
圖33至圖36為根據一些實施方式於進一步形成第一封裝以及用於將其他封裝結構附接至第一封裝的形成過程的中間步驟的剖面示意圖。透過本文中所描述的各種實施方式製程於前側重佈線結構144中形成金屬化圖案之後，執行圖33至圖36的製程。
參考圖33，導電連接件148形成於UBM 141上。導電連接件148可為BGA連接件、焊料球、金屬柱、受控塌陷晶粒連接（controlled collapse chip connection；C4）凸塊、微凸塊、化學鍍鎳鈀浸金（electroless nickel-electroless palladium-immersion gold technique；ENEPIG）技術形成的凸塊或類似者。導電連接件148可包含導電材料，諸如，焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施方式中，可例如以一般所採用的方法，如蒸鍍(evaporation)、電鍍(electroplating)、印刷(printing)、焊料轉移(solder transfer)、植球(ball placement)或類似者所形成的最初焊料層來形成導電連接件148。一旦焊料層已形成於結構上，則可執行回焊以便將材料塑形成所要之凸塊形狀。在另一實施方式中，導電連接件148例如為藉由濺鍍、列印、電鍍、化學鍍、CVD或類似者所形成的金屬柱（如銅柱）。金屬柱可以是無焊料且具有實質上垂直的側壁。在一些實施方式中，金屬頂蓋層（未繪示）形成於金屬柱連接件148的頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可藉由鍍覆製程形成。
如圖33所示，表面安裝元件（surface mount device；SMD）146亦可形成於UBM 141上。SMD 146可包含被動元件，諸如，電容器、電阻器、電感器、其組合或類似者。SMD 146可經由重佈線結構144中的金屬化圖案電性連接至積體電路晶粒114。
在圖34中，執行載體基板剝離，以將載體基板100自背側重佈線結構（例如，介電層104）分離（剝離）。根據一些實施方式，剝離包含使諸如雷射光或UV光的光投影於釋放層102上，以使得釋放層102在光熱下分解且可移除載體基板100。接著翻轉結構且將其置放於膠帶190上。
如圖34所示，穿過介電層104而形成開口，以暴露金屬化圖案106的部分。舉例而言，可以使用雷射鑽孔、蝕刻或類似的製程形成開口。
在圖35中，藉由沿切割道區（例如，在相鄰近的第一封裝區600與第二封裝區602之間）鋸割來執行單體化製程。鋸割步驟將第一封裝區600自第二封裝區602單體化。
所得之單體化封裝200示於圖35中，其中封裝200可以是第一封裝區600或第二封裝區602中的一者。封裝200亦可被稱作整合扇出型（integrated fan-out；InFO）封裝200。
如圖36所示，封裝結構500包含封裝200（可被稱作第一封裝200）、第二封裝300以及基板400。第二封裝300包含基板302以及耦接至基板302的一或多個堆疊式晶粒308（308A以及308B）。基板302可由半導體材料製成，諸如，矽（silicon）、鍺（germanium）、金剛石（diamond）或類似者。在一些實施方式中，亦可使用化合物材料，諸如，矽鍺（silicon germanium）、碳化矽（silicon carbide）、砷化鎵（gallium arsenic）、砷化銦（indium arsenide）、磷化銦（indium phosphide）、碳化矽鍺（silicon germanium carbide）、磷化鎵砷（gallium arsenic phosphide）、磷化鎵銦（gallium indium phosphide）、其組合及類似者。另外，基板302可為絕緣層上矽（silicon-on-insulator；SOI）基板。通常，SOI基板包含半導體材料，例如是磊晶矽、鍺、矽鍺、SOI、絕緣層上矽鍺（silicon germanium on insulator；SGOI）或其組合。在一個替代的實施方式中，基板302例如是基於絕緣芯，例如玻璃纖維增強樹脂芯。舉例來說，芯材料例如為玻璃纖維樹脂，諸如，FR4。芯材料的替代方案例如包含雙馬來醯亞胺三嗪（bismaleimide-triazine；BT）樹脂，又或者是其他印刷電路板（printed circuit board；PCB）材料或膜層。累積（build up）膜，諸如，味之素累積膜（Ajinomoto build-up film；ABF）或其他的疊層物可用於基板302。
基板302可包含主動以及被動元件（未示於圖28中）。多種為本領域中具有通常知識者所知之元件，例如電晶體、電容器、電阻器、其組合以及類似者可以廣泛地用以產生半導體封裝300的設計的結構以及功能要求。元件可以透過使用任何適合的方法而形成。
基板302亦可包含金屬化層（未繪示）以及穿孔306。金屬化層可形成於主動以及被動元件上方，且經設計以連接各種元件以形成功能電路。金屬化層可由介電質（例如，低k介電材料（low-k dielectric material））層與導電材料（例如，銅）層的交替配置而形成，其中導電材料層透過通孔互連，且金屬化層可經由任何適合的製程（諸如，沈積、鑲嵌、雙鑲嵌或類似的製程）予以形成。在一些實施方式中，基板302實質上無主動以及被動元件。
基板302的第一側上可具有接合墊（bond pad）303以耦接至堆疊式晶粒308，且在基板302的第二側上具有接合墊304以耦接至導電連接件314，基板302的第二側與第一側相對。在一些實施方式中，藉由在基板302的第一側以及第二側上形成凹部（recesses）（未繪示）以在介電層（未繪示）中形成接合墊303及304。通過形成凹部，可以允許接合墊303以及304嵌入於介電層中。在其他實施方式中，因接合墊303以及304可形成於介電層上，而省略凹部。在一些實施方式中，接合墊303以及304包含由銅、鈦、鎳、金、鈀、類似者或其組合製成的薄晶種層（未繪示）。接合墊303以及304的導電材料可沈積於薄晶種層上方。可藉由電化學鍍鍍覆製程（electro-chemical plating process）、無電極鍍覆製程（electroless plating process）、CVD、ALD、PVD、類似者或其組合形成導電材料。在一個實施方式中，接合墊303以及304的導電材料為銅、鎢、鋁、銀、金、類似者或其組合。
在一個實施方式中，接合墊303以及304為包含三個導電材料層（例如鈦層、銅層以及鎳層）的UBM。然而，本領域中具有通常知識者所知之許多適合的材料及膜層的配置，諸如，鉻/鉻銅合金/銅/金的配置、鈦/鈦鎢/銅的配置，或銅/鎳/金的配置也都適合用於UBM 303以及304的形成。目前可用於UBM 303以及304之任何適合的材料或材料層應亦全部包含於本文的範疇內。在一些實施方式中，穿孔306延伸穿過基板302且將至少一個接合墊303耦接至至少一個接合墊304。
在上述之實施方式中，堆疊式晶粒308藉由打線（wire bond）310耦接至基板302，但也可以使用其他連接件，諸如，導電凸塊。在一個實施方式中，堆疊式晶粒308為堆疊式記憶體晶粒。舉例而言，堆疊式記憶體晶粒308可包含低功率（low-power；LP）雙資料速率（double data rate；DDR）記憶體模組，諸如，LPDDR1、LPDDR2、LPDDR3、LPDDR4、非揮發性記憶體或類似記憶體模組。
在一些實施方式中，堆疊式晶粒308以及打線310可由模製材料312密封。例如透過使用壓縮模製將模製材料312模製於堆疊式晶粒308以及打線310上。在一些實施方式中，模製材料312為模製化合物、聚合物、環氧樹脂、氧化矽填充物材料、類似者或其組合。藉由執行固化步驟以固化模製材料312，其中固化可為熱固化、UV固化、類似者或其組合。
在一些實施方式中，堆疊式晶粒308以及打線310埋入於模製材料312中，且在固化模製材料312之後，執行平坦化步驟（如研磨）以移除模製材料312的過量部分，以為第二封裝300提供實質上平坦（planar）的表面。
在形成第二封裝300之後，第二封裝300透過導電連接件314、接合墊304以及金屬化圖案106接合至第一封裝200。在一些實施方式中，堆疊式記憶體晶粒308可經由打線310、接合墊303以及304、穿孔306、導電連接件314以及穿孔112耦接至積體電路晶粒114。
導電連接件314可類似於上文所描述的導電連接件148，且並不在本文中重複描述，但導電連接件314無需與導電連接件148相同。在一些實施方式中，在接合導電連接件314之前，導電連接件314塗佈有助焊劑（未繪示），諸如，免洗助焊劑（no-clean flux）。導電連接件314可浸漬於助焊劑中，或助焊劑可噴射至導電連接件314上。在另一實施方式中，助焊劑可塗覆於金屬化圖案106的表面。
在一些實施方式中，導電連接件314可具有環氧樹脂助焊劑（未繪示），助焊劑在其與在第二封裝300附接至第一封裝200之後剩餘的環氧樹脂助焊劑的環氧樹脂部分中的至少一些回焊之前形成於導電連接件314上。此剩餘環氧樹脂部分可充當底填充料以減小應力且保護自回焊導電連接件314產生的接點。在一些實施方式中，底填充料（未繪示）可形成於第二封裝300與第一封裝200之間，且環繞導電連接件314。可在附接第二封裝300之後藉由毛細流動製程（capillary flow process）形成底填充料，或可在附接第二封裝300之前藉由適合的沈積方法形成底填充料。
第二封裝300與第一封裝200之間的接合可為焊料接合或直接金屬至金屬（諸如，銅至銅或錫至錫）接合。在一個實施方式中，藉由回流製程將第二封裝300接合至第一封裝200。在此回流形成過程，導電連接件314與接合墊304以及金屬化圖案106接觸，以將第二封裝300實體地且電性地耦接至第一封裝200。在接合製程之後，IMC（未繪示）可形成於金屬化圖案106與導電連接件314的界面處，且亦形成於導電連接件314與接合墊304之間的界面處（未繪示）。
半導體封裝500包含安裝至基板400上的第一封裝200以及第二封裝300。基板400可被稱作封裝基板400。使用導電連接件148將封裝200安裝至封裝基板400。
封裝基板400可由半導體材料製成，諸如，矽、鍺、金剛石或類似者。或者，亦可使用化合物材料，諸如，矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等的組合及類似者。另外，封裝基板400可為SOI基板。大體而言，SOI基板包含半導體材料層，諸如，磊晶矽、鍺、矽鍺、SOI、SGOI或其組合。在一個替代性實施方式中，基板400例如是基於絕緣芯，例如玻璃纖維增強樹脂芯。舉例來說，芯材料例如為玻璃纖維樹脂，例如FR4。芯材料的替代方案包含雙馬來醯亞胺三嗪BT樹脂，或者，其他PCB材料或膜。封裝基板400亦可以使用累積膜，例如ABF或其他疊層物。
封裝基板400可包含主動以及被動元件（未示於圖36中）。多種為本領域中具有通常知識者所知之元件，諸如，電晶體、電容器、電阻器、其組合以及類似者可以廣泛地用以產生半導體封裝500的設計的結構以及功能要求。可使用任何適合的方法形成元件。
封裝基板400亦可包含金屬化層、通孔（未繪示）以及位在金屬化層以及通孔上方的接合墊402。金屬化層可形成於主動以及被動元件上方，且經設計以連接各種元件以形成功能電路。金屬化層可由介電質（例如，低k介電材料）層與導電材料（例如，銅）層的交替配置而形成，其中導電材料層透過通孔互連，且金屬化層可經由任何適合的製程（諸如，沈積、鑲嵌、雙鑲嵌或類似的製程）予以形成。在一些實施方式中，封裝基板400實質上無主動以及被動元件。
在一些實施方式中，回焊導電連接件148以將第一封裝200附接至接合墊402。導電連接件148將封裝基板400（包含封裝基板400中的金屬化層）電性地及/或實體地耦接至第一封裝200。
導電連接件148可具有環氧樹脂助焊劑（未繪示），助焊劑在其與在第一封裝200附接至封裝基板400之後剩餘的環氧樹脂助焊劑的環氧樹脂部分中的至少一些回焊之前形成於導電連接件148上。此剩餘環氧樹脂部分可充當底填充料以減小應力且保護自回焊導電連接件148產生的接點。在一些實施方式中，底填充料（未繪示）可形成於第一封裝200與封裝基板400之間，且環繞導電連接件148。可在附接第一封裝200之後藉由毛細流動製程形成底填充料，或可在附接第一封裝200之前藉由適合的沈積方法形成底填充料。
RDL後形成製程繪示於圖1至圖36中。舉例而言，在將積體電路晶粒114配置於第一封裝200中之後，在積體電路晶粒114上方形成重佈線結構144。在其他實施方式中，可在形成RDL之後將積體電路晶粒114接合至封裝特徵（有時稱作RDL先形成製程）。舉例而言，圖37至圖40為根據一些替代性實施方式的製造半導體封裝的各種中間階段的剖面示意圖。
在圖37中，重佈線結構144在附接積體電路晶粒114之前形成於載體基板100上方。用以形成重佈線結構144的製程可實質上類似於在圖1至圖36中所描述的製程，其中以類似符號說明表示類似元件。
在形成重佈線結構144之後，導電柱700形成於重佈線結構144上，如圖38所示。作為形成導電柱700的示範例，晶種層（未繪示）形成於重佈線結構144上方。在一些實施方式中，晶種層為金屬層，金屬層可為包括單層或由不同材料形成的多個子層的複合層。在一些實施方式中，晶種層包括鈦層以及在鈦層上方的銅層。可例如藉由使用PVD或類似的製程來形成晶種層。接著在晶種層上形成並圖案化光阻。光阻可藉由旋轉塗佈或類似的製程而形成且暴露於光以用於圖案化。光阻的圖案對應於導電柱700。圖案化光阻形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中且形成於晶種層之經暴露的部分上。導電材料可藉由鍍覆而形成，諸如，電鍍、化學鍍或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。接著，移除於其上方未形成導電材料的部分光阻以及晶種層。可藉由可接受的灰化或剝離製程來移除光阻，諸如，使用氧電漿或類似者。一旦光阻被移除，可透過使用可接受的蝕刻製程（如濕式或乾式蝕刻）移除晶種層之經暴露的部分。晶種層以及導電材料的剩餘部分形成導電柱700。
在圖39中，積體電路晶粒114使用適合的接合製程（諸如，覆晶接合）接合至重佈線結構144。積體電路晶粒114可使用導電連接件702接合至導電柱700。導電連接件702可包括微凸塊（microbumps；µbumps）、C4凸塊、BGA球或類似者。積體電路晶粒114可包含如上文關於圖4的積體電路晶粒114所描述的類似特徵，其中以類似符號說明表示類似元件。
隨後，在圖40中，密封體704形成於各個組件上。密封體704可為模製化合物、環氧樹脂或類似者，且可藉由壓縮模製、轉移模製或類似者予以塗覆。可圍繞積體電路114以及在積體電路晶粒114與重佈線結構144之間施配密封體704。在固化之後，密封體704可視情況經歷研磨製程以暴露積體電路晶粒114。在一些實施方式中，可省略研磨步驟。在形成密封體704之後，可自載體100剝離各種特徵，且可沿切割道（例如配置於相鄰近之第一封裝區600與第二封裝區602之間）執行單體化製程。導電連接件（未繪示）可形成於重佈線結構144的一相對側上（例如，在金屬化圖案132上）。導電連接件可用以接合單體化的封裝至其他封裝特徵，諸如，其他積體電路晶粒、元件封裝、封裝基板、中介層（interposer）、主板（motherboard）、其組合或類似者。
因此，如上文所描述，各種實施方式提供在半導體封裝的重佈線結構中形成導電特徵（諸如，導電線及/或通孔）的方法。實施方式製程可使用用以界定導通孔的圖案的光阻來形成導通孔。因為在形成導通孔之後隨後移除光阻，所以對用於光阻的材料的選擇不限於適合於包含在已完成包裝中的介電材料。舉例而言，可選擇光阻的材料以支援相對高解析度的微影，相對高解析度微影允許形成精密間距的導通孔。實施方式導通孔可具有約1µm或更小的寬度，但亦可形成具有其他尺寸的通孔。在移除光阻之後，圍繞通孔形成介電層，且選擇介電質層的材料以向配置於其中的重佈線圖案提供結構支撐以及絕緣。儘管介電層亦可包括感光性材料，但介電層可能不支援與用以界定導通孔的光阻同樣高的解析度圖案化。因此，各種實施方式可提供以下至少一種非限制性優點：藉由使用較高解析度光阻以定義較小導通孔之導通孔的形狀、降低製造成本、減小聚合物層解析度窗口問題、重佈線層中的改良的平坦度、增加金屬化圖案密度以及類似者。
本發明實施例提供一種半導體封裝中的密集型重佈線層的形成方法，其包括以下步驟。在晶種層上方形成經圖案化第一光阻，其中經圖案化第一光阻中的第一開口暴露晶種層。在晶種層上的第一開口中鍍覆第一導電材料。移除經圖案化第一光阻。在移除經圖案化第一光阻之後，在第一導電材料的側壁上方且沿側壁形成經圖案化第二光阻，其中經圖案化第二光阻中的第二開口暴露第一導電材料的一部分。在第一導電材料上的第二開口中鍍覆第二導電材料。移除經圖案化第二光阻。在移除經圖案化第二光阻之後，移除晶種層的經暴露部分。圍繞第一導電材料以及第二導電材料沈積介電層。
在一些實施方式中，半導體封裝中的密集型重佈線層的形成方法更包括平坦化介電層，以使得介電層的頂部表面與第二導電材料的頂部表面實質上齊平。在一些實施方式中，經圖案化第二光阻的感光性材料配置於第二導電材料的底部表面與晶種層之間。在一些實施方式中，第二開口更暴露晶種層的一部分。在一些實施方式中，半導體封裝中的密集型重佈線層的形成方法更包括在積體電路晶粒上方以及在密封積體電路晶粒的密封體上沈積晶種層。在一些實施方式中，半導體封裝中的密集型重佈線層的形成方法更包括在載體基板上方沈積晶種層；以及在沈積介電層之後，使用覆晶接合製程在介電層上方接合積體電路晶粒。在一些實施方式中，半導體封裝中的密集型重佈線層的形成方法更包括密封積體電路晶粒，其中密封積體電路晶粒包括在積體電路晶粒的底部表面與介電層之間施配密封體。在一些實施方式中，其中介電層包括感光聚合物，且其中經圖案化第二光阻支援比感光聚合物更高解析度的微影製程。
本發明實施例提供一種半導體封裝中的密集型重佈線層的形成方法，其包括以下步驟。將積體電路晶粒密封於密封體中。在密封體以及積體電路晶粒上方沈積第一光阻。在第一光阻中圖案化出第一開口，以暴露第一導電材料。在第一開口中鍍覆導通孔，其中導通孔電性連接至積體電路晶粒。移除第一光阻。圍繞導通孔沈積第一聚合物層，其中第一聚合物層與第一光阻包括不同材料。平坦化第一聚合物層，以使得第一聚合物層的頂部表面與導通孔的頂部表面實質上齊平。
在一些實施方式中，第一導電材料為導電線，其中沈積第一聚合物層更包括沿導電線的側壁沈積第一聚合物層。在一些實施方式中，半導體封裝中的密集型重佈線層的形成方法更包括在積體電路晶粒以及密封體上方沈積第二光阻；在第二光阻中圖案化出第二開口；在第二開口中鍍覆導電線，其中導電線電性連接至積體電路晶粒；以及移除第二光阻，其中在移除第二光阻之後沈積第一光阻。在一些實施方式中，沈積第一聚合物層包括在導通孔的底部表面下沈積第一聚合物層的一部分。在一些實施方式中，第一導電材料為第一晶種層，且其中半導體封裝中的密集型重佈線層的形成方法更包括在平坦化第一聚合物層之後，在第一聚合物層以及導通孔上方沈積第二晶種層；在第二晶種層上方沈積第二光阻；在第二光阻中圖案化出暴露第二晶種層的第二開口；在第二開口中鍍覆電性連接至導通孔的導電線；以及圍繞導電線沈積第二聚合物層。在一些實施方式中，半導體封裝中的密集型重佈線層的形成方法更包括平坦化第二聚合物層，以使得第二聚合物層的頂部表面與導電線的頂部表面實質上齊平。
本發明實施例提供一種半導體封裝，其包括積體電路晶粒、密封體、穿孔以及重佈線結構。密封體經配置而圍繞積體電路晶粒。穿孔延伸穿過密封體。重佈線結構位在積體電路晶粒以及密封體上方，其中重佈線結構的金屬化圖案包括導電線以及導通孔。導電線配置於介電層中且電性連接至積體電路晶粒，其中介電層接觸密封體的頂部表面。導通孔位在導電線上方且電性連接至導電線，其中導通孔的頂部表面與介電層的頂部表面實質上齊平。
在一些實施方式中，介電層的一部分配置於導通孔的底部表面下。在一些實施方式中，沿導電線的側壁延伸的線亦沿導通孔的側壁延伸。在一些實施方式中，介電層的底部表面與導電線的頂部表面實質上齊平，其中沿著垂直於介電層的頂部表面的線，無其他導電特徵配置於介電層與密封體之間。在一些實施方式中，重佈線結構的額外金屬化圖案包括與導通孔的頂部表面的形成接面的額外導電線。在一些實施方式中，導電線包括在導電材料下的晶種層，且其中晶種層的頂部表面為實質上共面的。
前文概述數個實施方式的特徵，以使得本領域的技術人員可較佳地理解本發明實施例的態樣。本領域的技術人員應理解，其可易於使用本發明實施例作為設計或修改用於進行本文中所引入的實施方式的相同目的及/或達成相同優點的其他製程以及結構的基礎。本領域的技術人員亦應認識到，此類等效構造並不脫離本發明的精神以及範疇，且其可在不脫離本發明的精神以及範疇的情況下在本文中進行各種改變、替代以及更改。
100‧‧‧載體基板
102‧‧‧釋放層
104、134、138、142、166、188‧‧‧介電層
106、132、136、140、141‧‧‧金屬化圖案
110‧‧‧背側重佈線結構
112、306‧‧‧穿孔
114‧‧‧積體電路晶粒
116‧‧‧黏著劑
118‧‧‧半導體基板
120‧‧‧互連結構
122‧‧‧墊
124‧‧‧鈍化膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130、704‧‧‧密封體
132A、136A、158‧‧‧導電線
132B、136B、164、170、176、186‧‧‧導通孔
144‧‧‧前側重佈線結構
146‧‧‧表面安裝元件
148、314、702‧‧‧導電連接件
150、302、400‧‧‧基板
152、180‧‧‧晶種層
152A、180A‧‧‧鈦層
152B、180B‧‧‧銅層
154‧‧‧第一罩幕/第一光阻
160‧‧‧第二罩幕/第二光阻
156、182‧‧‧經圖案化第一光阻
157、161、168、174、184‧‧‧開口
162‧‧‧經圖案化第二光阻
190‧‧‧膠帶
200‧‧‧第一封裝
300‧‧‧第二封裝/半導體封裝
303、304、402‧‧‧接合墊
308A、308B‧‧‧堆疊式晶粒
310‧‧‧打線
312‧‧‧模製材料
500‧‧‧封裝結構/半導體封裝
600、602‧‧‧封裝區
700‧‧‧導電柱
當結合附圖閱讀時，自以下詳細描述最好地理解本發明實施例的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，為論述清楚起見，可任意增加或減小各種特徵的尺寸。 圖1至圖36為根據一些本發明實施例的形成半導體元件封裝的各種中間階段。 圖37至圖40為根據一些其他本發明實施例的形成半導體元件封裝的各種中間階段。

Claims (1)

  1. 一種半導體封裝中的密集型重佈線層的形成方法，其包括： 在晶種層上方形成經圖案化第一光阻，其中所述經圖案化第一光阻中的第一開口暴露所述晶種層； 在所述晶種層上的所述第一開口中鍍覆第一導電材料； 移除所述經圖案化第一光阻； 在移除所述經圖案化第一光阻之後，在所述第一導電材料的側壁上方且沿所述側壁形成經圖案化第二光阻，其中所述經圖案化第二光阻中的第二開口暴露所述第一導電材料的一部分； 在所述第一導電材料上的所述第二開口中鍍覆第二導電材料； 移除所述經圖案化第二光阻； 在移除所述經圖案化第二光阻之後，移除所述晶種層的經暴露部分；以及 圍繞所述第一導電材料以及所述第二導電材料沈積介電層。
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