CN113140516A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN113140516A
CN113140516A CN202011310609.0A CN202011310609A CN113140516A CN 113140516 A CN113140516 A CN 113140516A CN 202011310609 A CN202011310609 A CN 202011310609A CN 113140516 A CN113140516 A CN 113140516A
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interposer
package
forming
carrier
redistribution
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CN113140516B (zh
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林士庭
卢思维
陈伟铭
丁国强
侯上勇
吴集锡
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例涉及封装件及其形成方法。一种形成封装件的方法包括将半导体器件附接到中介层结构，将中介层结构附接到第一载体衬底，将集成的无源器件附接到第一载体衬底，在半导体器件和集成的无源器件上方形成密封剂，将第一载体衬底分离，将密封剂和半导体器件附接到第二载体衬底，在密封剂、中介层结构和集成无源器件上形成第一再分布结构，其中，第一再分布结构接触中介层结构和集成无源器件，以及在第一再分布结构上的形成外部连接件。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
自集成电路(IC)的发展以来，由于各种电子部件(即，晶体管、二极管、电阻器、电容器等)在集成密度方面不断提高，半导体产业经历了持续快速的增长。大多数情况下，集成密度的提高来自最小部件尺寸的不断减小，这使得更多的部件可以集成到给定区域中。
这些集成的改进本质上是二维(2D)的，因为集成部件占据的区域基本上是在半导体晶圆的表面上。增加的密度和相应的集成电路面积的减小通常已经超过了将集成电路芯片直接结合到衬底上的能力。中介层已用于从芯片区域到较大的中介层区域重新分配球接触区域。此外，中介层已允许包括多个芯片的三维封装件。也已开发其他封装件来合并三维的层面。
发明内容
根据本发明的一个方面，提供了一种形成封装件的方法，包括：形成器件结构，包括：将第一管芯连接到第一中介层；将第二管芯连接至第二中介层；和在第一中介层和第二中介层上方形成第一再分布结构，其中，第一再分布结构将第一中介层电连接到第二中介层；以及形成封装件结构，包括：将第一表面安装器件(SMD)和器件结构附接到第一载体；用第一密封剂密封第一SMD和器件结构，以形成具有顶表面和底表面的密封结构；将密封结构的顶表面附接到第二载体；和在密封结构的底表面上方形成第二再分布结构，其中，第二再分布结构将第一SMD和器件结构电连接。
根据本发明的另一个方面，一种形成封装件的方法，包括：将多个半导体器件附接到中介层结构；将中介层结构附接到第一载体衬底；将多个集成无源器件附接到第一载体衬底；在多个半导体器件和多个集成无源器件上方形成密封剂；分离第一载体衬底；将密封剂和多个半导体器件附接到第二载体衬底；在密封剂、中介层结构和多个集成无源器件上形成第一再分布结构，其中，第一再分布结构接触中介层结构和多个集成无源器件；以及在第一再分布结构上形成多个外部连接件。
根据本发明的又一个方面，提供了一种封装件，包括：器件衬底；和器件结构，附接到器件衬底的第一侧，器件结构包括：第一中介层；第二中介层；多个第一半导体器件，附接到第一中介层；多个第二半导体器件，附接到第二中介层；和第一再分布结构，连接到第一中介层和第二中介层。
附图说明
当结合参考附图进行阅读时，根据下文具体的描述可以更好地理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘出且仅用于示出的目的。事实上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1-图2是根据一些实施例在形成器件封装件的工艺期间的中间步骤的截面图。
图3A-图3C是根据一些实施例在形成器件封装件的工艺期间的中间步骤的截面图和平面图。
图4-图9是根据一些实施例在形成器件封装件的工艺期间的中间步骤的截面图。
图10-图13是根据一些实施例在形成器件结构的工艺期间的中间步骤的截面图。
图14是根据一些实施例在形成器件封装件的工艺期间的中间步骤的平面图。
图15是根据一些实施例的器件封装件的示意图。
图16A-图16C是根据一些实施例在形成封装件结构的工艺期间的中间步骤的截面图。
图17-图22是根据一些实施例在形成封装件结构的工艺期间的中间步骤的截面图。
图23A-图23C是根据一些实施例在形成封装件结构的工艺期间的中间步骤的截面图。
图24-图28是根据一些实施例在形成封装件结构的工艺期间的中间步骤的截面图。
图29是根据一些实施例的封装件结构的截面图。
具体实施方式
以下公开内容提供了许多用于实施所公开的不同特征的不同实施例或实例。以下描述组件和配置的具体实例以简化本发明。当然，这仅仅是实例，并不是用于限制本发明。而且，在以下描述中，第一部件形成在第二部件上方或者之上可以包括第一部件和第二部件直接接触的实施例，还可以包括在第一部件和第二部件之间插入有附加部件，从而使得第一部件和第二部件不直接接触的实施例。再者，本公开可在各个示例中重复参照数字和/或字母。该重复是为了简明和清楚，而且其本身没有规定所述各种实施例和/或结构之间的关系。
此外，为了便于描述，诸如“在…下面”、“在…下方”、“下”、“在…上方”、“上”等空间相对位置术语在本文中可以用于描述如附图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。应该理解，除了图中描述的方位外，这些空间相对位置术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，并因此对本文中使用的空间相对位置描述符进行同样的解释。
根据一些实施例，描述了包含集成电路器件的封装件。在一些实施例中，描述了包含通过再分布结构电连接的多个器件封装件的器件结构。使用再分布结构可以允许在每个器件封装件内形成较小的部件，这可以改善性能和光刻图案化。根据一些实施例，可以形成包括电子器件(例如，表面安装器件(SMD))、器件封装件和/或器件结构的封装件结构。通过使用两个分离的载体来形成封装件结构，可以使用具有不同厚度的电子器件。另外，可以使用再分布结构来形成电互连，这可以减少加工成本和加工步骤的数量。
图1是根据一些实施例的集成电路器件50的截面图。集成电路器件50可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、微控制器等)、存储管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或其组合。集成电路器件50可以形成在晶圆中，该晶圆可以包括在后续步骤中被分离以形成多个集成电路器件50的不同的器件区域。集成电路器件50包括衬底52和互连结构54。
衬底52可以包括体半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。衬底52的半导体材料可以是硅，锗，包括硅锗、硅碳、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体，包括SiGe，GaAsP，AlInAs，AlGaAs，GaInAs，GaInP和/或GaInAsP的合金半导体，或其组合。也可以使用诸如多层或梯度衬底的其他衬底。衬底52可以是掺杂的或未掺杂的。诸如晶体管、电容器、电阻器、二极管等器件可以形成在衬底52的有源表面(例如，向上的表面)中和/或上。
在衬底52的有源表面上形成具有一个或多个介电层和相应的金属化图案的互连结构54。介电层可以是金属间电介质(IMD)层。例如，IMD层可以由诸如未掺杂的硅酸盐玻璃(USG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy，旋涂-玻璃、旋涂聚合物、硅碳材料、他们的化合物、他们的复合材料、他们的组合等低K介电材料通过诸如旋涂、化学气相沉积(CVD)、等离子增强CVD(PECVD)、高密度等离子体化学气相沉积(HDP-CVD)等本领域已知的任何合适方法形成。介电层中的金属化图案可以例如通过使用通孔和/或迹线在器件之间传递电信号，并且还可以包含诸如电容器、电阻器、电感器等各种电器件。各种器件和金属化图案可以互连以执行一个或多个功能。该功能可以包括存储器结构、处理器结构、传感器、放大器、功率分配、输入/输出电路等。另外，可以在互连结构54之内和/或之上形成诸如导电柱或接触垫的管芯连接件，以提供到电路和器件的外部电连接。本领域普通技术人员将理解，提供以上示例是出于说明性目的。对于给定的应用，可以适当地使用其他电路。
在一些实施例中，集成电路器件50是包括多个衬底52的堆叠器件。例如，集成电路器件50可以是诸如混合存储立方体(HMC)模块、高带宽存储器(HBM)模块等的存储器件，并且可以包括多个存储器管芯。在这样的实施例中，集成电路器件50包括通过通孔互连的多个衬底52。每个衬底52可以具有(或可以不具有)分离的互连结构54。
图2是根据一些实施例的中介层70的截面图。尽管仅示出了一个中介层70，但是应当理解，中介层70可以形成在具有多个器件区域的晶圆中，每个器件区域都用于形成一个中介层70。中介层70包括衬底72、通孔74、和互连结构76。
衬底72可以是体半导体衬底、SOI衬底、多层半导体衬底等。衬底72的半导体材料可以是硅，锗，包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP的合金半导体，其组合等。也可以使用诸如多层或梯度衬底的其他衬底。衬底72可以是掺杂的或未掺杂的。诸如晶体管、电容器、电阻器、二极管等的器件可以形成在衬底72的表面内和/或上。在一些实施例中，衬底72是基于诸如玻璃纤维增强树脂芯片的绝缘芯片。例如，芯片材料可以是诸如FR4的玻璃纤维树脂、双马来酰亚胺-三嗪(BT)树脂、其他印刷电路板(PCB)材料或薄膜，组合等。诸如味之素(Ajinomoto)堆积膜(ABF)之类的堆积膜或其他层压制品可以用于衬底72。
通孔74形成为从衬底72的前表面延伸进衬底72中。通孔74有时也称为衬底通孔，或当衬底72为硅衬底时称为硅通孔(TSV)。可以通过例如通过蚀刻、铣削、激光技术，其组合等在衬底72中形成凹槽来形成通孔74。可以诸如通过使用氧化技术在凹槽中形成薄介电材料。可以诸如通过CVD、原子层沉积(ALD)、物理气相沉积(PVD)、热氧化、其组合等，在衬底72的前侧上方和开口中共形地沉积薄阻挡层。可以由诸如氮化钛、氧氮化钛、氮化钽、氧氮化钽、化钨、其组合等氮化物或氧氮化物形成阻挡层。可以在薄阻挡层上方和开口中沉积导电材料。可以通过电化学镀覆工艺、CVD、ALD、PVD、其组合等形成导电材料。导电材料的示例是铜、钨、铝、银、金、其组合等。可以通过诸如化学机械抛光(CMP)从衬底72的前侧去除过量的导电材料和阻挡层。因此，通孔74可以包括导电材料，具有在导电材料和衬底72之间的薄阻挡层。
互连结构76形成在衬底72的前表面上方，并且用于在衬底72的器件(如果有)、通孔74和/或外部器件之间形成电连接。互连结构76可以包括一个或多个介电层以及介电层中各自的金属化图案。金属化图案可以是包括形成电连接的通孔和/或迹线的再分布层(RDL)。在一些实施例中，互连结构76可以是再分布结构或扇出结构。
在一些实施例中，通过在衬底72上形成第一介电层(在图2中未单独标记)形成互连结构76。在一些实施例中，第一介电层由聚合物形成，该聚合物可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等光敏材料，可以使用光刻图案化该光敏材料。在其他实施例中，由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)等形成第一介电层。可以通过旋涂、层压、CVD等，或其组合形成第一介电层。然后图案化第一介电层以形成暴露通孔74的开口。在由光敏材料形成第一介电层的实施例中，可以通过根据期望的图案暴露第一介电层并执行显影工艺以去除不需要的材料来执行图案化，从而暴露出通孔74。也可以使用诸如使用图案化的掩模和蚀刻的其他技术来图案化第一介电层。
在第一介电层上方和在第一介电层中形成的开口中形成晶种层(图2中未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和在钛层上方的铜层。可以使用例如PVD等形成晶种层。然后根据期望的金属化图案在晶种层上形成并图案化掩膜(图2中未示出)。在一些实施例中，掩模是通过旋涂等形成的光刻胶，然后将光刻胶曝光以图案化。图案化形成穿过掩模的开口以暴露出晶种层。在掩模的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀的镀覆来形成导电材料。导电材料可以包括诸如铜、钛、钨、铝、这些的组合等的金属。然后，去除未在其上形成导电材料的光刻胶和部分晶种层。可以通过例如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。例如通过使用诸如通过湿法或干法蚀刻的可接受的蚀刻工艺，一旦去除了光刻胶，就去除了晶种层的暴露部分。晶种层的剩余部分和导电材料形成互连结构76内的第一RDL。
然后，可以在第一介电层上方形成附加的介电层和附加的RDL，以形成互连结构76内的附加电连接。可以使用与形成第一介电层和第一RDL相似的材料和工艺形成附加的介电层和附加的RDL。例如，可以在工艺中并且以与第一介电层相似的材料形成附加的介电层。可以穿过每个附加介电层形成开口以暴露下面的RDL的至少一部分。可以使用例如上面所描述的用于第一介电层的合适的光刻掩模和蚀刻工艺来形成开口，尽管可以替代地使用任何合适的工艺。在一些实施例中，由光敏聚合物形成附加介电层，并且可以使用光刻掩模和蚀刻工艺在附加介电层中直接图案化开口。
可以在每个附加的介电层中形成附加的RDL，以提供互连结构76内的附加的电连接。在一个实施例中，可以使用类似于第一RDL的材料和工艺形成附加的RDL。例如，用于附加的RDL的期望的图案中可以形成晶种层，并且在晶种层的顶部上放置和图案化光刻胶。然后可以使用例如电镀工艺在光刻胶的图案化开口中形成导电材料。然后可以去除光刻胶并且蚀刻晶种层，形成附加的RDL。可以由多个介电层和多个RDL以这种方式形成互连结构76。
在一些实施例中，可以在互连结构76的最上方的RDL上方形成和图案化凸块下金属结构层(UBM)。UBM提供到互连结构76的电连接，可以在互连结构76上放置诸如焊球/凸块、导电柱等电连接件。在一些实施例中，UBM包括扩散阻挡层、晶种层或它们的组合。扩散阻挡层可以包括Ti、TiN、Ta、TaN或其组合。晶种层可以包括铜或铜合金。但是，也可以包括诸如镍、钯、银、金、铝、它们的组合以及它们的多层的其他金属。可以使用溅射、电镀等形成UBM。
图3A至图15是根据一些实施例的在用于形成堆叠的半导体器件的工艺期间的中间步骤的截面图。在图3A至图9中，通过将各种集成电路器件50结合到中介层70的前侧来形成器件封装件100。在一些实施例中，第一器件封装件100是晶圆上芯片(CoW)封装件，尽管应当理解，实施例可以应用于其他三维集成电路(3DIC)封装件。器件结构100可以用于形成诸如封装件结构200(参见图22)或封装件结构300(参见图3A-图3C)的封装件结构。
在图3A-图3C中，一个或多个集成电路器件50附接到中介层70。图3A示出附接到中介层70的集成电路器件50A和50B的截面图，图3B-图3C示出根据一些实施例的以不同的布置附接到中介层70的集成电路器件50A和50B的平面图。互连结构54和76物理和电气连接集成电路器件50和插入件70。集成电路器件50可以通过互连结构76彼此电连接。集成电路器件50可以包括类似的器件和/或不同的器件。例如，图3A-图3C所示的实施例包括集成电路器件50A和集成电路器件50B，器件50A可以具有与器件50B不同的功能。集成电路器件50A或50B可各自具有单一功能(例如，逻辑器件、存储管芯等)，或可具有多种功能(例如，片上系统等)。在一个实施例中，集成电路器件50A是诸如CPU的逻辑器件，并且集成电路器件50B是诸如HBM模块的存储器件。在一些实施例中，集成电路器件50可以与其他集成电路器件50相关联。单个器件50A可具有与其相关联的并且电连接到该器件50A(例如，通过互连结构76)的一个或多个器件50B。
可以使用例如拾取和放置工具将集成电路器件50A和50B附接到互连结构76。在晶圆中形成中介层70的实施例中，集成电路器件50可以附着在晶圆的不同器件区域中。然后可以在随后的步骤中将不同的器件区域分离，以形成多个第一器件封装件100(参见图9)。可以以任何合适的配置在互连结构76上或器件区域内布置集成电路器件50。例如，图3B示出每个器件50A的一侧相邻有器件50B的器件50A，并且图3C示出每个器件50A的相对侧相邻有器件50B的器件50A。在一些实施例中，例如图3B的实施例，集成电路器件50B不对称地相邻集成电路器件50A布置。在一些实施例中，例如图3C的实施例，集成电路器件50B对称地相邻集成电路器件50A布置。不对称的布局可以允许集成电路器件50B更靠近集成电路器件50A的输入/输出(I/O)连接区域定位。这些是示例，并且其他配置或布置是可能的。
在图3A所示的实施例中，用包括导电凸块102、导电凸块104和导电连接件106的连接将集成电路器件50A和50B附接到互连结构76。导电凸块102电气和物理连接到是互连结构54，并且导电凸块104电气和物理连接到互连结构76。导电连接件106结合导电凸块102和104。导电凸块102可以形成在互连结构54或互连结构76的UBM(如果存在的话)上方。导电凸块102或104可以由诸如铜、铝、金、镍、钯等或其组合的导电材料形成。可以通过诸如溅射、印刷、电镀、化学镀、CVD等的适当工艺来形成导电凸块102或104。在一些实施例中，导电凸块102或104还可包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁或锥形的侧壁。导电凸块也可以称为微凸块。
导电连接件106可以由诸如焊料的导电材料形成，并且可以通过诸如蒸发、电镀、印刷、焊料转移、球置放等方法，通过在导电凸块102或104上初始形成焊料层而形成。一旦已经形成焊料层，就可以执行回流工艺以将导电连接件106成形为期望的凸块形状。
在其他实施例中，集成电路器件50通过面对面结合附接到互连结构76。例如，可以使用混合结合、熔融结合、直接结合、介电结合、金属结合等附接互连结构54和76而不使用焊料。此外，可以使用混合结合技术，例如，一些集成电路器件50A和50B可以通过导电连接件106结合到互连结构76，以及可以通过面对面结合将其他集成电路器件50A和50B结合到互连结构76。
在图4中，底部填充材料108分配在集成电路器件50和互连结构76之间。底部填充材料108围绕导电凸块102和104和导电连接件106。底部填充材料108可以是例如聚合物、环氧树脂、模制底部填充胶等任何可接受的材料。底部填充材料108可以通过毛细管流动工艺形成。
在图5中，在结构的各个部件上形成密封剂112。密封剂112可以是模塑料、环氧树脂等，并且可以通过压缩模制、传递模制等被应用。密封剂112可以形成在互连结构76上方，使得集成电路器件50和底部填充材料110被密封剂112围绕并覆盖。然后可以固化密封剂112。在一些实施例中，去除(例如，通过CMP)过量的密封剂112的材料，这也可以使结构平坦化，使得密封剂112的顶表面和集成电路器件50的顶表面是水平的。
在图6中，该结构被翻转并附接到载体114或其他合适的支撑结构用于后续工艺。载体114可以是玻璃载体衬底、陶瓷载体衬底等。载体114可以是晶圆，使得可以同时在载体114上形成多个封装件。该结构可以例如通过释放层116附接到载体114。可以由基于聚合物的材料形成释放层116，其可以从将在后续步骤中形成的上覆结构中与载体114一起被去除。在一些实施例中，释放层116是在加热时失去粘合特性的诸如光热转换(LTHC)释放涂层的基于环氧的热释放材料。在其他实施例中，释放层116可以是当暴露于UV光时会失去其粘合特性的紫外线(UV)胶。释放层116可以被配置为液体并且被固化，可以是层压到载体114上的层压膜，或者可以是类似的。释放层116的顶表面可以是水平的并且可以具有高度共面性。
在图7中，衬底72被减薄(例如，通过CMP)以暴露通孔74。在一些实施例中，衬底72的暴露表面和通孔74的暴露表面是水平的。在一些实施例中(未示出)，可以执行凹陷工艺以使衬底72凹陷，使得通孔74从衬底72的背侧突出。凹陷工艺可以是例如使用湿蚀刻和/或干蚀刻的合适的回蚀刻工艺。在一些实施例中，可以在衬底72的背侧上形成绝缘层(未示出)，该绝缘层围绕并保护通孔74的突出部分。
在图8中，将结构从载体114上分离并切割，形成一个或多个器件封装件100。根据一些实施例，分离包括在释放层116上投射诸如激光或紫外(UV)光的光，使得释放层116在光的热量下分解，并且可以去除载体114。在其他实施例中，可以使用去除剥离层116或载体114的其他技术。然后可以将该结构放置在胶带111等上，然后分离该结构以形成单个的器件封装件100，如图8所示。例如，可以沿着相邻器件区域之间的划线区域分离中介层70以形成器件封装件100。分离工艺可以包括锯切、切块等。在分离之后，每个器件封装件100的中介层70的侧壁和密封剂112的侧壁可以是共面的。在图9中示出了单个器件封装件100。在一些实施例中，单个器件封装件100可以具有在大约20mm和大约50mm之间的长度或宽度(例如，图9中所示的LW1)。器件封装件100也可以称为晶圆上芯片(CoW)器件。
图10至图16是根据一些实施例的在形成器件结构110(参见图12)的工艺期间的中间步骤的截面图和平面图。每个器件结构110包括通过再分布结构120彼此电连接的多个器件封装件100。类似于上述器件封装件100，器件结构110可以用于形成诸如封装件结构300(参见图28)的封装件结构。在器件结构110的一些实施例中，不是将单个大的中介层70用于一组集成电路器件50(如在器件封装件100中)，而是在分离的、较小的、通过再分布结构120电连接的中介层70上形成多组集成电路器件50。在某些情况下，以这种方式形成较小的中介层70允许使用标线，该标线配置为在互连结构76的光刻图案化期间缩减较大的图案(例如，缩减2倍、3倍、4倍或更大倍数)。较大图案的缩减的使用可以允许较小的图案化部件尺寸，例如较大的RDL密度、较小的RDL线宽等。较大的图案的缩减还可以允许减小图案化部件的线粗糙度，和减小图案化期间出现工艺缺陷的机会。另外，互连结构76的较小部件尺寸可以允许较小的噪声和较多的电信号有效传输，特别是对于较高频率(例如，大于约2MHz，诸如约5MHz)的信号。因此，通过形成具有附接到多个中介层70的多个集成电路器件50的器件结构110，在每个中介层70上集成半导体器件50之间的电互连可以形成为具有较小部件尺寸并具有改进的工艺可靠性。在一些实施例中，单个集成电路器件(例如，图9中的器件50A)的功能性可以被分离成每个都附接到分离的中介层70的两个或更多的集成电路器件(例如，图15-图16中的器件50C和50D)。
转到图10，根据一些实施例，多个器件封装件100附接到载体115。载体115可以是例如如前述的载体114(参见图6)的载体或材料。图10示出了附接到载体115的两个器件封装件100(标记为100A和100B)，但是在其他实施例中，可以将两个以上器件封装件100附接到载体，并且器件封装件100可以以任何合适的配置或布置被附接。图10所示的实施例包括第一器件封装件100A，第一器件封装件100A包括集成电路器件50A和50B；以及第二器件封装件100B，第二器件封装件100B包括集成电路器件50C和50D。每个器件封装件内的集成电路器件50可以相似或不同。例如，器件封装件100A中的集成电路器件50A可以与器件封装件100B中的集成电路器件50C相似或不同，或者器件封装件100A中的集成电路器件50B可以与器件封装件100B中的集成电路器件50D相似或不同。相似或不同的集成电路器件50的任何组合可以存在于器件封装件100中，并且集成电路器件50的其他配置是可能的。
可以使用例如拾取和放置工具将器件封装件100附接到互连结构76。在一些实施例中，可以在载体115上或在器件封装件100上形成粘合剂层(图10中未示出)以促进附接。在一些实施例中，单个器件封装件100可以具有在大约20mm与大约50mm之间的长度或宽度(例如，图10中所示的LW2)。在一些实施例中，在放置在载体115上之前，器件封装件100可以进行电测试。以这种方式，仅可以附接已知的好的器件封装件100，提高随后形成的器件结构110或封装件结构300的产量。
在图11中，根据一些实施例，在器件封装件100和载体115上形成密封剂113。密封剂113可以是模塑料、环氧树脂等，并且可以通过压缩模制、传递模制等被应用。在一些实施例中，密封剂113可以类似于密封剂112(参见图5)。可以形成密封剂113，使得器件封装件100被密封剂113围绕并覆盖。然后可以固化密封剂113。在一些实施例中，去除(例如，通过CMP)密封剂113的过量的材料，这也可以使结构平坦，从而密封剂113的顶部表面和器件封装件100的顶部表面是水平的。
再分布结构120形成在器件封装件100上方，并且用于在器件封装件100和/或外部器件之间形成电连接。再分布结构120可以包括一个或多个介电层和RDL，该RDL包括形成电连接的通孔和/或迹线。图12所示的再分布结构120是说明性示例，并且可以在再分布结构120中形成更多或更少的介电层和/或RDL。
在一些实施例中，以类似于互连结构76(见图2)的方式形成再分布结构120。例如，可以通过首先在器件封装件100和密封剂113上方形成介电层122来形成再分布结构120。在一些实施例中，介电层122由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等的可以使用光刻技术进行图案化的光敏材料。可以通过旋涂、层压、CVD等或其组合来形成介电层122。然后，图案化介电层122以形成暴露器件结构100的通孔74的开口。可以通过例如根据期望的图案暴露介电层122并执行显影工艺以去除不需要的材料来执行图案化，从而暴露出通孔74。也可以使用诸如使用图案化的掩模和蚀刻的其他技术来图案化介电层122。
晶种层(图12中未示出)形成在介电层122上方和在介电层122中形成的开口中。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和在钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并图案化掩模(图12中未示出)。在一些实施例中，掩模是通过旋涂等形成然后曝光以图案化的光刻胶。图案化形成穿过掩模的开口以暴露晶种层。然后，在掩模的开口中和晶种层的暴露的部分上形成导电材料。可以通过诸如电镀或化学镀等的镀覆来形成导电材料。导电材料可以包括诸如铜、钛、钨、铝、这些的组合等的金属。然后，未在其上形成导电材料的光刻胶和部分晶种层被去除。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。例如通过使用诸如通过湿法或干法蚀刻的可接受的蚀刻工艺，一旦去除了光刻胶，就去除了晶种层的暴露的部分。晶种层的剩余部分和导电材料在再分布结构120内形成RDL 124。
然后，可以在介电层122和RDL124上方形成附加的介电层和附加的RDL，以形成再分布结构120内附加的电连接。可以使用类似于用于形成介电层122和/或RDL124的材料和工艺来形成附加的介电层和附加的RDL。例如，附加的介电层可以在工艺中形成，并且具有类似于介电层122的材料。可以通过每个附加介电层形成开口以暴露下方RDL的至少一部分。可以使用合适的光刻掩模和蚀刻工艺来形成开口，例如以上对于介电层122所描述的那些，尽管可以替代地使用任何合适的工艺。在一些实施例中，附加介电层由光敏聚合物形成，并且可以使用光刻掩模和蚀刻工艺在附加介电层中直接图案化开口。
可以在每个附加的介电层中形成附加的RDL，以在再分布结构120内提供附加的电连接。在一个实施例中，可以使用类似于RDL 124的材料和工艺来形成附加的RDL。例如，用于附加的RDL的期望的图案中可以形成晶种层，并且在晶种层的顶部上放置和图案化光刻胶。然后可以使用例如电镀工艺在光刻胶的图案化开口中形成导电材料。然后可以去除光刻胶并且蚀刻晶种层，形成附加的RDL。可以由多个介电层和多个RDL以这种方式形成再分布结构120。
转到图13，将载体115从结构上剥离，形成器件结构110。在一些实施例中，还可以使用例如锯切或切割工艺分离器件衬底110。由于分离工艺，再分布结构120的外侧壁和密封剂113的外侧壁可以是共面的。
转到图14，示出了根据一些实施例的器件结构110的平面图。图14中示出的器件结构110是代表性的，为了清楚，一些特征未示出。图14的器件结构110示出了使用关于图13描述的思想的特定实施例。例如，器件结构110包括器件封装件100A和器件封装件100B，它们可以与图13中描述的封装件100A或100B相同或不同。图14中示出的器件结构110包括两个器件封装件100A和100B，但是在其他实施例中，器件结构110可以包括三个或更多器件封装件100。器件封装件100可以在器件结构110内具有任何合适的配置或布置。
在一些实施例中，在器件结构110内，不同的器件封装件100可以通过再分布结构120电连接，并且每个器件封装件100内的集成电路器件50可以通过器件封装件100的互连结构76电连接。这在图14中示出。其中，器件封装件100A的集成电路器件50A通过器件封装件100A的互连结构76连接到集成电路器件50B，并且器件封装件100B的集成电路器件50C通过器件封装件100B的互连结构76连接到集成电路器件50D。通过每个互连结构76的一部分76'，在图14中示出了每个器件封装件100内的集成电路器件50之间的连接。示例的部分76'也在图13中示出，尽管部分76'在图13-图14示出的是说明性的，但是可以与所示的不同。如图14所示，器件封装件100A通过再分布结构120电连接到器件封装件100B。器件封装件100之间的连接在图14中通过再分布结构120的一部分120'示出。示例的部分120'也在图13中示出，尽管示例的部分120'在图13-图14中是说明性的，并且可以与所示的不同。
通过在器件结构110中使用互连结构76和再分布结构120两者，器件结构110可以合并具有多个集成电路器件50的多个器件封装件100。由于使用如上所述的多个较小的中介层76，互连结构76的导电迹线(例如，RDL)可以形成为具有较小的部件尺寸，相比于再分布结构120的导电迹线(例如，RDL)。例如，中介层76上的部件可以使用具有较大图案缩减的标线来形成，相比于可用于在再分布结构120上形成部件的图案缩减选项。例如，互连结构76的导电迹线可具有在约0.1μm和约3μm之间的线宽，并且再分布结构120的导电迹线可具有在约1μm和约20μm之间的线宽。在某些情况下，由于互连结构76的特征尺寸较小，互连结构76可以具有比再分布结构120好的高频性能。因此与再分布结构120相比具有更高的性能。因此，器件结构110可允许在使用互连结构76的集成电路器件50之间，改善高频电气通信。因此，高频操作可以是理想的。另外，较低频率的器件封装件100之间的电通信可以是足够的，因此，可以使用再分布结构120而不会对性能造成负面影响。
转到图15至图16，在一些实施例中，单个集成电路器件50的功能可以分离成多个通过器件结构110的再分布层120电连接的集成电路器件50。如说明书性示例，图15示出了表示包括具有多个功能组件51A-D的单个集成电路器件50'的器件封装件100'的示意图。功能组件51A-D可以是例如模块、电路等，或其部分或其组合。所示的功能组件51A-D是说明性的，集成电路器件50可以具有比所描述的更多、更少或不同类型的功能组件。如图15所示，不是在一个器件封装件100'上形成单个的较大面积的集成电路器件50'，而是在两个分离的器件封装件100E和100F上的两个较小面积的集成电路器件50E和50F之间划分集成电路器件50'的功能组件51A-D。如上所述，以这种方式，较小面积的器件封装件100E和100F的部件可以形成为具有比较大面积的器件封装件100'的部件更小的尺寸。因此，通过在器件结构110内的多个器件封装件100上使用多个集成电路器件50，而不是在单个器件封装件100上使用单个集成电路器件50，可以实现较小的部件尺寸的益处。在其他实施例中，单个集成电路器件50的功能可以划分为两个以上的较小集成电路器件50，并且因此，关联的器件结构110可以具有两个以上的器件封装件100。
图16A至图22是根据一些实施例的在形成封装件结构200(参见图22)的工艺期间的中间步骤的截面图。封装件结构200包括电连接到再分布结构220的一侧的一个或多个器件封装件100，以及电连接到再分布结构220的该相同侧的一个或多个电子器件210。在图16A至图18中，器件封装件100被附接到第一载体202，并且电子器件210被附接到形成在第一载体202上的导电焊盘208。在图19至图20中，该结构从第一载体202被移除并且被安装至第二载体222。在图21至图22中，再分布结构220和外部连接件224形成在器件封装件100和电子器件210上方，从而形成封装件结构200。
图16A-图16C示出了根据一些实施例的在将器件封装件100和电子器件210附接到第一载体202之前的器件封装件100、电子器件210和第一载体202。根据一些实施例，图16A示出了在器件封装件100的中介层70上方形成粘合剂206的器件封装件100。器件封装件100可以类似于前述的器件封装件100，例如图9中所描述的。粘合剂206可以是任何合适的粘合剂、环氧树脂、管芯附着膜(DAF)等。
图16B示出了根据一些实施例的电子器件210。电子器件210可以是例如包括一个或多个有源器件和/或一个或多个诸如电容器、电阻器、电感器等的无源器件的半导体器件或其他器件。电子器件210可以是例如集成无源器件(IPD)。在一些实施例中，电子器件210是包括诸如多层陶瓷电容器(MLCC)等电容器的无源器件。在一些实施例中，电子器件210可以是表面安装器件(SMD)等。在一些实施例中，电子器件210可以具有在大约50μm和大约600μm之间的厚度。电子器件210包括一个或多个提供外部组件与电子器件210之间的电连接的连接件212。连接件212可以是例如导电凸块、焊盘、引线、焊球等。
图16C示出了可以是用于后续工艺的合适的支撑结构的第一载体202。第一载体202可以是玻璃载体衬底、陶瓷载体衬底、晶圆、面板等。第一载体202可以是晶圆，从而可以在载体202上同时形成多个封装件。释放层204可以形成在第一载体202上。释放层204可以由基于聚合物的材料形成，其可以从将在后续步骤中形成的上覆结构中与第一载体202一起被去除。在一些实施例中，释放层204是诸如光热转换(LTHC)释放涂层的在加热时失去其粘合特性的基于环氧的热释放材料。在其他实施例中，释放层204可以是当暴露于UV光时失去其粘合特性的紫外线(UV)胶。释放层204可以被配置为液体并且被固化，可以是层压到第一载体202上的层压膜、DAF等。释放层204的顶表面可以是水平的并且可以具有高度的共面性。
仍然参考图16C，可以在释放层204上方形成导电连接件208。导电连接件208可以是导电焊盘、凸块、支柱等，并且随后连接到电子器件210的连接件212。以提供到电子器件210的电连接。在一些实施例中，可以通过在释放层204上方沉积晶种层(未示出)来形成导电连接件208。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层和在钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并图案化光刻胶。可以通过旋涂等形成光刻胶，并且可以将光刻胶曝光以图案化。光刻胶的图案对应于导电通孔。图案形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中和晶种层的暴露部分上。可以通过诸如电镀或化学镀等镀覆来形成导电材料。导电材料可以包括例如铜、钛、钨、铝、其组合等金属。未在其上形成导电材料的光刻胶和部分晶种层被去除。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。例如通过使用诸如通过湿法或干法蚀刻的可接受的蚀刻工艺，一旦去除了光刻胶，就去除了晶种层的暴露的部分。晶种层的剩余部分和导电材料形成导电连接件208。
转到图17，根据一些实施例，器件封装件100和电子器件210被附接到第一载体202。图17示出了单个器件封装件100和附接到第一载体202的两个电子器件210，但是在其他实施例中可以附接一个以上的器件封装件或更多或更少的电子器件210。附接到第一载体202的电子器件210可以是类似的电子器件或者可以是不同的电子器件。
可以使用例如拾取和放置工具，将器件封装件100和电子器件210放置在第一载体202上。器件封装件100可以通过粘合剂206附接到第一载体202上的释放层204。电子器件210可以通过导电连接件208附接到第一载体202。在一些实施例中，电子器件210可以被附接到导电连接件208，例如通过依序将电子器件210的连接件212浸入焊料和/或助焊剂材料中，然后使用拾取和放置工具以将连接件212与导电连接件208对准。在一些实施例中，在放置电子器件210之前，可以先将焊料材料(例如，焊膏)应用到导电连接件208。在一些情况下，在放置电子器件210之后，可以执行回流以将连接件212结合到导电连接件208。
在某些情况下，通过以这种方式将电子器件210附接到第一载体202，电子器件210可以在最终封装件结构200(参见图22)中更靠近器件封装件100定位。例如，在一些实施例中，电子器件210可以通过在约300μm和约30,000μm之间的距离D与器件封装件100分离。通过更靠近器件封装件100定位电子器件，可以减小电阻，并且可以改善器件性能，特别是对于在更高频率下的操作。另外，通过将电子器件210附接到第一载体，可以在相同封装件结构200中使用具有多个厚度的多个电子器件210，而不会增加封装件结构200的整体厚度。还可以通过密封剂214(参见图18)保护电子器件210以下方式，这可以提高器件的可靠性。
在图18中，密封剂214形成在结构的各个部件上。密封剂214可以是模塑料、环氧树脂等，并且可以通过压缩模制、传递模制等被应用。密封剂214可以形成在器件封装件100和电子器件210上方，从而器件封装件100和电子器件210被密封剂214围绕并覆盖。然后可以固化密封剂214。在一些实施例中，去除(例如，通过CMP)密封剂214的过量的材料，这也可以使结构的顶部平坦，从而密封剂214的顶部表面和器件封装件100的顶部表面是水平的。
在图19中，执行载体分离，以将第一载体202从结构脱离(去键合)，然后将该结构附接到第二载体222。根据一些实施例，分离包括在释放层204上投射诸如激光或紫外(UV)光的光，从而释放层204在光的热量下分解，并且可以去除第一载体202。然后将该结构翻转并附接到第二载体222。第二载体222可以类似于第一载体202，例如包括玻璃载体衬底、陶瓷载体衬底、晶圆、面板等。释放层223可以形成在第二载体222上，并且该结构可以附接到释放层223。释放层223可以是例如DAF等，或者可以类似于上述的释放层204。
在图20中，根据一些实施例，在结构的底部上执行平坦化工艺。平坦化工艺可以是例如CMP。在一些实施例中，平坦化工艺可以去除粘合剂206并且可以暴露器件封装件100的导电连接件208和通孔74。在一些情况下，平坦化工艺还可以平坦化结构，从而密封剂214的底表面和器件封装件100的底表面和底表面是水平的。
在图21中，根据一些实施例，再分布结构220形成在结构的底部上方。再分布结构220在电子器件210、器件封装件100和外部组件之间提供电互连。再分布结构220包括介电层226、228和230，并且包括金属化图案232和234。金属化图案也可以被称为再分布层(RDL)或再分布线。再分布结构220被示为具有两层金属化图案的示例。可以在再分布结构220中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和过程。
在图21中，通过通孔74和导电连接件208，介电层226沉积在密封剂214上。在一些实施例中，介电层226由诸如PBO、聚酰亚胺、BCB等可以使用光刻掩模来图案化的光敏材料形成。可以通过旋涂、层压、CVD等或其组合形成介电层226。然后图案化介电层226。图案化形成暴露部分通孔74和导电连接件208开口。可以通过可接受的工艺来形成图案，例如通过当介电层226是光敏材料时将介电层226暴光，或通过使用诸如各向异性蚀刻的蚀刻。如果介电层226是光敏材料，则介电层226可以在曝光之后显影。
然后，根据一些实施例形成金属化图案232。金属化图案232包括在介电层226的主表面上并沿着介电层226的主表面延伸的线部分(也称为导电线)。金属化图案232还包括延伸穿过介电层226以物理和电气耦合通孔74与导电连接件208的通孔部分(也称为导电通孔)。作为形成金属化图案232的示例，晶种层形成在介电层226上方和延伸穿过介电层226的开口中。在一些实施例中，晶种层是金属层，可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和在钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。可以通过旋涂等形成光刻胶，并且可以将光刻胶曝光用于图案化。光刻胶的图案对应于金属化图案232。图案化形成穿过光刻胶的开口以暴露晶种层。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等镀覆来形成导电材料。导电材料可以包括诸如铜、钛、钨、铝等金属。导电材料和晶种层的下面部分的组合形成金属化图案232。去除其上未形成导电材料的光刻胶和部分晶种层。可以通过例如使用氧等离子体等可接受的灰化或剥离工艺去除光刻胶。例如通过使用诸如通过湿法或干法蚀刻的可接受的蚀刻工艺，一旦去除了光刻胶，就去除了晶种层的暴露部分。
在形成金属化图案232之后，介电层228沉积在金属化图案232和介电层226上。介电层228可以以类似于介电层226的方式形成和图案化，并且可以由类似于介电层226的材料形成。
然后，根据一些实施例形成金属化图案234。金属化图案234包括在介电层228的主表面上并沿着介电层228的主表面延伸的线部分。金属化图案234还包括延伸穿过介电层228以物理和电气耦合金属化图案232的通孔部分。可以用与金属化图案232相似的方式和类似的材料形成金属化图案234。在一些实施例中，金属化图案234具有与金属化图案232不同的尺寸。例如，金属化图案234的导线和/或通孔可以比金属化图案232的导线和/或通孔更宽或更厚。此外，金属化图案234可以形成为比金属化图案232更大的间距。
介电层230沉积在金属化图案234和介电层228上。可以用类似于介电层228的方式形成介电层230，并且可以由与介电层226相同的材料形成。介电层230是再分布结构220的最顶层介电层。因此，再分布结构220的所有金属化图案(例如，金属化图案232和234)设置在介电层230和器件封装件100之间。此外，再分布结构220的所有中间介电层(例如，介电层226和228)设置在介电层230和器件封装件100之间。
在一些实施例中，UBM 236形成为再分布结构220的外部连接。UBM236可以包括在介电层230的主表面上并沿着介电层230的主表面延伸的导电部分。UBM236还包括延伸穿过介电层230以物理和电气连接至金属化图案234的导电通孔。UBM236可以由与金属化图案232相同的材料或不同的材料形成。例如，UBM 236可以包括铜或铜合金。但是，也可以包括诸如钛、镍、钯、银、金、铝、它们的组合以及它们的多层的其他金属。可以使用溅射、电镀等形成UBM 236。在一些实施例中，UBM 236具有与金属化图案232或234不同的尺寸。
在某些情况下，通过形成所描述的再分布结构220，可以将多个电子器件210连接到至少一个器件封装件100，而无需使用单独的中介层或衬底。另外，再分布结构220的使用允许封装件包括组件(例如，器件封装件100或电子器件210)，而无需额外的结合步骤(例如，将器件封装件100结合到中介层的摩擦步骤)、底部填充的沉积或其他相关工艺步骤。以这种方式，可以减少用于形成包装的成本和工艺步骤的数量。另外，在工艺期间使用两个载体(例如202和222)可以减少工艺期间结构的翘曲量。
在图22中，外部连接件224形成在UBM 138上。外部连接件224可以是球栅阵列(BGA)连接件、焊球、金属柱，可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍化学镀钯与浸金技术(ENEPIG)形成的凸块等。外部连接件224可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合的导电材料。在一些实施例中，通过首先经由蒸发、电镀、印刷、焊料转移、焊球放置等形成焊料层而形成外部连接件224。一旦在结构上形成焊料层，就可以执行回流以将材料成形为期望的凸块形状。在另一个实施例中，外部连接件224包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属盖层。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，并且可以通过镀覆工艺形成。
仍然参考图22，执行载体分离以将第二载体222从结构脱离(分离)，从而形成封装件结构200。根据一些实施例，分离包括在释放层224上投射诸如激光或紫外(UV)光的光，从而释放层204在光的热量下分解，并且可以去除第一载体222。然后可以将结构翻转并放置在胶带(未示出)上。然后可以分离结构从以形成封装件结构200。可以通过锯切、切割等分离。由于分离工艺，再分布结构220和密封剂214的边缘可以是共面的。
以这种方式，可以用具有不同厚度的电子器件210形成封装件结构200，而不增加封装件结构200的整体厚度。另外，通过用本文所述的再分布结构220形成封装件结构200，可以不使用额外的中介层或衬底形成封装件结构200，这可以减少制造成本并且减少工艺步骤的数量。
图23A至图28是根据一些实施例的在用于形成封装件结构300(参见图28)的工艺期间的中间步骤的截面图。除了不使用粘合剂206和导电连接件208之外，封装件结构300类似于封装件结构200。以这种方式，用于形成封装件结构300的工艺步骤的数量可以少于用于形成封装件结构300的工艺步骤的数量。封装件结构300包括电连接到再分布结构220的一侧的一个或多个器件结构110，以及电连接到再分布结构220的同一侧的一个或多个电子器件210。虽然图23A至图28中描述的封装件结构300使用器件结构110(参见图14)示出，但是在其他实施例中，封装件结构300可以使用器件封装件100(参见图9)代替或器件结构110，或者封装件结构300除了使用器件结构110之外还可以使用器件封装100(参见图9)。在图23A至图25中，器件结构110和电子器件210附接到第一载体202。在图26中，该结构从第一载体202移除，并安装至第二载体222。在图27至图28中，再分布结构220和外部连接件224形成在器件结构110和电子器件210上方，以形成封装件结构300。
图23A-图23C示出了根据一些实施例的在将器件结构110和电子器件210附接到第一载体202之前的器件结构110、电子器件210和第一载体202。图23A示出了器件结构110，器件结构110可以类似于先前描述的器件结构110，诸如在图14中所描述的。图16B示出了电子器件210，电子器件210可以类似于先前描述的电子器件210。电子器件210包括在外部组件和电子器件210之间提供电连接的一个或多个连接件212。图16C示出了第一载体202，第一载体202可以是用于后续加工的合适的支撑结构。第一载体202可以类似于先前描述的第一载体202。释放层204可以形成在第一载体202上，释放层204可以类似于先前描述的释放层204。
转到图24，根据一些实施例，器件结构110和电子器件210附接到第一载体202。图24示出了单个器件结构110和附接到第一载体202的两个电子器件210，但是，在其他实施例中，可以附接一个或多个器件结构110、一个或多个器件封装件100、和/或一个或多个电子器件210。附接到第一载体202的电子器件210可以是相似的电子器件，或者可以是不同的电子器件，并且可以具有不同的厚度，如图24所示。使用例如拾取和放置工具，器件结构110和电子器件210可以放置在第一载体上。
在某些情况下，通过以这种方式将电子器件210附接到第一载体202，在最终封装件结构300(参见图28)中，电子器件210可以更靠近器件结构110定位。通过将电子器件更靠近器件结构110定位，可以减小电阻，并且可以改善器件性能，特别是对于在更高频率下的操作。另外，通过将电子器件210附接到第一载体，可以使用具有不同尺寸或不同高度的电子器件210，而不增加最终封装件结构300的整体厚度。电子器件210也可以由密封剂214(参见图25)保护，这可以提高器件的可靠性。
在图25中，密封剂214形成在结构的各种部件上。密封剂214可以是模塑料、环氧树脂等，并且可以通过压缩模制、传递模制等被应用。密封剂214可以形成在器件结构110和电子器件210上方，从而器件结构110和电子器件210被密封剂214围绕和覆盖。然后可以固化密封剂214。在一些实施例中，去除(例如，通过CMP)密封剂214的过量的材料，这也可以使结构的顶部平坦，从而密封剂214的顶部表面和器件结构110的顶部表面是水平的。
在图26中，执行载体分离，以将第一载体202从结构脱离(分离)，然后将该结构附接到第二载体222。根据一些实施例，分离包括在释放层204上投射诸如激光或紫外(UV)光的光，从而释放层204在光的热量下分解，并且可以去除第一载体202。然后将结构翻转并附接到第二载体222。第二载体222可以类似于先前描述的第一载体202或第二载体222。释放层224可以形成在第二载体222上，并且该结构可以附接到释放层224。释放层224可以是例如DAF等，并且可以类似于上述释放层224。
在图27中，根据一些实施例，再分布结构220形成在结构的底部上方。再分布结构220在电子器件210、器件结构110和外部组件之间提供电互连。再分布结构220可以类似于先前在图21中描述的再分布结构220，并且可以用类似的方式形成。例如，图27所示的再分布结构220包括介电层226、228和230，并包括金属化图案232和234。可以在再分布结构220中形成更多或更少的介电层和金属化图案。在一些实施例中，形成UBM236，用于到再分布结构220的外部连接，这可以类似于先前描述的UBM236。
在某些情况下，通过形成所描述的再分布结构220，可以将多个电子器件210连接到至少一个器件结构110，而无需使用单独的中介层或衬底。另外，再分布结构220的使用允许封装件包括组件(例如，器件结构110、器件封装件100、和/或电子器件210)而无需额外的结合步骤(例如，结合器件结构110或器件封装件100至中介层)、底部填充物的沉积、或其他相关工艺步骤。以这种方式，可以减少用于形成封装件的成本和加工步骤的数量。另外，在加工期间使用两个载体(例如202和222)可以减少加工期间结构的翘曲量。
在图28中，外部连接件224形成在UBM 236上。外部连接件224可以类似于前述的外部连接件224。仍然参考图28，执行载体分离，以将第二载体222从结构脱离(分离)，形成封装件结构300。根据一些实施例，分离包括在释放层224上投射诸如激光或紫外(UV)光的光，从而释放层224在光的热量下分解，并且可以去除第二载体222。然后可以将结构翻转并放置在胶带(未显示)上。然后可以将结构分离以形成封装件结构300。可以通过锯切、切割等分离。由于分离工艺，再分布结构220和密封剂214的边缘可以是共面的。
以这种方式，封装件结构300可以由具有不同厚度的电子器件210形成，而不增加封装件结构300的整体厚度。另外，通过形成如本文描述的具有再分布结构220的封装件结构300，可以不使用额外的中介层或衬底形成封装件结构300，这可以降低制造成本并减少加工步骤。另外，可以不包括导电连接件208或粘合剂206形成封装件结构300，进一步降低加工成本和步骤。
转到图29，根据一些实施例示出了包装结构400。封装件结构400包括通过连接件404结合到IC衬底402的器件结构110。器件结构110可以类似于先前描述的器件结构，例如图13中所描述的。IC衬底402可以是体半导体衬底、SOI衬底、多层半导体衬底等。IC衬底402的半导体材料可以是硅，锗，包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟的化合物半导，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP、其组合的合金半导体等。也可以使用例如多层或梯度衬底的其他衬底。IC衬底402可以是掺杂的或不掺杂的。诸如晶体管、电容器、电阻器、二极管等的器件可以形成在IC衬底402的表面和/或表面上。例如，IC衬底402可以是已在其中形成集成电路的半导体衬底、芯片、管芯等，并通过连接件404电连接到器件结构110。在一些实施例中，IC衬底402是基于诸如玻璃纤维增强树脂芯的绝缘芯。例如，芯材料可以是诸如FR4的玻璃纤维树脂、BT树脂、其他PCB材料或薄膜、组合等。诸如ABF的堆积膜或其他层压制品可被用于IC衬底402。
在一些实施例中，连接件404形成在器件结构110的再分布结构120上，然后将器件结构110放置在IC衬底402上，使得连接件404与IC衬底402上的相应的导电部件进行电气和物理连接。连接件404可以类似于先前描述的连接件224，并且可以用类似的方式形成。在一些情况下，在放置器件结构110之后，可以执行回流，以将连接件404结合到IC衬底402上的相应的导电部件。在将器件结构110结合到IC衬底402之后，可以在器件结构110和IC衬底402之间沉积底部填充物406。
在一些实施例中，一个或多个电子器件(图29中未示出)也可以连接到IC衬底402。电子器件可以类似于先前描述的电子器件210。电子器件可以连接到IC衬底402的一侧或两侧。例如，电子器件可以附接到IC衬底402的与器件结构110相同的一侧上。
实施例可以实现进步。通过形成具有通过再分布结构连接的多个器件封装件的器件结构，可以减小每个器件封装件的尺寸，从而允许形成具有更精细部件的器件封装件。例如，每个器件封装件的中介层内的金属化可以形成为具有更大的密度和更小的线宽，这可以提高在更高频率下的性能。在一些情况下，单个集成电路器件的功能可以被分为多个器件封装件，由于每个器件封装件的尺寸较小，这可以允许如所描述的改进金属化和改善性能。在一些情况下，在形成器件结构之前，可以对集成电路器件进行单独的电测试，这可以提高良率。通过使用双载体工艺形成封装件结构，可以将具有不同厚度的例如SMD的电子组件在相同的封装件结构内合并。另外，可以使用再分布结构代替封装件结构内的中介层，这可以减少成本和加工步骤。
在一个实施例中，一种方法包括形成器件结构，形成器件结构包括：将第一管芯连接到第一中介层，将第二管芯连接到第二中介层，以及在第一中介层和第二中介层上方形成第一再分布结构，其中，第一再分布结构将第一中介层电连接到第二中介层，以及形成封装件结构，形成封装件结构包括将第一表面安装器件(SMD)和器件结构附接到第一载体，用第一密封剂密封第一SMD和器件结构，以形成具有顶表面和底表面的密封结构，将密封结构的顶表面附接到第二载体，以及在密封结构的底表面上方形成第二再分布结构，其中，所述第二再分布结构电连接第一个SMD和器件结构。在一个实施例中，形成封装件结构还包括将第二SMD附接到第一载体，其中，第二SMD具有与第一SMD不同的厚度。在一个实施例中，该方法还包括平坦化密封结构，其中，在平坦化封装件结构之后，第一管芯的顶表面和第一密封剂的顶表面是水平的。在一个实施例中，形成器件结构还包括用第二密封剂密封第一中介层和第二中介层，其中，第一再分布结构在第二密封剂上方延伸。在一个实施例中，第一SMD的厚度小于封装件结构的厚度。在一个实施例中，该方法还包括在将第一管芯连接到第一中介层之后，在第一中介层上方形成第一再分布结构之前，电测试第一管芯。在一个实施例中，第二再分布结构的侧壁与密封结构的侧壁共面。在一个实施例中，该方法还包括在第二再分布结构上形成外部连接件。
在一个实施例中，一种方法包括：将半导体器件附接到中介层结构；将中介层结构附接到第一载体衬底，将集成无源器件附接到第一载体衬底；在半导体器件和集成无源器件上方形成密封剂。分离第一载体衬底，将密封剂和半导体器件附接到第二载体衬底，在密封剂、中介层结构和集成无源器件上形成第一再分布结构，其中，第一再分布结构接触中介层结构和集成无源器件，以及在第一个再分布结构上形成外部连接件。在一个实施例中，该方法还包括在中介层结构上形成第二再分布结构，其中，第二再分布结构附接到第一载体衬底。在一个实施例中，该方法还包括在中介层结构上形成互连结构，其中，半导体器件附接到互连结构。在一个实施例中，该方法还包括在将中介层结构附接到第一载体衬底之前，在半导体器件上方形成密封剂。在一个实施例中，该方法还包括在第一载体衬底上形成导电连接件，其中，集成无源器件附接到第一载体衬底。在一个实施例中，将中介层结构附接到第一载体衬底包括在中介层结构上形成粘合剂，以及使用粘合剂将中介层结构附接到第一载体衬底。在一个实施例中，通过密封剂将集成无源器件从中介层结构分离。
在一个实施例中，一种封装件包括器件衬底和附接到器件衬底的第一侧的器件结构，器件结构包括第一中介层、第二中介层、附接到第一中介层的第一半导体器件、附接到第二中介层的的第二半导体器件、以及连接到第一中介层和第二中介层的第一再分布结构。在一个实施例中，器件衬底包括集成电路。在一个实施例中，器件衬底是第二再分布结构。在一个实施例中，器件结构还包括附接到器件衬底的第一侧的表面安装器件(SMD)。在一个实施例中，封装件还包括覆盖SMD并且围绕器件结构的密封剂材料。
上面论述了多个实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或修改其他用于执行与本文所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员还应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种形成封装件的方法，包括：
形成器件结构，包括：
将第一管芯连接到第一中介层；
将第二管芯连接至第二中介层；和
在所述第一中介层和所述第二中介层上方形成第一再分布结构，其中，所述第一再分布结构将所述第一中介层电连接到所述第二中介层；以及
形成封装件结构，包括：
将第一表面安装器件和所述器件结构附接到第一载体；
用第一密封剂密封所述第一表面安装器件和所述器件结构，以形成具有顶表面和底表面的密封结构；
将所述密封结构的顶表面附接到第二载体；和
在所述密封结构的底表面上方形成第二再分布结构，其中，所述第二再分布结构将所述第一表面安装器件和所述器件结构电连接。
2.根据权利要求1所述的方法，其中，形成所述封装件结构还包括将第二表面安装器件附接到所述第一载体，其中，所述第二表面安装器件具有与所述第一表面安装器件不同的厚度。
3.根据权利要求1所述的方法，还包括平坦化所述密封结构，其中，在平坦化所述密封结构之后，所述第一管芯的顶表面和所述第一密封剂的顶表面是水平的。
4.根据权利要求1所述的方法，其中，形成器件结构还包括用第二密封剂密封所述第一中介层和所述第二中介层，其中，所述第一再分布结构在所述第二密封剂上方延伸。
5.根据权利要求1所述的方法，其中，所述第一表面安装器件的厚度小于所述密封结构的厚度。
6.根据权利要求1所述的方法，还包括在将所述第一管芯连接到所述第一中介层之后，在所述第一中介层上方形成第一再分布结构之前，电测试所述第一管芯。
7.根据权利要求1所述的方法，其中，所述第二再分布结构的侧壁与所述密封结构的侧壁共面。
8.根据权利要求1所述的方法，其中，还包括在所述第二再分布结构上形成外部连接件。
9.一种形成封装件的方法，包括：
将多个半导体器件附接到中介层结构；
将所述中介层结构附接到第一载体衬底；
将多个集成无源器件附接到所述第一载体衬底；
在所述多个半导体器件和所述多个集成无源器件上方形成密封剂；
分离所述第一载体衬底；
将所述密封剂和所述多个半导体器件附接到第二载体衬底；
在所述密封剂、所述中介层结构和所述多个集成无源器件上形成第一再分布结构，其中，所述第一再分布结构接触所述中介层结构和所述多个集成无源器件；以及
在所述第一再分布结构上形成多个外部连接件。
10.一种封装件，包括：
器件衬底；以及
器件结构，附接到所述器件衬底的第一侧，所述器件结构包括：
第一中介层；
第二中介层；
多个第一半导体器件，附接到所述第一中介层；
多个第二半导体器件，附接到所述第二中介层；和
第一再分布结构，连接到所述第一中介层和所述第二中介层。
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