CN109427597A - 半导体封装件中的导电通孔及其形成方法 - Google Patents

半导体封装件中的导电通孔及其形成方法 Download PDF

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Publication number
CN109427597A
CN109427597A CN201810082747.4A CN201810082747A CN109427597A CN 109427597 A CN109427597 A CN 109427597A CN 201810082747 A CN201810082747 A CN 201810082747A CN 109427597 A CN109427597 A CN 109427597A
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China
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layer
substrate
insulating layer
tube core
opening
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CN109427597B (zh
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黄松辉
张宏宾
邱绍玲
侯上勇
李宛谕
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种实施例方法包括将第一管芯接合至中介层的第一侧，中介层包括衬底；在将第一管芯接合至中介层的第一侧之后，在中介层的与第一侧相对的第二侧上沉积第一绝缘层；图案化穿过衬底和第一绝缘层的开口；以及在第一绝缘层上方并沿着开口的侧壁和横向表面沉积第二绝缘层。第二绝缘层包括硅。该方法还包括去除第二绝缘层的横向部分以在开口的侧壁上限定侧壁间隔件并且在开口中形成通孔，其中，通孔电连接至第一管芯。本发明实施例涉及半导体封装件中的导电通孔及其形成方法。

Description

半导体封装件中的导电通孔及其形成方法
技术领域
本发明实施例涉及半导体封装件中的导电通孔及其形成方法。
背景技术
随着集成电路(IC)的发展，由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体产业已经经历了快速增长。在大多数情况下，集成密度的这种改进来自最小部件尺寸的不断减小，这允许将更多的组件集成到给定区域内。
这些集成改进本质上是二维的(2D)，因为集成组件占据的区域基本上位于半导体晶圆的表面上。集成电路的密度的增加和面积的相应减小通常超过了将集成电路芯片直接接合到衬底上的能力。中介层已经用于将来自芯片的球接触区重新分配到中介层的更大区域。此外，中介层已经允许包括多个芯片的三维(3D)封装件。也已经开发其他封装件来接合于3D的各个方面。
发明内容
根据本发明的一些实施例，提供了一种形成封装件的方法，包括：将第一管芯接合至中介层的第一侧，所述中介层层包括衬底；在所述中介层的与所述第一侧相对的第二侧上沉积第一绝缘层；穿过所述衬底和所述第一绝缘层图案化开口；在所述第一绝缘层上方并且沿着所述开口的侧壁和横向表面沉积第二绝缘层，所述第二绝缘层包括硅；去除所述第二绝缘层的横向部分以在所述开口的侧壁上限定侧壁间隔件；以及在所述开口中形成通孔，其中，所述通孔电连接至所述第一管芯。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：将第一管芯和第二管芯接合至中介层，所述中介层包括：再分布结构，包括将所述第一管芯电连接至所述第二管芯的一个或多个金属化图案；以及衬底，位于所述再分布结构的与所述第一管芯和所述第二管芯相对的一侧上；在所述衬底的与所述再分布结构相对的表面上沉积第一含硅绝缘层；延伸穿过所述第一含硅绝缘层和所述衬底图案化第一开口，所述第一开口暴露所述一个或多个金属化图案的第一金属化图案；沿着所述第一开口的侧壁形成侧壁间隔件，所述侧壁间隔件包括含硅绝缘材料；形成延伸穿过所述第一开口并电连接至所述第一金属化图案的电连接件；以及使用所述电连接件将封装件衬底接合至所述中介层。
根据本发明的又一些实施例，还提供了一种封装件，包括：第一管芯，所述第一管芯接合至中介层，所述中介层包括：金属化图案，电连接至所述第一管芯；以及衬底，位于所述金属化图案的与所述第一管芯相对的一侧；含硅绝缘层，位于所述衬底的与所述金属化图案相对的表面上；聚合物层，位于所述含硅绝缘层的与所述衬底相对的一侧上；通孔，延伸穿过所述聚合物层、所述含硅绝缘层和所述衬底至所述金属化图案；以及含硅侧壁间隔件，位于所述通孔和所述衬底之间，所述含硅侧壁间隔件还设置在所述通孔和所述含硅绝缘层之间。
附图说明
当接合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图17、图18A、图18B和图19至图21示出根据一些实施例的制造半导体器件封装件的中间阶段的截面图和顶视图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
各个实施例包括一种器件封装件，其中，该器件封装件包括接合至中介层的一个或多个半导体芯片以及接合至中介层的与一个或多个半导体芯片相对的一侧的封装件衬底。在一些实施例中，器件封装件可以称为衬底上晶圆上芯片(CoWoS)超薄夹层(UTS)封装件。中介层在一个或多个半导体芯片与封装件衬底之间提供电路由。例如，中介层可以包括设置在半导体衬底上的再分布结构(例如，包括设置在一个或多个绝缘层中的导线和/或导电通孔)。再分布结构提供至/来自一个或多个半导体芯片的电路由。导电通孔可以延伸穿过衬底并且电连接至再分布结构的导电部件。在一些实施例中，焊料区设置在导电通孔上以提供用于接合至封装件衬底的电连接件(例如，微凸块(μ凸块))。
为了实现小的封装件轮廓，可以在制造期间减薄中介层的半导体衬底。由于半导体衬底的薄度，延伸穿过半导体衬底的导电通孔在器件封装件的热处理期间(例如，可靠性/应力测试、回流/接合至封装件衬底)变形(例如，分层)的风险增加。各个实施例在导电通孔的侧壁上提供绝缘间隔件以改善导电通孔的刚性并减少制造缺陷。在一些实施例中，绝缘间隔件可以将导电通孔与中介层的半导体衬底绝缘，并且提供增加的结构支撑。例如，绝缘间隔件可以是诸如氮化硅、氧化硅、氮氧化硅等的含硅材料。与其他绝缘材料(例如聚合物)相比，已经观察到由上述材料制成的间隔件提供了改进的结构支撑。
将相对于特定的上下文来描述实施例，即使用衬底上晶圆上芯片(CoWoS)处理的管芯-中介层-衬底堆叠的封装件。然而，其他实施例也可以应用于诸如管芯-管芯-衬底堆叠的封装件的其他封装件，以及其他处理。本文讨论的实施例是为了提供实例以能够实现或使用本发明的主题，并且本领域普通技术人员将容易地理解可以对本发明作出改进，同时保持在不同实施例的预期范围内。在以下附图中，相同的参考标号和字符表示相同的组件。虽然方法实施例可以描述为以特定的顺序实施，但是也可以以任何合理的顺序来实施其他方法实施例。
图1示出形成一个或多个管芯68。管芯68的主体60可以包括任何数量的管芯、衬底、晶体管、有源器件、无源器件等。在实施例中，主体60可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。主体60的半导体材料可以是硅、锗、包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或它们的组合。还可以使用诸如多层衬底或梯度衬底的其他衬底。主体60可以是掺杂的或未掺杂的。可以在有源表面62中和/或上形成诸如晶体管、电容器、电阻器、二极管等的器件。
在有源表面62上形成包括一个或多个介电层和一个或多个相应的金属化图案的互连结构64。介电层中的金属化图案可以诸如通过使用通孔和/或迹线在器件之间路由电信号，并且还可以包括诸如电容器、电阻器、电感器等的各种电子器件。可以互连各种器件和金属化图案以实施一个或多个功能。功能可以包括存储器结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。额外地，可以在互连结构64中和/或上形成诸如导电柱(例如，包括诸如铜的金属)的管芯连接件66以提供至电路和器件的外部电连接。在一些实施例中，管芯连接件66从互连结构64突出以形成柱结构，当将管芯68接合至其他结构时要使用该柱结构。本领域的普通技术人员将会理解，提供上述实例是为了说明的目的。可以适当使用其他电路以用于给定应用。
更特别地，可以在互连结构64中形成金属间介电(IMD)层。例如，可以通过本领域已知的任何合适的方法(诸如，旋涂、化学气相沉积(CVD)、等离子体增强的CVD(PECVD)、高密度等离子体化学气相沉积(HDP-CVD)等)由低K介电材料(诸如，未掺杂的硅酸盐玻璃(USG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成IMD层。例如，通过使用光刻技术在IMD层上沉积并图案化光刻胶材料以暴露IMD层的将变为金属化图案的部分，可以在IMD层中形成金属化图案。诸如各向异性干蚀刻工艺的蚀刻工艺可用于在IMD层中创建与IMD层的暴露部分相对应的凹槽和/或开口。凹槽和/或开口可以内衬有扩散阻挡层并填充有导电材料。扩散阻挡层可以包括通过原子层沉积(ALD)等沉积的一层或多层氮化钽、钽、氮化钛、钛、钴钨等或它们的组合。金属化图案的导电材料可以包括通过CVD、物理气相沉积(PVD)等沉积的铜、铝、钨、银及它们的组合等。诸如通过使用化学机械抛光(CMP)，可以去除IMD层上的任何多余的扩散阻挡层和/或导电材料。
在图2中，将包括互连结构64的主体60分割成单独的管芯68。典型地，管芯68包括诸如器件和金属化图案的相同的电路，但是管芯可以具有不同的电路。分割可以包括锯切、切割等。
每个管芯68可以包括一个或多个逻辑管芯(例如，中央处理单元、图形处理单元、片上系统、现场可编程栅极阵列(FPGA)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、功率管理管芯(例如，功率管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等，或它们的组合。此外，在一些实施例中，管芯68可以具有不同的尺寸(例如，不同的高度和/或表面积)，并且在其他实施例中，管芯68可以具有相同的尺寸(例如，相同的高度和/或表面积)。
图3示出形成组件96(参见图21)的第一侧。在处理期间，衬底70包括一个或多个组件96。组件96可以是中介层或另一管芯。衬底70可以是晶圆。衬底70可以包括块状半导体衬底、SOI衬底、多层半导体衬底等。衬底70的半导体材料可以是硅、锗、包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或它们的组合。还可以使用诸如多层衬底或梯度衬底的其他衬底。衬底70可以是掺杂的或未掺杂的。可以在衬底70的第一表面72中和/或上形成诸如晶体管、电容器、电阻器、二极管等的器件，其中，第一表面还可以称为有源表面。在组件96是中介层的实施例中，组件96通常将不包括位于其中的有源器件，但是中介层可以包括形成在第一表面72中和/或上的无源器件。
再分布结构76形成在衬底70的第一表面72上方，并且用于电连接集成电路器件(如果存在)和/或外部器件。再分布结构76可以包括一个或多个介电层和位于介电层中的相应的金属化图案。金属化图案可以包括通孔和/或迹线以互连任何器件和/或至外部器件。金属化图案有时称为再分布线(RDL)。介电层可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、诸如PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等的低K介电材料。可以通过诸如旋涂、CVD、PECVD、HDP-CVD等的本领域已知的任何合适的方法沉积介电层。例如，通过使用光刻技术在介电层上沉积并图案化光刻胶材料以暴露介电层的将变为金属化图案的部分，可以在介电层中形成金属化图案。诸如各向异性干蚀刻工艺的蚀刻工艺可用于在介电层中创建与介电层的暴露部分相对应的凹槽和/或开口。凹槽和/或开口可以内衬有扩散阻挡层并填充有导电材料。扩散阻挡层可以包括通过ALD等沉积的TaN、Ta、TiN、Ti、CoW等的一层或多层，并且导电材料可以包括通过CVD、PVD、镀工艺等沉积的铜、铝、钨、银和它们的组合等。诸如通过使用CMP，可以去除介电层上的任何多余的扩散阻挡层和/或导电材料。
在导电焊盘上的再分布结构76的顶面处形成电连接件77/78。在一些实施例中，导电焊盘包括凸块下金属(UBM)。在所示实施例中，在再分布结构76的介电层的开口中形成焊盘。在另一实施例中，焊盘(UBM)可以延伸穿过再分布结构76的介电层的开口并且还延伸跨过再分布结构76的顶面。作为形成焊盘的实例，至少在再分布结构76的介电层中的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其中，该金属层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。例如，可以使用PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。可通过旋涂等形成光刻胶并且可将光刻胶暴露于光从而用于图案化。光刻胶的图案对应于焊盘。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中且在晶种层的暴露部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘。在不同地形成焊盘的实施例中，可以利用多个光刻胶和图案化步骤。
在一些实施例中，电连接件77/78包括具有金属帽层78的金属柱77，金属帽层78可以是位于金属柱77上方的焊料帽。包括柱77和帽层78的电连接件77/78有时称为微凸块77/78。在一些实施例中，金属柱77包括诸如铜、铝、金、镍、钯等或它们的组合的导电材料，并且可以通过溅射、印刷、电镀、化学镀、CVD等形成。金属柱77可以不含焊料并且具有大致垂直的侧壁。在一些实施例中，在金属柱77的顶部上形成金属帽层78。金属帽层78可以包括镍、锡、锡铅、金、铜、银、钯、铟、镍钯金、镍金等或它们的组合并且可以通过镀工艺形成。
在另一实施例中，电连接件77/78不包括金属柱，并且是焊料球和/或凸块，诸如由可控坍塌芯片连接件(C4)、化学镀镍浸金(ENIG)、化学镍镀钯浸金技术(ENEPIG)形成的凸块等。在这个实施例中，凸块电连接件77/78可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在这个实施例中，通过首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等合适的方法形成焊料层来形成导电连接件77/78。一旦已经在结构上形成焊料层，就可以实施回流，以将材料成形为期望的凸块形状。
在图4中，例如通过电连接件77/78和管芯上的金属柱79以形成导电接合件91的方式通过倒装芯片接合将管芯68和管芯88附接至组件96的第一侧。金属柱79可以类似于金属柱77，并且在此不重复描述。例如，使用拾取和放置工具可以将管芯68和管芯88放置到电连接件77/78上。在一些实施例中，在管芯68和管芯88的金属柱77(如图3所示)、金属柱79上或两者上形成金属帽层78。
可以通过与上面参考管芯68所描述的类似的处理来形成管芯88。在一些实施例中，管芯88包括一个或多个存储器管芯，诸如存储器管芯(例如，DRAM管芯、SRAM管芯、高带宽存储器(HBM)管芯、混合存储器立方体(HMC)管芯等)的堆叠件。在存储器管芯的堆叠件的实施例中，管芯88可以包括存储器管芯和存储器控制器两者，诸如例如具有存储器控制器的四个或八个存储器管芯的堆叠件。此外，在一些实施例中，管芯88可以具有不同的尺寸(例如，不同的高度和/或表面积)，并且在其他实施例中，管芯88可以具有相同的尺寸(例如，相同的高度和/或表面积)。
在一些实施例中，管芯88的高度可以类似于管芯68的高度(如图4所示)，或者在一些实施例中，管芯68和88可以具有不同的高度。
管芯88包括主体80、互连结构84和管芯连接件86。管芯88的主体80可以包括任何数量的管芯、衬底、晶体管、有源器件、无源器件等。在实施例中，主体80可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。主体80的半导体材料可以是硅、锗、包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或它们的组合。还可以使用诸如多层衬底或梯度衬底的其他衬底。主体80可以是掺杂的或未掺杂的。可以在有源表面中和/或上形成诸如晶体管、电容器、电阻器、二极管等的器件。
在有源表面上形成包括一个或多个介电层和一个或多个相应的金属化图案的互连结构84。一个或多个介电层中的一个或多个金属化图案可以诸如通过使用通孔和/或迹线在器件之间路由电信号，并且还可以包括诸如电容器、电阻器、电感器等的各个电子器件。可以互连各个器件和金属化图案以实施一个或多个功能。功能可以包括存储器结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。额外地，可以在互连结构84中和/或上形成诸如导电柱(例如，包括诸如铜的金属)的管芯连接件86，以提供至电路和器件的外部电连接。在一些实施例中，管芯连接件86从互连结构84突出以形成在将管芯88接合至其他结构时要使用的柱结构。本领域的普通技术人员将会理解，提供的上述实例是为了说明的目的。可以适当使用其他电路以用于给定应用。
更特别地，可以在互连结构84中形成IMD层。例如，可以通过本领域已知的任何合适的方法(诸如，旋涂、CVD、PECVD、HDP-CVD等)由低K介电材料(诸如，PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成IMD层。例如，通过使用光刻技术在IMD层上沉积并图案化光刻胶材料以暴露IMD层的将变为金属化图案的部分，可以在IMD层中形成金属化图案。诸如各向异性干蚀刻工艺的蚀刻工艺可用于在IMD层中创建与IMD层的暴露部分相对应的凹槽和/或开口。凹槽和/或开口可以内衬有扩散阻挡层并填充有导电材料。扩散阻挡层可以包括通过ALD等沉积的一层或多层氮化钽、钽、氮化钛、钛、钴钨等或它们的组合。金属化图案的导电材料可以包括通过CVD、PVD等沉积的铜、铝、钨、银及它们的组合等。诸如通过使用CMP，可以去除IMD层上的任何多余的扩散阻挡层和/或导电材料。
在管芯连接件66和86分别从互连结构64和84突出的实施例中，可以从管芯68和88排除金属柱79，因为突出的管芯连接件66和86可以用作用于金属帽层78的柱。
导电接合件91将管芯68和管芯88中的电路分别通过互连结构84和64以及管芯连接件86和66电连接至组件96中的再分布结构76。
在一些实施例中，在接合电连接件77/78之前，利用诸如免洗焊剂的焊剂(未示出)涂覆电连接件77/78。电连接件77/78可以浸入到焊剂中，或者可以将焊剂喷射到电连接件77/78上。在另一实施例中，还可以将焊剂施加到电连接件79/78。在一些实施例中，在将管芯68和管芯88附接至组件96之后，在将电连接件77/78和/或79/78与保留的环氧树脂焊剂的环氧树脂部分的至少一些回流之前，电连接件77/78和/或79/78可以具有形成在其上的环氧树脂焊剂(未示出)。保留的环氧树脂部分可以用作底部填充物以减少应力并保护由于回流电连接件77/78/79而产生的接合件。
管芯68和管芯88以及组件96之间的接合可以是焊料接合或直接金属至金属(诸如铜至铜或锡至锡)接合。在实施例中，通过回流工艺将管芯68和管芯88接合至组件96。在该回流工艺期间，电连接件77/78/79分别与管芯连接件66和86接触，并且再分布结构76的焊盘将管芯68和管芯88物理地且电连接至组件96。在接合工艺之后，可以在金属柱77和79与金属帽层78的界面处形成IMC(未示出)。
图4和后续的图分别示出用于形成第一封装件和第二封装件的第一封装件区90和第二封装件区92。划线区94位于相邻的封装件区之间。如图4所示，第一管芯和多个第二管芯附接在第一封装件区90和第二封装件区92的每个中。
在一些实施例中，管芯68是片上系统(SoC)或图形处理单元(GPU)，以及第二管芯是管芯68可使用的存储器管芯。在实施例中，管芯88是堆叠的存储器管芯。例如，堆叠的存储器管芯88可以包括诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等的存储器模块的低功率(LP)双数据率(DDR)存储器模块。
在图5中，将底部填充材料100分配到管芯68、管芯88和再分布结构76之间的间隙中。底部填充材料100可以沿着管芯68和管芯88的侧壁向上延伸。底部填充材料100可以是诸如聚合物、环氧树脂、模制底部填充物等的任何可接受的材料。底部填充材料100可以在附接管芯68和88之后通过毛细管流动工艺形成，或者可以在附接管芯68和88之前通过合适的沉积方法形成。
图7至图20示出形成组件96的第二侧和延伸穿过组件96(参见图20)的衬底70的通孔(TV)128。在图7中，翻转图6的结构以准备形成组件96的第二侧。该结构可以放置在载体衬底200或其他合适的支撑结构上，从而用于图7至图20的工艺。
载体衬底200可以是玻璃载体衬底、陶瓷载体衬底等。图6的结构可以通过释放层202附接至载体衬底200。释放层202可以由聚合物基材料形成，释放层可以与载体衬底200一起从上面的结构中去除。在一些实施例中，释放层202是诸如光热转换(LTHC)释放涂层的环氧树脂基热释放材料，该材料在加热时失去其粘性。在其他实施例中，释放层202可以是紫外(UV)胶，其在暴露于UV光时失去其粘性。释放层202可以以液体形式进行分配并且被固化，可以是层压在载体衬底200上的层压膜，或者可以是类似物。
如图7所示，在该处理阶段处，组件96的衬底70和再分布结构76具有在从约50μm至约775μm的范围内的组合厚度T1。在图8中，对衬底70的第二侧实施减薄工艺以减薄衬底70。减薄工艺可以包括蚀刻工艺、研磨工艺等或它们的组合。在一些实施例中，在减薄工艺之后，组件96的衬底70和再分布结构76具有在从约30μm至约200μm的范围内(诸如100μm)的组合厚度T2。
图9至图19示出形成延伸穿过组件96的衬底70的TV 128的各个中间阶段。TV 128也可以称为电连接件(例如，微凸块)，其允许组件96在后续工艺步骤(参见图21)中接合至封装件衬底。图9至图19示出图8的结构的区域250(参见图8)的详细的截面图。
参考图9，示出区域250的细节。如上所述，区域250包括如上所述的衬底70的部分和再分布结构76的部分。例如，再分布结构76包括IMD层104，其中，IMD层104可以包括如上所述的低k介电材料(例如，USG)。在IMD层104内形成金属化图案102。在一些实施例中，金属化图案102是导线(例如，包括铜、铝、钨、银及它们的组合)，其中，该金属化图案102在管芯68、管芯88和/或封装件衬底300(参见图21)之间提供电路由。
可以在金属化图案102和衬底70之间设置绝缘缓冲层108。在一些实施例中，绝缘缓冲层108在金属化图案102和衬底70之间提供电隔离。在一些实施例中，绝缘缓冲层108包括诸如未掺杂的硅酸盐玻璃(USG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的复合物、它们的组合等的低K介电材料。可以通过诸如旋涂、CVD、PECVD、HDP-CVD等的本领域已知的任何合适的方法沉积绝缘缓冲层108。绝缘缓冲层108和IMD层104的材料可以相同或不同。可以在IMD层104和绝缘缓冲层108之间设置蚀刻停止层106(例如，氮化硅等)。可以通过诸如旋涂、CVD、PECVD、HDP-CVD等的本领域已知的任何合适的方法沉积蚀刻停止层106。可以在制造金属化图案102期间使用蚀刻停止层106，以提供用于在IMD层104中蚀刻开口的端点。如图9所示，金属化图案102还延伸穿过蚀刻停止层106。因此，作为形成金属化图案102的部分，也可以使用合适的光刻和蚀刻工艺来图案化蚀刻停止层106。
在图10中，在衬底70的背侧上沉积绝缘层110。例如，可以在衬底70的与金属化图案102和IMD层104相对的一侧上设置绝缘层110。在一些实施例中，绝缘层110包括诸如氮化硅、氧化硅、氮氧化硅等的含硅绝缘体。可以通过诸如旋涂、CVD、PECVD、HDP-CVD等的本领域已知的任何合适的方法沉积绝缘层110。绝缘层110的厚度可以在约0.4μm至约1.0μm的范围内。
在图11中，穿过绝缘层110、衬底70和绝缘缓冲层108图案化开口112。为了便于说明，在区域250中示出了一个开口112，并且应当理解，可以穿过图8的结构中的绝缘层110、衬底70和缓冲层108同时图案化多个开口112。可以使用例如光刻和蚀刻的组合，依次穿过绝缘层110、衬底70和绝缘缓冲层108图案化开口112。例如，可以通过旋涂等在绝缘层110上方沉积光刻胶(未示出)。在沉积之后，例如，通过将图案化的光掩模放置在光刻胶上方，使用光掩模曝光光刻胶的部分，并且显影光刻胶以去除光刻胶的曝光或未曝光部分(取决于使用正性光刻胶还是负性光刻胶)来图案化光刻胶。光刻胶的图案对应于开口112的图案。然后使用光刻胶作为掩模依次蚀刻绝缘层110、衬底70和绝缘缓冲层108。蚀刻工艺的类型可以取决于绝缘层110、衬底70和绝缘缓冲层108的材料。例如，因为衬底70和绝缘层110/绝缘缓冲层108由不同材料制成，所以可以使用不同的蚀刻工艺。例如，为了蚀刻绝缘层110，可以使用干蚀刻工艺。用于干蚀刻工艺的示例性蚀刻剂包括SF6等。作为另一实例，为了蚀刻衬底70，可以使用干蚀刻工艺。用于干蚀刻工艺的示例性蚀刻剂包括SF6等。作为另一实例，为了蚀刻绝缘缓冲层108，可以使用干蚀刻工艺和/或湿蚀刻工艺。用于干蚀刻工艺的示例性蚀刻剂包括SF6等。用于湿蚀刻工艺的示例性蚀刻剂包括氟化氢等。
此外，作为使用不同的蚀刻工艺的结果，穿过绝缘层110、衬底70和绝缘缓冲层108的开口112的宽度可以不同。例如，绝缘层110中的开口112的宽度W1可以大于衬底70和绝缘缓冲层108中的开口112的宽度W2。在一些实施例中，宽度W1在约15μm至约30μm的范围内，并且宽度W2在约15.1μm至约30.3μm的范围内。在其他实施例中，绝缘层110中的开口112的宽度W1可以等于衬底70和绝缘缓冲层108中的开口112的宽度W2。此外，开口112可以具有位于衬底70中侧壁112A和112B，并且开口112可以具有位于绝缘层110中侧壁112C。在一些实施例中，侧壁112B将侧壁112A直接连接至侧壁112C。与侧壁112A和侧壁112C相比，可相对于衬底70的主表面以不同的角度设置侧壁112B。例如，相对于衬底70的主表面，侧壁112B的斜率可以小于侧壁112A和侧壁112C的相应斜率。
可以在图案化工艺中使用其他层来形成开口112。例如，可以使用一个或多个可选的硬掩模层来图案化绝缘层110、衬底70和绝缘缓冲层108。通常，在蚀刻工艺需要除了由光刻胶材料提供的掩蔽之外的掩蔽的实施例中，一个或多个硬掩模层是有用的。在后续的蚀刻工艺以图案化绝缘层110、衬底70期间，还将蚀刻图案化的光刻胶掩模，但是光刻胶材料的蚀刻速率不如绝缘层110、衬底70和绝缘缓冲层108的蚀刻速率高。如果蚀刻工艺使得在完成对绝缘层110、衬底70和绝缘缓冲层108的蚀刻工艺之前可以消耗图案化的光刻胶掩模，则可以使用额外的硬掩模。选择硬掩模层或多个硬掩模层的材料，使得该硬掩模层的蚀刻速率小于其下面的材料(诸如，绝缘层110、衬底70和/或绝缘缓冲层108的材料)的蚀刻速率。在图案化开口112之后，可以去除可选的硬掩模层和光刻胶的任何剩余的残留物。
在图12中，在绝缘层110上方并且沿着开口112的侧壁和底面沉积绝缘层114。在一些实施例中，绝缘层114包括诸如氮化硅、氧化硅、氮氧化硅等的含硅绝缘体。绝缘层114的材料可以与绝缘层110的材料相同或不同。即使在绝缘层114和绝缘层110由相同的材料制成的实施例中，由于用于形成绝缘层110和114的单独的沉积工艺，仍然可以在绝缘层110和绝缘层114之间形成界面。可以通过诸如CVD、PECVD、HDP-CVD等的本领域已知的任何合适的方法来沉积绝缘层114。在一些实施例中，使用共形沉积工艺来沉积绝缘层114，从而使得绝缘层114的横向部分的厚度(例如，开口112的底面之外和上方的部分)大致等于绝缘层114的垂直部分(例如，沿着开口112的侧壁的部分)的厚度。绝缘层114的厚度可以在约1μm至约5μm的范围内。
接下来参考图13，使用合适的蚀刻工艺去除绝缘层114的横向部分。在一些实施例中，蚀刻可以是各向异性的(例如，指向由箭头150指示的方向)。各向异性蚀刻工艺的实例包括使用SF6等作为蚀刻剂的干蚀刻工艺。作为各向异性蚀刻工艺的结果，去除绝缘层114的横向部分，同时保留绝缘层114的垂直部分(例如，开口112的侧壁上的部分)。因此，沿着开口112的侧壁112A、112B和112C形成侧壁间隔件114'。例如，侧壁间隔件114'可以与绝缘层110的侧壁和衬底70的侧壁形成界面。在顶视图中，侧壁间隔件114'可以(未提供)具有环形形状。
图案化绝缘层114以限定侧壁间隔件114'可能不需要使用任何光刻工艺或掩模层。例如，因为在形成绝缘层114之前已经形成并且图案化绝缘层110，所以可以使用定向蚀刻工艺在包括衬底70的整个晶圆上图案化绝缘层114，而不需要掩蔽晶圆的不同区域。可以使用定时蚀刻工艺，从而使得该结构包括沿着顶面和侧壁由绝缘材料(例如，绝缘层110和侧壁间隔件114')覆盖的衬底70。因此，可以降低制造成本。
在图14中，沉积应力缓冲层116。可以通过诸如CVD、PECVD、HDP-CVD等的本领域已知的任何合适的方法来沉积应力缓冲层116。在一些实施例中，使用共形沉积工艺来沉积应力缓冲层116，从而使得应力缓冲层116的横向部分的厚度(例如，开口112的底面之外和上方的部分)大致等于应力缓冲层116的垂直部分(例如，沿着开口112的侧壁的部分)的厚度。在其他实施例中，可以使用诸如旋涂的非共形工艺来沉积应力缓冲层116。应力缓冲层116可以包括与绝缘层110和侧壁间隔件114'不同的材料。例如，在一些实施例中，应力缓冲层116包括诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物。在一些实施例中，应力缓冲层116沉积为光敏层，同时绝缘层110和侧壁间隔件114'不沉积为光敏层。尽管图14将应力缓冲层116示出为单层，但在其他实施例中，应力缓冲层116可以是包括例如多个堆叠的聚合物层的多层结构。在这样的实施例中，多个堆叠的聚合物层中的每个可以包括不同的材料。
在图15中，图案化应力缓冲层116以去除开口112中的应力缓冲层116的部分，并且将开口112延伸到应力缓冲层116中。图案化应力缓冲层116可以进一步暴露绝缘层110的部分。可以使用任何合适的工艺来实施应力缓冲层116的图案化。例如，当应力缓冲层116包括光敏材料(例如，PBO)时，可以使用光刻工艺来图案化应力缓冲层116。在这样的实施例中，在图案化之后，可以在图案化之后对应力缓冲层116实施固化以硬化应力缓冲层116。在一些实施例中，应力缓冲层116可以包括具有相对低的固化温度(例如，小于约200℃)的聚合物，以便减少将结构的其他组件(例如，管芯68和管芯88，参见图8)暴露于高温并在固化期间损坏这些组件的风险。在固化之后，应力缓冲层116可能不再是光敏的。在其他实施例中，应力缓冲层116不沉积为光敏层，并且可以使用光刻和蚀刻的组合利用一个或多个掩模来图案化应力缓冲层116。
在图16至图18A和图18B中，穿过开口112形成导电部件。作为形成导电部件的实例，在图16中的应力缓冲层116上方并且沿着开口112的侧壁/底面形成晶种层118。在一些实施例中，晶种层118是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。例如，可以使用PVD等形成晶种层。
接下来，在图17中，在晶种层118上形成并图案化光刻胶120。可以图案化光刻胶以包括开口122，其中，开口122暴露晶种层118的位于开口112中的部分。也可以在开口122中暴露位于应力缓冲层116上方的晶种层118的至少部分。光刻胶的图案对应于后续形成的导电部件(例如导电部件124，参见图18A)的图案。
在图18A中，在晶种层118的暴露部分上的开口112(参见图17)和开口122(参见图17)中形成导电部件124。可以通过诸如电镀或化学镀等的镀形成导电部件124。导电部件124可以包括如铜、钛、钨、铝等的金属。在形成导电部件124之后，去除光刻胶120(参见图17)和晶种层118的其上未形成导电部件124的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶120。一旦去除光刻胶120，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层118的暴露部分。在顶视图中(参见图18B)，所得到的导电部件124可以具有圆形或卵形形状。在其他实施例中，还可以预期用于导电部件124的其他形状。在顶视图中，侧壁间隔件114'(图18B中未示出)可以环绕、物理分离和从衬底70隔离导电部件。
在图19中，在导电部件124上方形成焊料区126。在一些实施例中，通过首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等这种合适的方法形成焊料层来形成焊料区126。一旦已经在导电部件124上形成焊料层，可以实施回流以将材料成形为期望的凸块形状。
因此，TV 128形成为延伸穿过应力缓冲层116、绝缘层110和衬底70。TV 128包括焊料区126、导电部件124和晶种层118。在各个实施例中，TV 128电连接至IMD层104中的金属化图案102。绝缘层110和侧壁间隔件114'将TV 128与衬底70和延伸穿过衬底70的其他TV128(参见图20)电隔离。在一些实施例中，TV 128还用作微凸块，其中，该微凸块可以用于将衬底70接合至另一封装部件(例如，封装件衬底300，参见图21)。此外，由于侧壁间隔件114'的材料，侧壁间隔件114'可以为TV 128提供改进的结构支撑。因此，当TV 128与另一封装部件接合(例如，热工艺)时，可以减少制造缺陷(例如，TV 128的变形)。在后续的测试循环(例如可靠性应力测试)中可能类似地减少制造缺陷。
图20示出在形成TV 128之后包括衬底70的晶圆的缩小的视图。使用以上相对于图9至图19描述的工艺来形成每个TV 128。如图20所示，TV128通过再分布结构76中的金属化图案电连接至管芯68和管芯88。
还如图20所示，实施载体分离以将载体衬底200与管芯68、管芯88和模塑料120分离(去接合)。根据一些实施例，去接合包括将诸如激光或UV光的光投射到释放层202上，从而使得释放层202在光的热量下分解，并且可以去除载体衬底200。然后翻转结构并放置在胶带上(未示出)。后续地，沿着划线区94在相邻区域90和92之间分割组件96以形成组件封装件204，其中，该组件封装件204包括管芯68、组件96和管芯88等。可以通过锯切、切割等来实施分割。
图21示出在衬底300上附接组件封装件204。TV 128对准并抵靠(put against)衬底300的接合焊盘302。可以回流TV 128以在衬底300和组件96之间创建接合。衬底300可以包括封装件衬底，诸如其中包括核心的构建衬底、包括多个层压介电膜的层压衬底、PCB等。衬底300可以包括与组件封装件相对的诸如焊料球的电连接件(未示出)，以允许将衬底300安装至另一器件。可以在组件封装件204和衬底300之间并且围绕TV 128的从衬底70、绝缘层110和应力缓冲层116突出的部分分配底部填充材料(未示出)。底部填充材料可以是诸如聚合物、环氧树脂、模制底部填充物等的任何可接受的材料。
在一些实施例中，可以包括应力缓冲层116以吸收由组件封装件204和衬底300之间的接合工艺引起的应力。此外，如上所述，侧壁间隔件114'和绝缘层110可以包括在热工艺(例如，将组件封装件204接合至衬底300)期间减少TV 128的变形的材料。
额外地，一个或多个表面器件304可以连接至衬底300。表面器件304可用于向组件封装件204或封装件整体提供额外的功能或编程。在实施例中，表面器件304可以包括期望连接至组件封装件204或封装件的其他部分并与其结合使用的表面安装器件(SMD)或集成无源器件(IPD)，其中，该集成无源器件(IPD)包括诸如电阻器、电感器、电容器、跳线、这些的组合等的无源器件。根据各个实施例，可以将表面器件304放置到衬底300的第一主表面上、衬底300的相对主表面上或两者上。
还可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘以允许使用探针和/或探针卡等测试3D封装件或3DIC。可以对中间结构以及最终结构实施验证测试。额外地，本文公开的结构和方法可以与测试方法结合使用，该测试方法结合了已知良好管芯的中间验证以增加产量并降低成本。
本发明中的器件和方法的实施例具有许多优势。例如，可以在制造期间减薄的组件(例如，组件96)的半导体衬底(例如，衬底70)。由于半导体衬底的薄度，延伸穿过半导体衬底的导电通孔(例如，TV 128)在器件封装件的热处理期间(例如，可靠性/应力测试、回流/接合至封装件衬底等)变形(例如，分层)的风险增加。各个实施例在导电通孔的侧壁上提供绝缘间隔件(例如，侧壁间隔件114’)以改善导电通孔的刚性并减少制造缺陷。在一些实施例中，绝缘间隔件可以将导电通孔与中介层的半导体衬底隔离，并且为导电通孔提供增加的结构支撑，这减少了后续的热工艺(例如，接合和/或可靠性测试)期间的制造缺陷。
根据实施例，一种方法包括将第一管芯接合至中介层的第一侧，中介层包括衬底；在中介层的与第一侧相对的第二侧上沉积第一绝缘层；穿过衬底和第一绝缘层图案化开口；在第一绝缘层上方并且沿着开口的侧壁和横向表面沉积第二绝缘层，第二绝缘层包括硅；去除第二绝缘层的横向部分以在开口的侧壁上限定侧壁间隔件；以及在开口中形成通孔，其中，通孔电连接至第一管芯。在实施例中，在将第一管芯接合至中介层的第一侧时，中介层是晶圆的组件，并且该方法还包括在开口中形成通孔之后，从晶圆分割中介层。在实施例中，去除第二绝缘层的横向部分包括不使用任何图案化掩模的各向异性蚀刻工艺。在实施例中，去除第二绝缘层的横向部分暴露第一绝缘层。在实施例中，第一绝缘层和第二绝缘层由相同的材料制成并且均包括氮化硅。在实施例中，该方法还包括在开口中形成通孔之前，在第一绝缘层上方形成应力缓冲层；应力缓冲层包括与第一绝缘层和第二绝缘层不同的材料。在实施例中，形成通孔包括沿着开口的侧壁和底面沉积晶种层；在晶种层上镀导电部件，其中，导电部件延伸穿过衬底和第一绝缘层；以及在导电部件的与晶种层相对的表面上形成焊料区。在实施例中，该方法还包括将中介层接合至封装件衬底；焊料区直接接合至封装件衬底的接触焊盘。
根据实施例，一种方法包括：将第一管芯和第二管芯接合至中介层，中介层层包括再分布结构，其中，该再分布结构包括将第一管芯电连接至第二管芯的一个或多个金属化图案；以及位于再分布结构的与第一管芯和第二管芯相对的一侧上的衬底。该方法还包括在衬底的与再分布结构相对的表面上沉积第一含硅绝缘层；图案化延伸穿过第一含硅绝缘层和衬底的第一开口，第一开口暴露一个或多个金属化图案的第一金属化图案；沿第一开口的侧壁形成侧壁间隔件，侧壁间隔件包括含硅绝缘材料；形成延伸穿过第一开口并电连接至第一金属化图案的电连接件；以及使用电连接件将封装件衬底接合至中介层。在实施例中，该方法还包括：在形成侧壁间隔件之后，在第一含硅绝缘层上方沉积绝缘缓冲层；绝缘缓冲层包括聚合物；并将第一开口延伸到绝缘缓冲层中。在实施例中，形成侧壁间隔件包括：在第一含硅绝缘层上方、沿着第一开口的侧壁以及在第一开口的底面上方沉积第二含硅绝缘层；以及使用各向异性蚀刻工艺图案化第二含硅绝缘层以去除第二含硅绝缘层的横向部分并限定侧壁间隔件。在实施例中，侧壁间隔件与衬底形成第一界面并且与第一含硅绝缘层形成第二界面，第一界面与第二界面横向间隔开。在实施例中，侧壁间隔件与衬底形成第三界面，第三界面设置在第一界面和第二界面之间，相对于衬底的主表面，第三界面的斜率小于第一界面的斜率和第二界面的斜率。在实施例中，第一含硅绝缘层包括氮化硅、氧化硅或氮氧化硅，并且侧壁间隔件包括氮化硅、氧化硅或氮氧化硅。在实施例中，形成电连接件包括：沿着侧壁间隔件的侧壁并且在第一金属化图案上方沉积种晶种层；镀从晶种层延伸至第一开口外部的导电部件；以及在导电部件上形成焊料区。在实施例中，该方法还包括在第一管芯和中介层之间分配底部填充物，底部填充物还在第二管芯和中介层之间延伸；以及将第一管芯、第二管芯和底部填充物密封在模塑料中。在实施例中，延伸穿过第一含硅绝缘层和衬底图案化第一开口包括将第一开口图案化为在第一含硅绝缘层中的宽度比在衬底中的宽度更宽。
根据实施例，封装件包括接合至中介层的第一管芯，中介层包括电连接至第一管芯的金属化图案；以及位于金属化图案的与第一管芯相对的一侧上的衬底。封装件还包括位于衬底的与金属化图案相对的表面上的含硅绝缘层；位于含硅绝缘层的与衬底相对的一侧上的聚合物层；穿过聚合物层、含硅绝缘层和衬底延伸至金属化图案的通孔；以及位于通孔和衬底之间的含硅侧壁间隔件，含硅侧壁间隔件进一步设置在通孔和含硅绝缘层之间。在实施例中，含硅侧壁间隔件与含硅绝缘层形成第一界面并且由与含硅绝缘层相同的材料制成。在实施例中，含硅侧壁间隔件与衬底形成第二界面，第一界面与第二界面横向间隔开。在实施例中，通孔包括延伸穿过聚合物层、含硅绝缘层和衬底的导电部件；以及位于导电部件的与金属化图案相对的一侧上的焊料区，其中，焊料区直接接合至封装件衬底的接触焊盘。在实施例中，含硅侧壁间隔件包括氧化硅、氮化硅或氮氧化硅。
根据实施例，封装件包括接合至封装组件的第一管芯和第二管芯，封装组件包括再分布结构，再分布结构包括在第一管芯和第二管芯之间提供电路由的一层或多层金属化图案；以及位于再分布结构的与第一管芯和第二管芯相对的一侧上的衬底。封装件还包括在衬底的与再分布结构相对的一侧上的第一绝缘层，第一绝缘层包括氮化硅、氧化硅或氮氧化硅；沿着第一绝缘层和衬底的侧壁的侧壁间隔件，其中，侧壁间隔件包括氮化硅、氧化硅或氮氧化硅；以及延伸穿过第一绝缘层和衬底的电连接件，侧壁间隔件将电连接件与衬底隔离，其中，电连接件电连接至金属化图案中的第一金属化图案。在实施例中，封装件还包括位于第一绝缘层的与衬底相对的一侧上的第二绝缘层，第二绝缘层包括与第一绝缘层不同的材料。在实施例中，侧壁间隔件包括位于第一绝缘层中具有第一斜率的第一侧壁；位于衬底中具有第二斜率的第二侧壁；以及将第一侧壁连接至第二侧壁的第三侧壁，第三侧壁具有相对于衬底的主表面比第一斜率和第二斜率更小的第三斜率。在实施例中，封装组件是没有任何有源器件的中介层。
根据实施例，中介层包括位于第一介电层中的金属化图案；位于第一介电层上方的衬底；位于衬底上方的第一绝缘层，第一绝缘层包括氮化硅、氧化硅或氮氧化硅；沿着第一绝缘层和衬底的侧壁的侧壁间隔件，其中侧壁间隔件包括氮化硅、氧化硅或氮氧化硅。侧壁间隔件包括位于第一绝缘层中的具有第一斜率的第一侧壁；位于衬底中具有第二斜率的第二侧壁；以及将第一侧壁连接至第二侧壁的第三侧壁，第三侧壁具有比相对于衬底的主表面的第一斜率和第二斜率更小的第三斜率；以及延伸穿过第一绝缘层和衬底的电连接件，侧壁间隔件设置在电连接件和衬底之间。电连接件电连接至金属化图案。在实施例中，中介层还包括位于第一绝缘层和第一介电层之间的第二绝缘层，侧壁间隔件延伸穿过第二绝缘层。
根据实施例，一种方法包括：在没有任何有源器件的中介层的衬底上方沉积第一绝缘层，第一绝缘层设置在衬底的与再分布结构相对的一侧上；图案化穿过衬底和第一绝缘层的开口；在第一绝缘层上方并沿着开口的侧壁和横向表面沉积第二绝缘层，其中，第二绝缘层包括氧化硅、氮化硅或氮氧化硅；去除第二绝缘层的横向部分以在开口的侧壁上限定侧壁间隔件；以及在开口中形成外部连接件，其中，外部连接件电连接至再分布结构中的金属化图案。在实施例中，该方法还包括将第一管芯接合至中介层的第一侧，并将封装件衬底接合至中介层的与第一侧相对的第二侧，外部连接件的焊接区直接接合至封装件衬底的接触焊盘。
根据本发明的一些实施例，提供了一种形成封装件的方法，包括：将第一管芯接合至中介层的第一侧，所述中介层层包括衬底；在所述中介层的与所述第一侧相对的第二侧上沉积第一绝缘层；穿过所述衬底和所述第一绝缘层图案化开口；在所述第一绝缘层上方并且沿着所述开口的侧壁和横向表面沉积第二绝缘层，所述第二绝缘层包括硅；去除所述第二绝缘层的横向部分以在所述开口的侧壁上限定侧壁间隔件；以及在所述开口中形成通孔，其中，所述通孔电连接至所述第一管芯。
在上述方法中，在将所述第一管芯接合至所述中介层的第一侧时，所述中介层是晶圆的组件，并且其中，所述方法还包括在所述开口中形成所述通孔之后，从所述晶圆分割所述中介层。
在上述方法中，去除所述第二绝缘层的横向部分包括不使用任何图案掩模的各向异性蚀刻工艺。
在上述方法中，去除所述第二绝缘层的横向部分暴露所述第一绝缘层。
在上述方法中，所述第一绝缘层和所述第二绝缘层由相同的材料制成并且均包括氮化硅。
在上述方法中，所述方法还包括在所述开口中形成所述通孔之前，在所述第一绝缘层上方形成应力缓冲层，其中，所述应力缓冲层包括与所述第一绝缘层和所述第二绝缘层不同的材料。
在上述方法中，形成所述通孔包括：沿着所述开口的侧壁和底面沉积晶种层；在所述晶种层上镀导电部件，其中，所述导电部件延伸穿过所述衬底和所述第一绝缘层；以及在所述导电部件的与所述晶种层相对的表面上形成焊料区。
在上述方法中，还包括将所述中介层接合至封装件衬底，其中，所述焊接区直接接合至所述封装件衬底的接触焊盘。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：将第一管芯和第二管芯接合至中介层，所述中介层包括：再分布结构，包括将所述第一管芯电连接至所述第二管芯的一个或多个金属化图案；以及衬底，位于所述再分布结构的与所述第一管芯和所述第二管芯相对的一侧上；在所述衬底的与所述再分布结构相对的表面上沉积第一含硅绝缘层；延伸穿过所述第一含硅绝缘层和所述衬底图案化第一开口，所述第一开口暴露所述一个或多个金属化图案的第一金属化图案；沿着所述第一开口的侧壁形成侧壁间隔件，所述侧壁间隔件包括含硅绝缘材料；形成延伸穿过所述第一开口并电连接至所述第一金属化图案的电连接件；以及使用所述电连接件将封装件衬底接合至所述中介层。
在上述方法中，还包括：在形成所述侧壁间隔件之后，在所述第一含硅绝缘层上方沉积绝缘缓冲层，所述绝缘缓冲层包括聚合物；以及将所述第一开口延伸到所述绝缘缓冲层中。
在上述方法中，形成所述侧壁间隔件包括：在所述第一含硅绝缘层上方，沿着所述第一开口的侧壁并且在所述第一开口的底面上方沉积第二含硅绝缘层；以及使用各向异性蚀刻工艺图案化所述第二含硅绝缘层以去除所述第二含硅绝缘层的横向部分并限定所述侧壁间隔件。
在上述方法中，所述侧壁间隔件与所述衬底形成第一界面并且与所述第一含硅绝缘层形成第二界面，所述第一界面与所述第二界面横向间隔开。
在上述方法中，所述侧壁间隔件与所述衬底形成第三界面，所述第三界面设置在所述第一界面和所述第二界面之间，相对于所述衬底的主表面，所述第三界面的斜率小于所述第一界面的斜率和所述第二界面的斜率。
在上述方法中，所述第一含硅绝缘层包括氮化硅、氧化硅或氮氧化硅，并且其中，所述侧壁间隔件包括氮化硅、氧化硅或氮氧化硅。
在上述方法中，形成所述电连接件包括：沿着所述侧壁间隔件的侧壁并且在所述第一金属化图案上方沉积晶种层；镀从所述晶种层延伸至所述第一开口的外部的导电部件；以及在所述导电部件上形成焊料区。
在上述方法中，还包括：在所述第一管芯和所述中介层之间分配底部填充物，所述底部填充物还在所述第二管芯和所述中介层之间延伸；以及将所述第一管芯、所述第二管芯和所述底部填充物密封在模塑料中。
在上述方法中，图案化延伸穿过所述第一含硅绝缘层和所述衬底的第一开口包括将所述第一开口图案化为在所述第一含硅绝缘层中的宽度比在所述衬底中的宽度更宽。
根据本发明的又一些实施例，还提供了一种封装件，包括：第一管芯，所述第一管芯接合至中介层，所述中介层包括：金属化图案，电连接至所述第一管芯；以及衬底，位于所述金属化图案的与所述第一管芯相对的一侧；含硅绝缘层，位于所述衬底的与所述金属化图案相对的表面上；聚合物层，位于所述含硅绝缘层的与所述衬底相对的一侧上；通孔，延伸穿过所述聚合物层、所述含硅绝缘层和所述衬底至所述金属化图案；以及含硅侧壁间隔件，位于所述通孔和所述衬底之间，所述含硅侧壁间隔件还设置在所述通孔和所述含硅绝缘层之间。
在上述封装件中，所述含硅侧壁间隔件与所述含硅绝缘层形成第一界面并且由与所述含硅绝缘层相同的材料制成。
在上述封装件中，所述含硅侧壁间隔件与所述衬底形成第二界面，所述第一界面与所述第二界面横向间隔开。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成封装件的方法，包括：
将第一管芯接合至中介层的第一侧，所述中介层层包括衬底；
在所述中介层的与所述第一侧相对的第二侧上沉积第一绝缘层；
穿过所述衬底和所述第一绝缘层图案化开口；
在所述第一绝缘层上方并且沿着所述开口的侧壁和横向表面沉积第二绝缘层，所述第二绝缘层包括硅；
去除所述第二绝缘层的横向部分以在所述开口的侧壁上限定侧壁间隔件；以及
在所述开口中形成通孔，其中，所述通孔电连接至所述第一管芯。
2.根据权利要求1所述的方法，其中，在将所述第一管芯接合至所述中介层的第一侧时，所述中介层是晶圆的组件，并且其中，所述方法还包括在所述开口中形成所述通孔之后，从所述晶圆分割所述中介层。
3.根据权利要求1所述的方法，其中，去除所述第二绝缘层的横向部分包括不使用任何图案掩模的各向异性蚀刻工艺。
4.根据权利要求1所述的方法，其中，去除所述第二绝缘层的横向部分暴露所述第一绝缘层。
5.根据权利要求1所述的方法，其中，所述第一绝缘层和所述第二绝缘层由相同的材料制成并且均包括氮化硅。
6.根据权利要求1所述的方法，其中，所述方法还包括在所述开口中形成所述通孔之前，在所述第一绝缘层上方形成应力缓冲层，其中，所述应力缓冲层包括与所述第一绝缘层和所述第二绝缘层不同的材料。
7.根据权利要求1所述的方法，其中，形成所述通孔包括：
沿着所述开口的侧壁和底面沉积晶种层；
在所述晶种层上镀导电部件，其中，所述导电部件延伸穿过所述衬底和所述第一绝缘层；以及
在所述导电部件的与所述晶种层相对的表面上形成焊料区。
8.根据权利要求7所述的方法，还包括将所述中介层接合至封装件衬底，其中，所述焊接区直接接合至所述封装件衬底的接触焊盘。
9.一种形成封装件的方法，包括：
将第一管芯和第二管芯接合至中介层，所述中介层包括：
再分布结构，包括将所述第一管芯电连接至所述第二管芯的一个或多个金属化图案；以及
衬底，位于所述再分布结构的与所述第一管芯和所述第二管芯相对的一侧上；
在所述衬底的与所述再分布结构相对的表面上沉积第一含硅绝缘层；
延伸穿过所述第一含硅绝缘层和所述衬底图案化第一开口，所述第一开口暴露所述一个或多个金属化图案的第一金属化图案；
沿着所述第一开口的侧壁形成侧壁间隔件，所述侧壁间隔件包括含硅绝缘材料；
形成延伸穿过所述第一开口并电连接至所述第一金属化图案的电连接件；以及
使用所述电连接件将封装件衬底接合至所述中介层。
10.一种封装件，包括：
第一管芯，所述第一管芯接合至中介层，所述中介层包括：
金属化图案，电连接至所述第一管芯；以及
衬底，位于所述金属化图案的与所述第一管芯相对的一侧；
含硅绝缘层，位于所述衬底的与所述金属化图案相对的表面上；
聚合物层，位于所述含硅绝缘层的与所述衬底相对的一侧上；
通孔，延伸穿过所述聚合物层、所述含硅绝缘层和所述衬底至所述金属化图案；以及
含硅侧壁间隔件，位于所述通孔和所述衬底之间，所述含硅侧壁间隔件还设置在所述通孔和所述含硅绝缘层之间。
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