TW201913928A - 半導體元件封裝及其製造方法 - Google Patents

半導體元件封裝及其製造方法 Download PDF

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TW201913928A
TW201913928A TW106143053A TW106143053A TW201913928A TW 201913928 A TW201913928 A TW 201913928A TW 106143053 A TW106143053 A TW 106143053A TW 106143053 A TW106143053 A TW 106143053A TW 201913928 A TW201913928 A TW 201913928A
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Taiwan
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insulating layer
silicon
substrate
layer
die
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TW106143053A
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TWI657553B (zh
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黃松輝
張宏賓
邱紹玲
侯上勇
李宛諭
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台灣積體電路製造股份有限公司
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Publication of TWI657553B publication Critical patent/TWI657553B/zh

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Abstract

本發明實施例的半導體元件封裝的製造方法包括：將第一晶粒結合至中介體的第一側，所述中介體包括基底；在將第一晶粒結合至中介體的第一側之後，在所述中介體的與所述第一側相對的第二側上沈積第一絕緣層；穿過所述基底及所述第一絕緣層圖案化出開口；以及在所述第一絕緣層之上以及沿所述開口的側壁及橫向表面沈積第二絕緣層。所述第二絕緣層包括矽。所述方法更包括：移除所述第二絕緣層的橫向部分，以在所述開口的側壁上界定側壁間隔壁；以及在所述開口中形成穿孔，其中所述穿孔電性連接至所述第一晶粒。

Description

半導體元件封裝及其製造方法
自開發出積體電路（integrated circuit，IC）以來，半導體行業已因各種電子組件（即，電晶體、二極體、電阻器、電容器等）積體密度的持續提升而經歷持續且快速的成長。很大程度上，積體密度的該些提升源自於最小特徵尺寸（minimum feature size）的重複減小，此使得更多的組件能夠整合至給定區域中。
由於積體組件所佔據的面積主要位於半導體晶圓的表面上，該些整合度提升本質上是在二維（two-dimensional，2D）的層面上。積體電路的密度增大及對應的面積減小已普遍抑制了將積體電路晶片直接結合至基底的能力。目前使用中介體（interposer）來將球接觸區域自晶片的區域重新分佈至更大的中介體區域。此外，藉由使用中介體，能夠達成包括多個晶片的三維（three-dimensional，3D）封裝。亦已開發出包含三維態樣的其他封裝。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下（beneath）」、「下面（below）」、「下部的（lower）」、「上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括元件在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或處於其他定向）且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
各種實施例包括一種元件封裝（device package）。所述元件封裝包括一或多個半導體晶片以及封裝基底。所述一或多個半導體晶片結合至中介體。所述封裝基底結合至所述中介體的與所述一或多個半導體晶片相對的側。在一些實施例中，元件封裝可被稱作基底上晶圓上晶片（chip-on-wafer-on-substrate，CoWoS）超薄夾層（ultra-thin sandwich，UTS）封裝。中介體在所述一或多個半導體晶片與封裝基底之間提供電性路由（electrical routing）。舉例而言，中介體可包括設置於半導體基底上的重佈線結構（例如，包括設置於一或多個絕緣層中的導電線及/或導電通孔（conductive via））。重佈線結構往來於所述一或多個半導體晶片提供電性路由。導電通孔可延伸穿過基底且電性連接至重佈線結構的導電特徵。在一些實施例中，在導電通孔上設置焊料區以提供用於結合至封裝基底的電性連接件（例如，微凸塊（μbump））。
為達成小的封裝輪廓，可在製造期間將中介體的半導體基底薄化。基於半導體基底的薄化，延伸穿過所述半導體基底的導電通孔在元件封裝的熱加工（例如，對封裝基底進行的可靠性/應力測試、回流（reflow）/結合等）期間變形（例如，分層（delamination））的風險加大。各種實施例在導電通孔的側壁上提供絕緣間隔壁以提高所述導電通孔的剛性（rigidity）且減少製造缺陷（manufacturing defect）。在一些實施例中，絕緣間隔壁可使導電通孔與中介體的半導體基底絕緣且提高導電通孔的結構支撐。舉例而言，絕緣間隔壁可為例如氮化矽、氧化矽、氮氧化矽等含矽材料。相較於其他絕緣材料（例如，聚合物）而言，已觀察到由以上材料製成的間隔壁會提供得到改善的結構性支撐。
將在一種使用基底上晶圓上晶片（CoWoS）加工的晶粒-中介體-基底（Die-Interposer-Substrate）堆疊封裝的特定技術背景中闡述各實施例。然而，其他實施例亦可應用於其他封裝（例如，晶粒-晶粒-基底（Die-Die-Substrate）堆疊封裝）及其他加工。本文中所論述的實施例是為了提供實例以便能夠製成或使用本發明的標的（subject matter），且此項技術中具有通常知識者將易於理解，可在保持處於不同實施例的預期範圍內的同時作出潤飾。以下各圖中的相同參考編號及符號指代相同組件。儘管方法實施例可被論述成以特定次序執行；然而其他方法實施例可以任何合理的次序執行。
圖1示出形成一或多個晶粒68。晶粒68的主體60可包括任意數目的晶粒、基底、電晶體、主動元件、被動元件等。在實施例中，主體60可包括塊狀半導體基底（bulk semiconductor substrate）、絕緣層上半導體（semiconductor-on-insulator，SOI）基底、多層式半導體基底（multi-layered semiconductor substrate）等。主體60的半導體材料可為：矽；鍺；化合物半導體，包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用例如多層式基底或梯度基底（gradient substrate）等其他基底。主體60可為經摻雜的或未經摻雜的。可在主動表面62中及/或主動表面62上形成例如電晶體、電容器、電阻器、二極體等元件。
在主動表面62上形成包括一或多個介電層及相應金屬化圖案的內連線結構64。介電層中的金屬化圖案可例如使用通孔及/或跡線（trace）來在各元件之間路由電性訊號，且所述介電層中的所述金屬化圖案亦可含有例如電容器、電阻器、電感器等各種電性元件。所述各種元件與金屬化圖案可進行內連以執行一或多個功能。所述功能可包括記憶體結構、處理結構、感測器、放大器、功率分佈、輸入/輸出電路系統等。另外，在內連線結構64中及/或內連線結構64上形成例如導電柱（例如，包含例如銅等金屬）等晶粒連接件66以向所述電路系統及元件提供外部電性連接。在一些實施例中，晶粒連接件66自內連線結構64突出以形成欲在將晶粒68結合至其他結構時使用的柱結構。此項技術中具有通常知識者應知，提供以上實例是用於說明的目的。可使用適宜於給定應用的其他電路系統。
更具體而言，可在內連線結構64中形成金屬間介電質（inter-metallization dielectric，IMD）層。可藉由例如旋轉塗佈、化學氣相沈積（chemical vapor deposition，CVD）、電漿增強型化學氣相沈積（plasma-enhanced CVD，PECVD）、高密度電漿化學氣相沈積（high-density plasma chemical vapor deposition，HDP-CVD）等此項技術中所習知的任何適合的方法以例如以下材料來形成金屬間介電質層：低介電常數介電材料（low-K dielectric material），例如未經摻雜的矽酸鹽玻璃（undoped silicate glass，USG）、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼磷矽酸鹽玻璃（borophosphosilicate glass，BPSG）、氟矽酸鹽玻璃（fluorosilicate glass，FSG）、SiOx Cy 、旋塗玻璃（Spin-On-Glass）、旋塗聚合物（Spin-On-Polymer）、矽碳材料、其化合物、其複合物、其組合等。可例如藉由以下方式在金屬間介電質層中形成金屬化圖案：使用微影技術（photolithography technique）在所述金屬間介電質層上沈積光阻（photoresist）材料並將所述光阻材料圖案化以暴露出所述金屬間介電質層的將變成所述金屬化圖案的一些部分。可使用例如非等向性乾式蝕刻製程（anisotropic dry etch process）等蝕刻製程在金屬間介電質層中形成與所述金屬間介電質層的被暴露出的部分對應的凹陷部及/或開口。凹陷部及/或開口可被襯覆以擴散障壁層（diffusion barrier layer）並被填充以導電材料。擴散障壁層可包括藉由原子層沈積（atomic layer deposition，ALD）等而沈積的氮化鉭、鉭、氮化鈦、鈦、鈷鎢等或其組合的一或多個層。金屬化圖案的導電材料可包括藉由化學氣相沈積、物理氣相沈積（physical vapor deposition，PVD）等而沈積的銅、鋁、鎢、銀及其組合等。可例如使用化學機械研磨（chemical mechanical polish，CMP）來移除位於金屬間介電質層上的任何過量的擴散障壁層及/或導電材料。
在圖2中，將包括內連線結構64的主體60單體化成各別的晶粒68。通常各晶粒68含有相同的電路系統（例如，元件及金屬化圖案）。儘管如此，各晶粒亦可具有不同的電路系統。所述單體化可包括鋸切（sawing）、切割（dicing）等。
晶粒68中的每一者可包括一或多個邏輯晶粒（例如，中央處理單元、圖形處理單元（graphics processing unit，GPU）、系統晶片（system-on-a-chip）、現場可程式化閘陣列（field-programmable gate array，FPGA）、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、電源管理晶粒（例如，電源管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency，RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end，AFE）晶粒）等或其組合。此外，在一些實施例中，晶粒68可為不同尺寸（例如，不同高度及/或表面積），且在其他實施例中，晶粒68可為相同尺寸（例如，相同高度及/或表面積）。
圖3示出形成組件96（參見圖21）的第一側。在加工期間，基底70包括一或多個組件96。組件96可為中介體或另一晶粒。基底70可為晶圓。基底70可包括塊狀半導體基底、絕緣層上半導體基底、多層式半導體基底等。基底70的半導體材料可為：矽；鍺；化合物半導體，包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用例如多層式基底或梯度基底（gradient substrate）等其他基底。基底70可為經摻雜的或未經摻雜的。可在基底70的第一表面72（其亦可稱作主動表面）中及/或在基底70的第一表面72上形成例如電晶體、電容器、電阻器、二極體等元件。在其中組件96為中介體的實施例中，一般在組件96中將不包括主動元件。儘管如此，中介體可包括形成於第一表面72中及/或第一表面72上的被動裝置。
在基底70的第一表面72之上形成重佈線結構76，重佈線結構76用於對各積體電路元件（若有）進行電性連接及/或將各所述積體電路元件電性連接至外部元件。重佈線結構76可包括一或多個介電層及位於所述介電層中的相應金屬化圖案。金屬化圖案可包括用於對任意元件進行內連及/或將所述任意元件內連至外部元件的通孔及/或跡線。金屬化圖案有時被稱作重佈線（Redistribution Line，RDL）。介電層可包含：氧化矽；氮化矽；碳化矽；氮氧化矽；低介電常數介電材料，例如磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、SiOx Cy 、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合等。介電層可藉由例如旋轉塗佈、化學氣相沈積、電漿增強型化學氣相沈積、高密度電漿化學氣相沈積等此項技術中所習知的任何適合的方法來沈積。可例如藉由以下方式在介電層中形成金屬化圖案：使用微影技術在所述介電層上沈積光阻材料並將所述光阻材料圖案化以暴露出所述介電層的將變成所述金屬化圖案的一些部分。可使用例如非等向性乾式蝕刻製程等蝕刻製程在介電層中形成與所述介電層的被暴露出的部分對應的凹陷部及/或開口。凹陷部及/或開口可被襯墊以擴散障壁層並被填充以導電材料。障壁層可包含藉由原子層沈積（atomic layer deposition，ALD）等而沈積的TaN、Ta、TiN、Ti、CoW等的一或多個層，且導電材料可包含藉由化學氣相沈積、物理氣相沈積、鍍覆製程等而沈積的銅、鋁、鎢、銀及其組合等。可例如使用化學機械研磨來移除位於介電層上的任何過量的擴散障壁層及/或導電材料。
在導電接墊上的重佈線結構76的頂表面處形成電性連接件（柱77/頂蓋層78）。在一些實施例中，導電接墊包括凸塊下金屬（under bump metallurgy，UBM）。在所示實施例中，接墊形成於重佈線結構76的介電層的開口中。在另一實施例中，接墊（凸塊下金屬）可延伸穿過重佈線結構76的介電層的開口且亦延伸跨越重佈線結構76的頂表面。作為形成接墊的實例，至少在重佈線結構76的介電層中的開口中形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。接著在晶種層上形成光阻並將所述光阻圖案化。所述光阻可藉由旋轉塗佈（spin coating）等來形成且可被暴露至光以進行圖案化。光阻的圖案對應於接墊。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。所述導電材料可藉由鍍覆（例如電鍍（electroplating）或無電鍍覆（electroless plating）等）來形成。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的一些部分。所述光阻可藉由例如使用氧電漿等的可接受的灰化製程（ashing process）或剝除製程（stripping process）來移除。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻（wet etching）或乾式蝕刻（dry etching））來移除晶種層的被暴露出的部分。晶種層的剩餘部分與導電材料形成接墊。在其中以不同方式形成接墊的實施例中，可利用更多的光阻及圖案化步驟。
在一些實施例中，電性連接件（柱77/頂蓋層78）包括金屬柱77，金屬柱77之上具有金屬頂蓋層78，金屬頂蓋層78可為焊料頂蓋。有時將包括柱77及頂蓋層78的電性連接件稱作微凸塊。在一些實施例中，金屬柱77包括例如銅、鋁、金、鎳、鈀、類似物或其組合等導電材料，且可藉由濺鍍（sputtering）、印刷、電鍍、無電鍍覆、化學氣相沈積等來形成。金屬柱77可為無焊料的（solder free）且具有實質上垂直的側壁。在一些實施例中，在金屬柱77的頂部上形成金屬頂蓋層78。金屬頂蓋層78可包含鎳、錫、錫-鉛、金、銅、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，且可藉由鍍覆製程來形成。
在另一實施例中，電性連接件不包括金屬柱，且電性連接件是例如受控塌陷晶片連接（controlled collapse chip connection，C4）、無電鍍鎳浸金（electroless nickel immersion Gold，ENIG）、無電鍍鎳鈀浸金技術（electroless nickel electroless palladium immersion gold technique，ENEPIG）形成的凸塊等焊料球及/或凸塊。在此實施例中，凸塊電性連接件可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合等導電材料。在此實施例中，電性連接件是藉由以下方式來形成：首先藉由例如蒸鍍（evaporation）、電鍍、印刷、焊料轉移（solder transfer）、植球（ball placement）等適合的方法形成焊料層。一旦已在結構上形成焊料層，則可執行回流（reflow）以將材料造形成所期望的凸塊形狀。
在圖4中，例如利用電性連接件（柱77/頂蓋層78）以及晶粒68及晶粒88上的金屬柱79藉由倒裝晶片結合（flip-chip bonding）而將各所述晶粒貼合至組件96的第一側以形成導電接點91。金屬柱79可相似於金屬柱77且本文中不再對其予以贅述。可使用例如拾取及放置工具（pick-and-place tool）將晶粒68及晶粒88放置於電性連接件（柱77/頂蓋層78）上。在一些實施例中，金屬頂蓋層78形成於金屬柱77上（如圖3中所示）、晶粒68及晶粒88的金屬柱79上、或金屬柱77與金屬柱79二者上。
晶粒88可藉由與以上參照晶粒68所述的加工相似的加工來形成。在一些實施例中，晶粒88包括一或多個記憶體晶粒，例如記憶體晶粒堆疊（例如，動態隨機存取記憶體晶粒、靜態隨機存取記憶體晶粒、高頻寬記憶體（High-Bandwidth Memory，HBM）晶粒、混合記憶體立方（Hybrid Memory Cube，HMC）晶粒等）。在記憶體晶粒堆疊實施例中，晶粒88可包括記憶體晶粒與記憶體控制器二者，例如（舉例而言，由四個或八個記憶體晶粒與記憶體控制器形成的堆疊）。此外，在一些實施例中，晶粒88可為不同尺寸（例如，不同高度及/或表面積），且在其他實施例中，晶粒88可為相同尺寸（例如，相同高度及/或表面積）。
在一些實施例中，晶粒88可具有與晶粒68（如圖4中所示）的高度相似的高度，或在一些實施例中，晶粒68與晶粒88可具有不同的高度。
晶粒88包括主體80、內連線結構84及晶粒連接件86。晶粒88的主體80可包括任何數目的晶粒、基底、電晶體、主動元件、被動元件等。在實施例中，主體80可包括塊狀半導體基底、絕緣層上半導體（SOI）基底、多層式半導體基底等。主體80的半導體材料可為：矽；鍺；化合物半導體，包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用例如多層式基底或梯度基底等其他基底。主體80可為經摻雜的或未經摻雜的。可在主動表面中及/或主動表面上形成例如電晶體、電容器、電阻器、二極體等元件。
在主動表面上形成包括一或多個介電層及相應金屬化圖案的內連線結構84。介電層中的金屬化圖案可例如使用通孔及/或跡線來在各元件之間路由電性訊號，且所述介電層中的所述金屬化圖案亦可含有例如電容器、電阻器、電感器等各種電性元件。所述各種元件與金屬化圖案可進行內連以執行一或多個功能。所述功能可包括記憶體結構、處理結構、感測器、放大器、功率分佈、輸入/輸出電路系統等。另外，在內連線結構84中及/或內連線結構64上形成例如導電柱（例如，包含例如銅等金屬）等晶粒連接件86以向所述電路系統及元件提供外部電性連接。在一些實施例中，晶粒連接件86自內連線結構84突出以形成欲在將晶粒88結合至其他結構時使用的柱結構。此項技術中具有通常知識者應知，提供以上實例是用於說明的目的。可使用適宜於給定應用的其他電路系統。
更具體而言，可在內連線結構84中形成金屬間介電質層。可藉由例如旋轉塗佈、化學氣相沈積、電漿增強型化學氣相沈積、高密度電漿化學氣相沈積等此項技術中所習知的任何適合的方法以例如以下材料來形成金屬間介電質層：低介電常數介電材料，例如磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、SiOx Cy 、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合等。可例如藉由以下方式在金屬間介電質層中形成金屬化圖案：使用微影技術在所述金屬間介電質層上沈積光阻材料並將所述光阻材料圖案化以暴露出所述金屬間介電質層的將變成所述金屬化圖案的一些部分。可使用例如非等向性乾式蝕刻製程等蝕刻製程在金屬間介電質層中形成與所述金屬間介電質層的被暴露出的部分對應的凹陷部及/或開口。凹陷部及/或開口可被襯覆以擴散障壁層並被填充以導電材料。擴散障壁層可包括藉由原子層沈積等而沈積的氮化鉭、鉭、氮化鈦、鈦、鈷鎢等或其組合的一或多個層。金屬化圖案的導電材料可包括藉由化學氣相沈積、物理氣相沈積等而沈積的銅、鋁、鎢、銀及其組合等。可例如使用化學機械研磨來移除位於金屬間介電質層上的任何過量的擴散障壁層及/或導電材料。
在其中晶粒連接件66及晶粒連接件86分別自內連線結構64及內連線結構84突出的實施例中，晶粒68及晶粒68可不包括金屬柱79，乃因所述突出的晶粒連接件66及晶粒連接件86可用作金屬頂蓋層78的柱。
導電接點91經由內連線結構84及內連線結構64以及晶粒連接件86及晶粒連接件66將晶粒68及晶粒88中的電路分別電性耦合至組件96中的重佈線結構76。
在一些實施例中，在結合電性連接件（柱77/頂蓋層78）之前，使用例如免清洗焊劑（no-clean flux）等焊劑（圖中未示出）塗佈電性連接件（柱77/頂蓋層78）。可將電性連接件（柱77/頂蓋層78）浸入焊劑中或可將所述焊劑噴射至電性連接件（柱77/頂蓋層78）上。在另一實施例中，亦可將焊劑塗覆至電性連接件（柱79/頂蓋層78）。在一些實施例中，在電性連接件（柱77/頂蓋層78）及/或電性連接件（柱79/頂蓋層78）被回流之前電性連接件（柱77/頂蓋層78）及/或電性連接件（柱79/頂蓋層78）上可形成有環氧樹脂焊劑（圖中未示出），所述環氧樹脂焊劑的環氧樹脂部分中的至少一些部分將在晶粒68及晶粒88貼合至組件96之後存留。此一存留的環氧樹脂部分可充當底部填充膠（underfill）以減小應力並保護因回流電性連接件（柱77/頂蓋層78/柱79）而得到的接點。
晶粒68及晶粒88與組件96之間的結合可為焊料結合或直接金屬-金屬（例如銅-銅或錫-錫）結合。在實施例中，藉由回流製程來將晶粒68及晶粒88結合至組件96。在此回流製程期間，電性連接件（柱77/頂蓋層78/柱79）分別接觸晶粒連接件66及晶粒連接件86，且重佈線結構76的接墊將晶粒68及晶粒88實體地耦合至且電性耦合至組件96。在結合製程之後，在金屬柱77及金屬柱79與金屬頂蓋層78的介面處可形成金屬間介電質層（圖中未示出）。
在圖4及後續各圖中，示出分別用於形成第一封裝及第二封裝的第一封裝區90及第二封裝區92。切割道區94位於鄰近的封裝區之間。如圖4中所示，在第一封裝區90及第二封裝區92中的每一者中貼合第一晶粒及多個第二晶粒。
在一些實施例中，晶粒68為系統晶片（SoC）或圖形處理單元（GPU），且第二晶粒為可被晶粒68利用的記憶體晶粒。在實施例中，晶粒88為堆疊記憶體晶粒。舉例而言，堆疊記憶體晶粒88可包括低功率（low-power，LP）雙倍資料速率（double data rate，DDR）記憶體模組，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似的記憶體模組。
在圖5中，向晶粒68、晶粒88、及重佈線結構76之間的間隙中分配底部填充膠材料100。底部填充膠材料100可沿晶粒68及晶粒88的側壁向上延伸。底部填充膠材料100可為例如聚合物、環氧樹脂、模塑底部填充膠等任何可接受的材料。底部填充膠材料100可在貼合晶粒68及晶粒88之後藉由毛細流動製程（capillary flow process）來形成，或者可在貼合晶粒68及晶粒88之前藉由適合的沈積方法來形成。
圖7至圖20示出形成組件96的第二側以及延伸穿過組件96（參見圖20）的基底70的穿孔（through via，TV）128。在圖7中，將圖6所示結構翻轉以準備形成組件96的第二側。可將所述結構放置於載體基底200上或其他適合於圖7至圖20所示製程的支撐結構上。
載體基底200可為玻璃載體基底、陶瓷載體基底等。可藉由離型層202將圖6所示結構貼合至載體基底200。離型層202可由聚合物系材料形成，所述聚合物系材料可與載體基底200一起自上覆結構被移除。在一些實施例中，離型層202為會在受熱時失去其黏合性質的環氧樹脂系熱釋放材料，例如光熱轉換（light-to-heat-conversion，LTHC）釋放塗層。在其他實施例中，離型層202可為會在暴露至紫外（ultra-violet，UV）光時失去其黏合性質的紫外膠（UV glue）。離型層202可作為液體形態被分配並固化，可為疊層至載體基底200上的疊層體膜（laminate film）或可為類似材料。
如圖7中所示，在此加工階段處，組件96的基底70與重佈線結構76具有介於自約50微米（μm）至約775微米範圍內的組合厚度T1。在圖8中，對基底70的第二側執行薄化製程（thinning process）以將基底70薄化。所述薄化製程可包括蝕刻製程、磨製製程（grinding process）等或其組合。在一些實施例中，在薄化製程之後，組件96的基底70與重佈線結構76具有介於自約30微米至約200微米範圍內（例如約100微米）的組合厚度T2。
圖9至圖19示出形成延伸穿過組件96的基底70的穿孔128的各種中間階段。穿孔128亦可被稱作電性連接件（例如，微凸塊），其使得組件96能夠在後續加工步驟中結合至封裝基底（參見圖21）。圖9至圖19示出圖8所示結構的區域250（參見圖8）的詳細剖視圖。
參照圖9，示出區域250的細節。區域250包括如上所述的基底70的一部分及重佈線結構76的一部分。舉例而言，重佈線結構76包括金屬間介電質層104，金屬間介電質層104可包含如上所述的低介電常數介電材料（例如，未經摻雜的矽酸鹽玻璃）。在金屬間介電質層104內形成金屬化圖案102。在一些實施例中，金屬化圖案102為導電線（例如，包含銅、鋁、鎢、銀及其組合），所述導電線在晶粒68、晶粒88及/或封裝基底300（參見圖21）之間提供電性路由。
可在金屬化圖案102與基底70之間設置絕緣緩衝層108。在一些實施例中，絕緣緩衝層108在金屬化圖案102與基底70之間提供電性隔離。在一些實施例中，絕緣緩衝層108包含低介電常數介電材料，例如未經摻雜的矽酸鹽玻璃（USG）、磷矽酸鹽玻璃（PSG）、硼磷矽酸鹽玻璃（BPSG）、氟矽酸鹽玻璃（FSG）、SiOx Cy 、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合等。絕緣緩衝層108可藉由例如旋轉塗佈、化學氣相沈積、電漿增強型化學氣相沈積、高密度電漿化學氣相沈積等此項技術中所習知的任何適合的方法來沈積。絕緣緩衝層108的材料與金屬間介電質層104的材料可相同或不同。可在金屬間介電質層104與絕緣緩衝層108之間設置蝕刻終止層106（例如，氮化矽等）。蝕刻終止層106可藉由例如旋轉塗佈、化學氣相沈積、電漿增強型化學氣相沈積、高密度電漿化學氣相沈積等此項技術中所習知的任何適合的方法來沈積。可在製造金屬化圖案102期間使用蝕刻終止層106來提供用於在金屬間介電質層104中蝕刻出開口的終止點（end point）。如圖9中所示，金屬化圖案102亦延伸穿過蝕刻終止層106。因此，作為形成金屬化圖案102的一部份，亦可使用適合的微影及蝕刻製程將蝕刻終止層106圖案化。
在圖10中，在基底70的背側上沈積絕緣層110。舉例而言，絕緣層110可設置於基底70的與金屬化圖案102及金屬間介電質層104相對的側上。在一些實施例中，絕緣層110包含例如氮化矽、氧化矽、氮氧化矽等含矽絕緣體。絕緣層110可藉由例如旋轉、化學氣相沈積、電漿增強型化學氣相沈積、高密度電漿化學氣相沈積等此項技術中所習知的任何適合的方法來沈積。絕緣層110的厚度可介於約0.4微米至約1.0微米範圍內。
在圖11中，穿過絕緣層110、基底70、及絕緣緩衝層108圖案化出開口112。為易於說明，在區域250中示出一個開口112，且應理解，可穿過圖8所示結構中的絕緣層110、基底70、及絕緣緩衝層108同時地圖案化出多個開口112。可使用例如微影與蝕刻的組合穿過絕緣層110、基底70、及絕緣緩衝層108依序地圖案化出開口112。舉例而言，可藉由旋轉塗佈等在絕緣層110之上沈積光阻（圖中未示出）。在沈積之後，接著例如藉由以下方式來將光阻圖案化：在光阻之上放置圖案化光罩，使用所述光罩暴露出所述光阻的一些部分，且將所述光阻顯影以移除所述光阻的被暴露出的部分或未被暴露出的部分（根據使用的是正型光阻（positive tone resist）還是負型光阻（negative tone resist））。光阻的圖案對應於開口112的圖案。接著使用光阻作為遮罩來依序地蝕刻絕緣層110、基底70、及絕緣緩衝層108。蝕刻製程的類型可相依於絕緣層110、基底70、及絕緣緩衝層108的材料。舉例而言，由於基底70及絕緣層110/絕緣緩衝層108是由不同材料製成，因此可使用不同的蝕刻製程。舉例而言，為蝕刻絕緣層110，可使用乾式蝕刻製程。乾式蝕刻製程的示例性蝕刻劑（etchant）包括SF6 等。作為另一實例，為蝕刻基底70，可使用乾式蝕刻製程。乾式蝕刻製程的示例性蝕刻劑包括SF6 等。作為另一實例，為蝕刻絕緣緩衝層108，可使用乾式蝕刻製程及/或濕式蝕刻製程。乾式蝕刻製程的示例性蝕刻劑包括SF6 等。濕式蝕刻製程的示例性蝕刻劑包括氟化氫等。
此外，作為使用不同蝕刻製程的結果，開口112在絕緣層110、基底70、及絕緣緩衝層108中的寬度可不相同。舉例而言，開口112在絕緣層110中的寬度W2可大於開口112在基底70及絕緣緩衝層108中的寬度W1。在一些實施例中，寬度W1介於約15微米至約30微米範圍內，且寬度W2介於約15.1微米至約30.3微米範圍內。在其他實施例中，開口112在絕緣層110中的寬度W2可等於開口112在基底70及絕緣緩衝層108中的寬度W1。此外，開口112可在基底70中具有側壁112A及側壁112B，且開口112可在絕緣層110中具有側壁112C。在一些實施例中，側壁112B將側壁112A直接連接至側壁112C。相對於基底70的主表面而言，側壁112B可以與側壁112A及側壁112C不同的角度進行設置。舉例而言，相對於基底70的主表面而言，側壁112B的斜率可小於側壁112A及側壁112C的相應斜率。
可在圖案化製程中使用其他層以形成開口112。舉例而言，可使用一或多個可選硬遮罩層來將絕緣層110、基底70、及絕緣緩衝層108圖案化。一般而言，在其中蝕刻製程需要除由光阻材料提供的遮罩（masking）以外的遮罩的實施例中，一或多個硬遮罩層可為有用的。儘管光阻材料的蝕刻速率可能不與絕緣層110、基底70、及絕緣緩衝層108的蝕刻速率一樣高，然而在用於將絕緣層110、基底70圖案化的後續蝕刻製程期間，圖案化光阻遮罩亦將被蝕刻。若蝕刻製程使得圖案化光阻遮罩可在完成對絕緣層110、基底70、及絕緣緩衝層108進行的蝕刻製程之前被消耗掉，則可使用附加的硬遮罩。一或多個硬遮罩層的材料被選擇成使得所述硬遮罩層表現出較下伏材料（例如，絕緣層110、基底70、及/或絕緣緩衝層108的材料）低的蝕刻速率。在圖案化出開口112之後，可移除選擇性使用的硬遮罩層及光阻的任何剩餘殘餘物。
在圖12中，在絕緣層110之上且沿開口112的側壁及底表面沈積絕緣層114。在一些實施例中，絕緣層114包含例如氮化矽、氧化矽、氮氧化矽等含矽絕緣體。絕緣層114的材料可與絕緣層110的材料相同或可不與絕緣層110的材料相同。即便在其中絕緣層114與絕緣層110是由相同材料製成的實施例中，仍可因用於形成絕緣層110及絕緣層114的單獨的沈積製程而在絕緣層110與絕緣層114之間形成介面。絕緣層114可藉由例如化學氣相沈積、電漿增強型化學氣相沈積、高密度電漿化學氣相沈積等此項技術中所習知的任何適合的方法來沈積。在一些實施例中，絕緣層114是使用共形沈積製程（conformal deposition process）來沈積，使得絕緣層114的橫向部分（例如，位於開口112的底表面外及所述底表面之上的部分）的厚度實質上等於絕緣層114的垂直部分（例如，沿著開口112的側壁的一些部分）的厚度。絕緣層114的厚度可介於約1微米至約5微米範圍內。
接下來參照圖13，使用適合的蝕刻製程來移除絕緣層114的橫向部分。在一些實施例中，蝕刻可為非等向性的（例如，在由箭頭150指示的方向上為定向的（directional））。示例性非等向性蝕刻製程包括進行使用SF6 等作為蝕刻劑的乾式蝕刻製程。作為非等向性蝕刻製程的結果，絕緣層114的橫向部分被移除，而絕緣層114的垂直部分（例如，位於開口112的側壁上的一些部分）則存留下來。因此，使得沿開口112的側壁112A、112B、及112C形成側壁間隔壁114'。舉例而言，側壁間隔壁114'可形成與絕緣層110的側壁之間的介面及與基底70的側壁之間的介面。側壁間隔壁114'可在俯視圖（未提供）中具有環形形狀（annular shape）。
將絕緣層114圖案化以界定側壁間隔壁114'可能不需要使用任何微影製程或遮罩層。舉例而言，由於在形成絕緣層114之前已形成絕緣層110並將絕緣層110圖案化，因此可使用定向蝕刻製程（directional etching process）來跨越包括基底70的整個晶圓將絕緣層114圖案化，而無需遮罩住所述晶圓的不同區域。可使用定時蝕刻製程（timed etching process），以使所述結構包括被絕緣材料（例如，絕緣層110及側壁間隔壁114'）沿頂表面及側壁覆蓋的基底70。因此，可降低製造成本。
在圖14中，沈積應力緩衝層116。應力緩衝層116可藉由例如化學氣相沈積、電漿增強型化學氣相沈積、高密度電漿化學氣相沈積等此項技術中所習知的任何適合的方法來沈積。在一些實施例中，應力緩衝層116是使用共形沈積製程來沈積，使得應力緩衝層116的橫向部分（例如，位於開口112的底表面外及所述底表面之上的部分）的厚度實質上等於應力緩衝層116的垂直部分（例如，沿著開口112的側壁的部分）的厚度。在其他實施例中，應力緩衝層116可使用例如旋轉塗佈等非共形製程（non-conformal process）來沈積。應力緩衝層116可包含與絕緣層110及側壁間隔壁114'不同的材料。舉例而言，在一些實施例中，應力緩衝層116包含例如聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）等聚合物。在一些實施例中，應力緩衝層116作為感光性層而沈積，而絕緣層110及側壁間隔壁114'不作為感光性層而沈積。儘管圖14將應力緩衝層116示作單層，然而在其他實施例中，應力緩衝層116可為包括例如多個經堆疊聚合物層的多層式結構。在此種實施例中，所述多個經堆疊聚合物層中的每一者可包含不同的材料。
在圖15中，將應力緩衝層116圖案化以移除應力緩衝層116的位於開口112中的一些部分且使開口112延伸至應力緩衝層116中。將應力緩衝層116圖案化可更使得暴露出絕緣層110的一些部分。將應力緩衝層116圖案化可使用任何適合的製程來執行。舉例而言，當應力緩衝層116包含感光性材料（例如，聚苯並惡唑）時，應力緩衝層116可使用光微影製程（lithography process）來圖案化。在此種實施例中，在圖案化之後，可在圖案化之後對應力緩衝層116執行固化以使應力緩衝層116硬化。在一些實施例中，應力緩衝層116可包含具有相對低的固化溫度（例如，小於約200℃）的聚合物以減少所述結構的其他組件（例如，晶粒68及晶粒88（參見圖8））在高溫下的暴露且減少在固化期間對該些組件造成損壞的風險。在固化之後，應力緩衝層116可不再為感光性的。在其他實施例中，應力緩衝層116不被沈積成感光性層，且可利用微影與蝕刻的組合、使用一或多個遮罩將應力緩衝層116圖案化。
在圖16至圖18A及圖18B中，穿過開口112形成導電特徵。作為形成導電特徵的實例，在應力緩衝層116之上且沿圖16中的開口112的側壁/底表面形成晶種層118。在一些實施例中，晶種層118為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。
接下來，在圖17中，在晶種層118上形成光阻120並將光阻120圖案化。所述光阻可被圖案化成包括開口122，開口122暴露出晶種層118的位於開口112中的一些部分。晶種層118的位於應力緩衝層116之上的至少一部分亦可在開口122中暴露出。光阻的圖案對應於後續形成的導電特徵（例如，導電特徵124（參見圖18A））的圖案。
在圖18A中，在開口112（參見圖17）中及位於晶種層118的被暴露出的部分上的開口122（參見圖17）中形成導電特徵124。導電特徵124可藉由鍍覆（例如電鍍或無電鍍覆等）來形成。導電特徵124可包括金屬，如銅、鈦、鎢、鋁等。在形成導電特徵124之後，移除光阻120（參見圖17）以及晶種層118的上面未形成有導電特徵124的一些部分。光阻120可藉由例如使用氧電漿等的可接受的灰化製程或剝除製程來移除。一旦光阻120被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層118的被暴露出的部分。在俯視圖（參見圖18B）中，所得導電特徵124可具有圓形形狀（circular shape）或長圓形狀（ovular shape）。在其他實施例中，亦預期存在導電特徵124的其他形狀。在俯視圖中，側壁間隔壁114'（圖18B中未示出）可包圍導電特徵，將所述導電特徵與基底70實體地隔開且使所述導電特徵與基底70絕緣。
在圖19中，在導電特徵124之上形成焊料區126。在一些實施例中，焊料區126是藉由以下方式來形成：首先藉由例如蒸鍍、電鍍、印刷、焊料轉移、植球等適合的方法形成焊料層。一旦已在導電特徵124上形成焊料層，則可執行回流以將材料造形成所期望的凸塊形狀。
因此，使得形成延伸穿過應力緩衝層116、絕緣層110、及基底70的穿孔128。穿孔128包括焊料區126、導電特徵124、及晶種層118。在各種實施例中，穿孔128電性連接至金屬間介電質層104中的金屬化圖案102。絕緣層110及側壁間隔壁114'使穿孔128與基底70以及延伸穿過基底70的其他穿孔128（參見圖20）電性絕緣。在一些實施例中，穿孔128亦充當微凸塊，所述微凸塊可用於將基底70結合至另一封裝特徵（例如，封裝基底300（參見圖21））。此外，側壁間隔壁114'的材料使得側壁間隔壁114'可為穿孔128提供得到改善的結構性支撐。因此，當穿孔128結合至另一封裝特徵（例如，熱製程）時，可減少製造缺陷（例如，穿孔128的變形）。在後續測試循環（例如，可靠性應力測試）中，可相似地減少製造缺陷。
圖20示出在形成穿孔128之後包括基底70的晶圓的縮小圖。穿孔128中的每一者是使用以上參照圖9至圖19所述的製程來形成。如由圖20所示，藉由重佈線結構76中的金屬化圖案將穿孔128電性連接至晶粒68及晶粒88。
如進一步由圖20所示，執行載體剝離（carrier de-bonding）以將載體基底200自晶粒68、晶粒88、及模塑化合物（光阻120）拆離（剝離）。根據一些實施例，所述剝離包括在離型層202上投射例如雷射光或紫外光等光，以使得離型層202在所述光的熱量作用下分解，且載體基底200可被移除。接著將所述結構翻轉並放置於膠帶（圖中未示出）上。隨後，在鄰近的區（第一封裝區90與第二封裝區92）之間沿切割道區94單體化出組件96以形成組件封裝204，組件封裝204包括晶粒68、組件96、及晶粒88等。所述單體化可藉由鋸切、切割等來進行。
圖21示出將組件封裝204貼合於基底300上，以形成半導體元件封裝400。將穿孔128對齊至基底300的結合接墊302，穿孔128被置放成靠著結合接墊302。可對穿孔128進行回流以在基底300與組件96之間形成結合件（bond）。基底300可包括封裝基底，例如其中包括芯體（core）的增層基底（build-up substrate）、包括多個疊層介電膜的疊層體基底、印刷電路板（printed circuit board，PCB）等。基底300可包括與組件封裝相對的例如焊料球等電性連接件（圖中未示出）以使得基底300能夠安裝至另一元件。可分配底部填充膠材料（圖中未示出），以使底部填充膠材料位於組件封裝204與基底300之間且環繞穿孔128的自基底70、絕緣層110、及應力緩衝層116突出的一些部分。所述底部填充膠材料可為例如聚合物、環氧樹脂、模塑底部填充膠等任何可接受的材料。
在一些實施例中，包括應力緩衝層116是為了吸收因組件封裝204與基底300之間的結合製程而造成的應力。此外，如上所述，側壁間隔壁114'及絕緣層110可包含使得在熱製程（例如，將組件封裝204結合至基底300）期間使穿孔128的變形減小的材料。
另外，可將一或多個表面元件304連接至基底300。表面元件304可用於向組件封裝204或整個所述封裝提供附加的功能性或程式設計。在實施例中，表面元件304可包括表面安裝元件（surface mount device，SMD）或積體被動元件（integrated passive device，IPD），所述積體被動元件（IPD）包括例如電阻器、電感器、電容器、跨接線（jumper）、該些的組合等期望連接至組件封裝204（或所述封裝的其他部份）並與組件封裝204（或所述封裝的所述其他部份）結合使用的被動元件。根據各種實施例，表面元件304可放置於基底300的第一主表面上、基底300的相對主表面上、或所述第一主表面與所述相對主表面二者上。
亦可包括其他特徵及製程。舉例而言，可包括測試結構，以幫助對三維封裝或三維積體電路元件進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試接墊，以容許對三維封裝或三維積體電路進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合包括對已知良好晶粒（known good die）進行中間驗證的測試方法而使用，以提高良率並降低成本。
本發明中的元件及方法的實施例具有諸多優點。舉例而言，組件（例如，組件96）的半導體基底（例如，基底70）可在製造期間被薄化。由於半導體基底是薄的，因此延伸穿過所述半導體基底的導電通孔（例如，穿孔128）在元件封裝的熱加工（例如，對封裝基底進行的可靠性/應力測試、回流/結合等）期間變形（例如，分層）的風險加大。各種實施例在導電通孔的側壁上提供絕緣間隔壁（例如，側壁間隔壁114'）以提高所述導電通孔的剛性且減少製造缺陷。在一些實施例中，絕緣間隔壁可使導電通孔與中介體的半導體基底絕緣且為所述導電通孔提供得到增進的結構支撐，此減少後續熱製程（例如，結合及/或可靠性測試）期間的製造缺陷（manufacturing defect）。
根據實施例，一種半導體元件封裝的製造方法包括：將第一晶粒結合至中介體的第一側，所述中介體包括基底；在中介體的與第一側相對的第二側上沈積第一絕緣層；穿過基底及第一絕緣層而圖案化出開口；在第一絕緣層之上以及沿開口的側壁及橫向表面沈積第二絕緣層，所述第二絕緣層包括矽；移除第二絕緣層的橫向部分，以在開口的側壁上界定側壁間隔壁；以及在開口中形成穿孔，其中所述穿孔電性連接至第一晶粒。在實施例中，在將第一晶粒結合至中介體的第一側時所述中介體是晶圓的組件，且所述半導體元件封裝的製造方法更包括：在開口中形成穿孔之後，自所述晶圓單體化出所述中介體。在實施例中，移除第二絕緣層的橫向部分包括進行不使用任何圖案化遮罩的非等向性蝕刻製程。在實施例中，移除第二絕緣層的橫向部分使得暴露出第一絕緣層。在實施例中，第一絕緣層及第二絕緣層是由相同的材料製成且所述第一絕緣層及所述第二絕緣層各自包括氮化矽。在實施例中，所述半導體元件封裝的製造方法更包括：在開口中形成穿孔之前，在第一絕緣層之上形成應力緩衝層；應力緩衝層包括與第一絕緣層及第二絕緣層不同的材料。在實施例中，形成穿孔包括：沿開口的側壁及底表面沈積晶種層；在晶種層上鍍覆導電特徵，其中所述導電特徵延伸穿過基底及第一絕緣層；以及在導電特徵的與晶種層相對的表面上形成焊料區。在實施例中，所述半導體元件封裝的製造方法更包括將中介體結合至封裝基底；焊料區直接結合至封裝基底的接觸接墊。
根據實施例，一種半導體元件封裝的製造方法包括：將第一晶粒及第二晶粒結合至中介體，所述中介體包括：重佈線結構，包括將第一晶粒電性連接至第二晶粒的一或多個金屬化圖案；以及基底，位於重佈線結構的與第一晶粒及第二晶粒相對的側上。所述半導體元件封裝的製造方法更包括在所述基底的與重佈線結構相對的表面上沈積第一含矽絕緣層；圖案化出延伸穿過第一含矽絕緣層及基底的第一開口，所述第一開口暴露出所述一或多個金屬化圖案的第一金屬化圖案；沿第一開口的側壁形成側壁間隔壁，所述側壁間隔壁包括含矽絕緣材料；形成電性連接件，所述電性連接件延伸穿過第一開口且電性連接至第一金屬化圖案；以及使用電性連接件將封裝基底結合至中介體。在實施例中，所述半導體元件封裝的製造方法更包括：在形成側壁間隔壁之後，在第一含矽絕緣層之上沈積絕緣緩衝層，所述絕緣緩衝層包括聚合物；以及使第一開口延伸至絕緣緩衝層中。在實施例中，形成側壁間隔壁包括：在第一含矽絕緣層之上、沿第一開口的側壁以及在所述第一開口的底表面之上沈積第二含矽絕緣層；以及使用非等向性蝕刻製程將第二含矽絕緣層圖案化，以移除所述第二含矽絕緣層的橫向部分並界定側壁間隔壁。在實施例中，側壁間隔壁形成與基底之間的第一介面以及與第一含矽絕緣層之間的第二介面，所述第一介面在側向上與所述第二介面間隔開。在實施例中，側壁間隔壁形成與基底之間的第三介面，所述第三介面設置於第一介面與第二介面之間，相對於所述基底的主表面而言，所述第三介面的斜率小於所述第一介面的斜率以及所述第二介面的斜率。在實施例中，第一含矽絕緣層包括氮化矽、氧化矽、或氮氧化矽，且側壁間隔壁包括氮化矽、氧化矽、或氮氧化矽。在實施例中，形成電性連接件包括：沿側壁間隔壁的側壁以及在第一金屬化圖案之上沈積晶種層；鍍覆導電特徵，所述導電特徵自晶種層延伸至第一開口外；以及在導電特徵上形成焊料區。在實施例中，所述方法更包括：在第一晶粒與中介體之間分配底部填充膠，所述底部填充膠更在第二晶粒與所述中介體之間延伸；以及將第一晶粒、第二晶粒、及底部填充膠包封於模塑化合物中。在實施例中，圖案化出延伸穿過第一含矽絕緣層及基底的第一開口包括圖案化出在所述第一含矽絕緣層中較在所述基底中寬的所述第一開口。
根據實施例，一種半導體元件封裝包括：第一晶粒，結合至中介體，所述中介體包括：金屬化圖案，電性連接至第一晶粒；以及基底，位於金屬化圖案的與第一晶粒相對的側上。所述封裝更包括：含矽絕緣層，位於基底的與金屬化圖案相對的表面上；聚合物層，位於含矽絕緣層的與基底相對的側上；穿孔，穿過聚合物層、含矽絕緣層及基底延伸至金屬化圖案；以及含矽側壁間隔壁，位於穿孔與基底之間，所述含矽側壁間隔壁更設置於所述穿孔與含矽絕緣層之間。在實施例中，含矽側壁間隔壁形成與含矽絕緣層之間的第一介面，且由與含矽絕緣層相同的材料製成。在實施例中，含矽側壁間隔壁形成與基底之間的第二介面，第一介面在側向上與所述第二介面間隔開。在實施例中，穿孔包括：導電特徵，延伸穿過聚合物層、含矽絕緣層、及基底；以及焊料區，位於導電特徵的與金屬化圖案相對的側上，其中所述焊料區直接結合至封裝基底的接觸接墊。在實施例中，含矽側壁間隔壁包含氧化矽、氮化矽、或氮氧化矽。
根據實施例，一種半導體元件封裝包括：第一晶粒及第二晶粒，所述第一晶粒及所述第二晶粒結合至封裝組件，所述封裝組件包括：重佈線結構，包括在第一晶粒與第二晶粒之間提供電性路由的金屬化圖案的一或多個層；以及基底，位於重佈線結構的與第一晶粒及第二晶粒相對的側上。所述半導體元件封裝更包括：第一絕緣層，位於基底的與重佈線結構相對的側上，所述第一絕緣層包含氮化矽、氧化矽、或氮氧化矽；側壁間隔壁，所述側壁間隔壁沿著第一絕緣層的側壁及基底的側壁，其中所述側壁間隔壁包括氮化矽、氧化矽、或氮氧化矽；以及電性連接件，延伸穿過第一絕緣層及基底，側壁間隔壁使所述電性連接件與基底絕緣，其中所述電性連接件電性連接至金屬化圖案中的第一金屬化圖案。在實施例中，所述封裝更包括第二絕緣層，所述第二絕緣層位於第一絕緣層的與基底相對的側上，所述第二絕緣層包含與所述第一絕緣層不同的材料。在實施例中，側壁間隔壁包括：第一側壁，在第一絕緣層中具有第一斜率；第二側壁，在基底中具有第二斜率；以及第三側壁，將第一側壁連接至第二側壁。相對於基底的主表面而言，所述第三側壁具有較第一斜率及第二斜率小的第三斜率。在實施例中，所述封裝組件是不含有任何主動元件的中介體。
根據實施例，一種中介體包括：金屬化圖案，位於第一介電層中；基底，位於第一介電層之上；第一絕緣層，位於基底之上，所述第一絕緣層包含氮化矽、氧化矽、或氮氧化矽；側壁間隔壁，所述側壁間隔壁沿著第一絕緣層的側壁及基底的側壁，其中所述側壁間隔壁包含氮化矽、氧化矽、或氮氧化矽。所述側壁間隔壁包括：第一側壁，在第一絕緣層中具有第一斜率；第二側壁，在基底中具有第二斜率；以及第三側壁，將第一側壁連接至第二側壁，相對於基底的主表面而言，所述第三側壁具有較第一斜率及第二斜率小的第三斜率；以及電性連接件，延伸穿過第一絕緣層及基底，側壁間隔壁設置於所述電性連接件與所述基底之間。電性連接件電性連接至金屬化圖案。在實施例中，中介體更包括第二絕緣層，所述第二絕緣層位於第一絕緣層與第一介電層之間，側壁間隔壁延伸穿過所述第二絕緣層。
根據實施例，一種半導體元件封裝的製造方法包括：在不含有任何主動元件的中介體的基底之上沈積第一絕緣層，所述第一絕緣層設置於所述基底的與重佈線結構相對的側上；穿過基底及第一絕緣層圖案化出開口；在第一絕緣層之上且沿開口的側壁及橫向表面沈積第二絕緣層，其中所述第二絕緣層包含氧化矽、氮化矽、或氮氧化矽；移除第二絕緣層的橫向部分以在開口的側壁上界定側壁間隔壁；以及在開口中形成外部連接件，其中所述外部連接件電性連接至重佈線結構中的金屬化圖案。在實施例中，所述方法更包括：將第一晶粒結合至中介體的第一側並將封裝基底結合至所述中介體的與所述第一側相對的第二側，外部連接件的焊料區直接結合至所述封裝基底的接觸接墊。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。
60、80‧‧‧主體
62‧‧‧主動表面
64、84‧‧‧內連線結構
66、86‧‧‧晶粒連接件
68‧‧‧晶粒
70‧‧‧基底
72‧‧‧第一表面
76‧‧‧重佈線結構
77、79‧‧‧柱
78‧‧‧頂蓋層
88‧‧‧晶粒
90‧‧‧第一封裝區
91‧‧‧導電接點
92‧‧‧第二封裝區
94‧‧‧切割道區
96‧‧‧組件
100‧‧‧底部填充膠材料
102‧‧‧金屬化圖案
104‧‧‧金屬間介電質層
106‧‧‧蝕刻終止層
108‧‧‧絕緣緩衝層
110、114‧‧‧絕緣層
112、122‧‧‧開口
112A、112B、112C‧‧‧側壁
114'‧‧‧側壁間隔壁
116‧‧‧應力緩衝層
118‧‧‧晶種層
120‧‧‧光阻
124‧‧‧導電特徵
126‧‧‧焊料區
128‧‧‧穿孔
150‧‧‧方向
200‧‧‧載體基底
202‧‧‧離型層
204‧‧‧組件封裝
250‧‧‧區域
300‧‧‧基底
302‧‧‧結合接墊
304‧‧‧表面元件
400‧‧‧半導體元件封裝
T1、T2‧‧‧組合厚度
W1、W2‧‧‧寬度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖17、圖18A、圖18B、及圖19至圖21示出根據一些實施例的製造半導體元件封裝的各中間階段的剖視圖及俯視圖。

Claims (20)

  1. 一種半導體元件封裝的製造方法，包括： 將第一晶粒結合至中介體的第一側，所述中介體包括基底； 在所述中介體的與所述第一側相對的第二側上沈積第一絕緣層； 穿過所述基底及所述第一絕緣層而圖案化出開口； 在所述第一絕緣層之上以及沿所述開口的側壁及橫向表面沈積第二絕緣層，所述第二絕緣層包括矽； 移除所述第二絕緣層的橫向部分，以在所述開口的側壁上界定側壁間隔壁；以及 在所述開口中形成穿孔，其中所述穿孔電性連接至所述第一晶粒。
  2. 如申請專利範圍第1項所述的半導體元件封裝的製造方法，其中在將所述第一晶粒結合至所述中介體的所述第一側時所述中介體是晶圓的組件，且其中所述半導體元件封裝的製造方法更包括：在所述開口中形成所述穿孔之後，自所述晶圓單體化出所述中介體。
  3. 如申請專利範圍第1項所述的半導體元件封裝的製造方法，其中移除所述第二絕緣層的所述橫向部分包括進行不使用任何圖案化遮罩的非等向性蝕刻製程。
  4. 如申請專利範圍第1項所述的半導體元件封裝的製造方法，其中移除所述第二絕緣層的所述橫向部分使得暴露出所述第一絕緣層。
  5. 如申請專利範圍第1項所述的半導體元件封裝的製造方法，其中所述第一絕緣層及所述第二絕緣層是由相同的材料製成且所述第一絕緣層及所述第二絕緣層各自包括氮化矽。
  6. 如申請專利範圍第1項所述的半導體元件封裝的製造方法，更包括：在所述開口中形成穿孔之前，在所述第一絕緣層之上形成應力緩衝層，其中所述應力緩衝層包括與所述第一絕緣層及所述第二絕緣層不同的材料。
  7. 如申請專利範圍第1項所述的半導體元件封裝的製造方法，其中形成所述穿孔包括： 沿所述開口的側壁及底表面沈積晶種層； 在所述晶種層上鍍覆導電特徵，其中所述導電特徵延伸穿過所述基底及所述第一絕緣層；以及 在所述導電特徵的與所述晶種層相對的表面上形成焊料區。
  8. 如申請專利範圍第7項所述的半導體元件封裝的製造方法，更包括將所述中介體結合至封裝基底，其中所述焊料區直接結合至所述封裝基底的接觸接墊。
  9. 一種半導體元件封裝的製造方法，包括： 將第一晶粒及第二晶粒結合至中介體，所述中介體包括： 重佈線結構，包括將所述第一晶粒電性連接至所述第二晶粒的一或多個金屬化圖案；以及 基底，位於所述重佈線結構的與所述第一晶粒及所述第二晶粒相對的側上； 在所述基底的與所述重佈線結構相對的表面上沈積第一含矽絕緣層； 圖案化出延伸穿過所述第一含矽絕緣層及所述基底的第一開口，所述第一開口暴露出所述一或多個金屬化圖案的第一金屬化圖案； 沿所述第一開口的側壁形成側壁間隔壁，所述側壁間隔壁包括含矽絕緣材料； 形成電性連接件，所述電性連接件延伸穿過所述第一開口且電性連接至所述第一金屬化圖案；以及 使用所述電性連接件將封裝基底結合至所述中介體。
  10. 如申請專利範圍第9項所述的半導體元件封裝的製造方法，更包括： 在形成所述側壁間隔壁之後，在所述第一含矽絕緣層之上沈積絕緣緩衝層，所述絕緣緩衝層包括聚合物；以及 使所述第一開口延伸至所述絕緣緩衝層中。
  11. 如申請專利範圍第9項所述的半導體元件封裝的製造方法，其中形成所述側壁間隔壁包括： 在所述第一含矽絕緣層之上、沿所述第一開口的側壁以及在所述第一開口的底表面之上沈積第二含矽絕緣層；以及 使用非等向性蝕刻製程將所述第二含矽絕緣層圖案化，以移除所述第二含矽絕緣層的橫向部分並界定所述側壁間隔壁。
  12. 如申請專利範圍第9項所述的半導體元件封裝的製造方法，其中所述側壁間隔壁形成與所述基底之間的第一介面以及與所述第一含矽絕緣層之間的第二介面，所述第一介面在側向上與所述第二介面間隔開。
  13. 如申請專利範圍第12項所述的半導體元件封裝的製造方法，其中所述側壁間隔壁形成與所述基底之間的第三介面，所述第三介面設置於所述第一介面與所述第二介面之間，相對於所述基底的主表面而言，所述第三介面的斜率小於所述第一介面的斜率以及所述第二介面的斜率。
  14. 如申請專利範圍第9項所述的半導體元件封裝的製造方法，其中所述第一含矽絕緣層包括氮化矽、氧化矽、或氮氧化矽，且其中所述側壁間隔壁包括氮化矽、氧化矽、或氮氧化矽。
  15. 如申請專利範圍第9項所述的半導體元件封裝的製造方法，其中形成所述電性連接件包括： 沿所述側壁間隔壁的側壁以及在所述第一金屬化圖案之上沈積晶種層； 鍍覆導電特徵，所述導電特徵自所述晶種層延伸至所述第一開口外；以及 在所述導電特徵上形成焊料區。
  16. 如申請專利範圍第9項所述的半導體元件封裝的製造方法，更包括： 在所述第一晶粒與所述中介體之間分配底部填充膠，所述底部填充膠更在所述第二晶粒與所述中介體之間延伸；以及 將所述第一晶粒、所述第二晶粒、及所述底部填充膠包封於模塑化合物中。
  17. 如申請專利範圍第9項所述的半導體元件封裝的製造方法，其中圖案化出延伸穿過所述第一含矽絕緣層及所述基底的所述第一開口包括圖案化出在所述第一含矽絕緣層中較在所述基底中寬的所述第一開口。
  18. 一種半導體元件封裝，包括： 第一晶粒，結合至中介體，所述中介體包括： 金屬化圖案，電性連接至所述第一晶粒；以及 基底，位於所述金屬化圖案的與所述第一晶粒相對的側上； 含矽絕緣層，位於所述基底的與所述金屬化圖案相對的表面上； 聚合物層，位於所述含矽絕緣層的與所述基底相對的側上； 穿孔，穿過所述聚合物層、所述含矽絕緣層及所述基底延伸至所述金屬化圖案；以及 含矽側壁間隔壁，位於所述穿孔與所述基底之間，所述含矽側壁間隔壁更設置於所述穿孔與所述含矽絕緣層之間。
  19. 如申請專利範圍第18項所述的半導體元件封裝，其中所述含矽側壁間隔壁形成與所述含矽絕緣層之間的第一介面，且由與所述含矽絕緣層相同的材料製成。
  20. 如申請專利範圍第19項所述的半導體元件封裝，其中所述含矽側壁間隔壁形成與所述基底之間的第二介面，所述第一介面在側向上與所述第二介面間隔開。
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