CN113078144B - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN113078144B
CN113078144B CN202110046168.6A CN202110046168A CN113078144B CN 113078144 B CN113078144 B CN 113078144B CN 202110046168 A CN202110046168 A CN 202110046168A CN 113078144 B CN113078144 B CN 113078144B
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substrate
interposer
die
layer
forming
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CN113078144A (zh
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吕宗育
黄炳刚
邱绍玲
侯上勇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

实施例包括在中介层的衬底中部分地形成第一通孔，该第一通孔延伸到中介层的衬底的第一侧。该方法还包括将第一管芯接合到中介层的衬底的第一侧。该方法还包括使中介层的衬底的第二侧凹进以暴露第一通孔，第一通孔从中介层的衬底的第二侧突出，其中，在凹进之后，中介层的衬底的厚度小于50μm。该方法还包括在中介层的衬底的第二侧上形成第一组导电凸块，第一组导电凸块中的至少一个电耦合到暴露的第一通孔。本申请的实施例还涉及半导体封装件及其形成方法。

Description

半导体封装件及其形成方法
技术领域
本申请的实施例涉及半导体封装件及其形成方法。
背景技术
自集成电路(IC)的发展以来，由于各种电子部件(即，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体行业经历了持续快速的增长。大部分情况下，这些集成密度的改进来自最小部件尺寸的不断减小，这使得更多的部件可以集成到给定的区域中。
这些集成改进本质上基本上是二维(2D)的，因为集成部件所占据的区域基本上在半导体晶圆的表面上。集成电路的增加的密度和相应的面积减小通常已经超过了将集成电路芯片直接接合到衬底上的能力。因此，中介层已经被用于将球的接触面积从芯片的接触面积再分布到中介层的较大面积。此外，中介层已经允许包括多个芯片的三维(3D)封装件。
尽管使用中介层具有减小芯片尺寸的好处，但是使用中介层通常具有缺点。中介层通常会引入在处理完成之前未被检测到的新的几组问题。因此，由于先前的处理中的缺陷使得中介层不可用，因此出现错误的中介层的封装件可能会经历不必要的处理。这些问题中的一些通常包括衬底通孔(TSV)中的空隙、蚀刻工艺后金属化层的异常布线、凸点冷焊(开路或短路)以及中介层球的裂纹。
发明内容
本申请的一些实施例提供了一种形成半导体封装件的方法，包括：在中介层的衬底中部分地形成第一通孔，所述第一通孔延伸到所述中介层的所述衬底的第一侧中；将第一管芯接合到所述中介层的所述衬底的所述第一侧；使所述中介层的所述衬底的第二侧凹进，以暴露所述第一通孔，所述第一通孔从所述中介层的所述衬底的所述第二侧突出，其中，在所述凹进之后，所述中介层的所述衬底的厚度小于50μm；以及在所述中介层的所述衬底的所述第二侧上形成第一组导电凸块，所述第一组导电凸块中的至少一个电耦合到暴露的第一通孔。
本申请的另一些实施例提供了一种形成半导体封装件的方法，包括：将第一管芯和第二管芯接合到中介层，所述中介层包括：再分布结构，所述再分布结构包括一个或多个金属化图案，所述一个或多个金属化图案将所述第一管芯电连接到所述第二管芯；衬底，所述衬底与所述第一管芯和所述第二管芯位于所述再分布结构的相对侧上；以及多个衬底通孔，所述多个衬底通孔延伸穿过所述衬底，所述多个衬底通孔电耦合到所述再分布结构的所述一个或多个金属化图案；在所述衬底的与所述再分布结构相对的表面上形成缓冲结构，所述缓冲结构包括聚合物层；穿过所述缓冲结构图案化多个开口，所述多个开口中的每一个使所述多个衬底通孔中的一个暴露；在所述多个开口中形成第一金属化图案，所述第一金属化图案电耦合到所述多个衬底通孔；以及在所述第一金属化图案上形成多个第一连接件。
本申请的又一些实施例提供了一种半导体封装件，包括：第一管芯，接合到中介层，所述中介层包括：再分布结构，所述再分布结构包括一个或多个金属化图案，所述一个或多个金属化图案将所述第一管芯电连接到所述第二管芯；衬底，所述衬底与所述第一管芯和所述第二管芯位于所述再分布结构的相对侧上；以及多个衬底通孔，所述多个衬底通孔延伸穿过所述衬底，所述多个衬底通孔电耦合到所述再分布结构的所述一个或多个金属化图案；缓冲结构，位于所述衬底的与所述再分布结构相对的表面上，所述缓冲结构包括聚合物层；第一金属化图案，位于所述缓冲结构中，所述第一金属化图案电耦合到所述多个衬底通孔；以及多个第一连接件，电耦合到所述第一金属化图案。
附图说明
为了更完整地理解本发明的实施例及其优点，现在结合附图参考以下描述，其中：
图1是根据一些实施例的包括中介层的封装件结构的截面图。
图2是根据一些实施例的包括中介层的封装件结构的截面图。
图3至图24示出了根据一些实施例的包括中介层的封装件结构的制造中的各个中间阶段。
图25至图31示出了根据一些实施例的包括中介层的封装件结构的制造中的各个中间阶段。
具体实施方式
以下公开提供了用于实现本发明的不同特征的许多不同的实施例或示例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下、”“在…下方、”“下部、”“在…之上、”“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
在一些实施例中，器件封装件可以包括一个或多个半导体芯片，一个或多个半导体芯片接合到中介层，其中，该中介层接合到衬底。中介层在一个或多个半导体芯片与封装件衬底之间提供电路由。例如，中介层可以包括设置在衬底上的再分布结构(例如，包括设置在一个或多个绝缘层中的导电线和/或通孔)。再分布结构提供至一个或多个半导体芯片或来自一个或多个半导体芯片的电路由。导电通孔可以延伸穿过衬底，并且电连接到再分布结构的导电部件。在一些实施例中，焊接区域设置在导电通孔上，以提供用于接合到封装件衬底的电连接件(例如，微凸块(μ凸块))。
为了获得小的封装件轮廓并改善封装件的性能，中介层的衬底的厚度在1μm至50μm的范围内。在一些实施例中，中介层的衬底的厚度小于50μm。由于衬底的薄度，衬底更加柔软并且可以在器件封装件的热处理期间(例如，可靠性/压力测试、回流/接合到封装件衬底等)减小封装件中的应力。此外，与较厚中介层中的通孔相比，中介层中的通孔的电阻、电感和电容得到改善。在一些实施例中，芯片的厚度与中介层的衬底的厚度之比在10至50的范围内。换句话说，芯片的厚度是中介层的衬底的10到50倍。在其它实施例中，芯片的衬底的厚度与中介层的衬底的厚度之比可以小于10或大于50。
各个实施例还在中介层与封装件衬底之间提供缓冲结构，以进一步提高封装件的可靠性并减小中介层的衬底和半导体芯片上的应力。在一些实施例中，缓冲结构可以包括一个或多个聚合物层，诸如聚酰亚胺。此外，缓冲结构可以包括杨氏模量在1吉帕斯卡(GPa)至10GPa的范围内的聚合物层。由于杨氏模量值低，因此缓冲结构具有柔韧性，并且会因破裂或断裂而变形。
将针对特定上下文(即，管芯-中介层-衬底堆叠封装件)描述实施例。然而，其它实施例也可以应用于其它封装件，诸如管芯-管芯-衬底堆叠封装件。本文所讨论的实施例是为了提供能够实现或使用本公开的主题的示例，并且本领域普通技术人员将容易理解在不同实施例的预期范围内可以进行的修改。下图中相同附图标记和字符表示相同的部件。尽管方法实施例可以被讨论为以特定顺序执行，但是其它方法实施例可以以任何逻辑顺序执行。
图1示出了封装件结构的截面图。图1示出了具有集成电路管芯77的中介层200的截面图，集成电路管芯77经由导电连接件68附接到中介层200的第一侧。集成电路管芯77包括互连件，该互连件包括一个或多个金属化层。
中介层200包括衬底40、衬底通孔(TSV，也称为硅通孔或半导体通孔)47。中介层200包括包含一个或多个金属化层的再分布结构。导电连接件68经由再分布结构中的一个或多个金属化层电耦合至中介层200中的TSV 47。TSV 47从衬底的前侧延伸穿过中介层200的衬底40到衬底40的背侧，再分布结构形成在衬底的前侧上。
中介层200的衬底40的厚度在1μm至50μm的范围内。在一些实施例中，芯片的衬底的厚度与中介层的衬底的厚度之比在10至50的范围内。在其它实施例中，芯片的衬底的厚度与中介层的衬底的厚度之比可以小于10或大于50。
中介层200包括钝化结构，该钝化结构可以包括一个或多个金属化层，诸如背侧再分布元件。导电焊盘机械耦合到中介层200的背侧，并且直接和/或经由钝化结构中的一个或多个金属化层电耦合到TSV 47。导电连接件96机械耦合到且电耦合到导电焊盘。导电连接件96提供来自集成电路管芯77的外部电连接。导电连接件96机械耦合到封装件衬底300，并且电耦合到封装件衬底300上的导电焊盘304。
封装件衬底300包括衬底302、面向中介层200的导电焊盘304和背向中介层200的导电焊盘306。导电连接件308机械耦合到且电耦合到导电焊盘306。封装件衬底300可以是芯衬底，芯衬底具有通孔和再分布结构，再分布结构在芯的两侧上并耦合到通孔。
图2示出了的包括缓冲结构120的中介层400的截面图。图2中的实施例类似于图1中的实施例，除了中介层400包括缓冲结构120之外。缓冲结构120包括减小封装件结构中的应力的一个或多个聚合物层，诸如聚酰亚胺层。
图3至图25示出了形成具有中间层和附接到该中介层的管芯的中介层200的方法，诸如图1所示的结构。应当理解，提供该顺序是为了说明的目的，并且可以使用其它顺序。
图3至图12示出了中介层200的形成。首先参考图3，提供了中介层的衬底40。衬底40通常包括类似于用于形成集成电路管芯的衬底的材料，诸如硅，该集成电路管芯将被附接到中介层。衬底40可以是晶圆。衬底40可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。衬底40的半导体材料可以是硅、锗、包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或其组合。也可以使用其它衬底，诸如多层或梯度衬底。衬底40可以是掺杂的或未掺杂的。诸如晶体管、电容器、电阻器、二极管等的器件可以形成在衬底40的上部表面中和/或上部表面上，该上部表面也可以称为衬底的有源表面。虽然衬底40可以由其它材料形成，但是可以认为将硅衬底用作中介层可以减少应力，因为硅衬底和通常用于管芯的硅之间的热膨胀系数(CTE)失配低于由不同材料形成的衬底。
在图4中，凹槽42部分地穿过衬底40形成。随后将在凹槽42中形成衬底通孔。凹槽42可以通过蚀刻技术、铣削技术、激光技术、其组合等形成。可以使用例如光刻和蚀刻的组合来形成衬底40中的凹槽42。例如，可以通过旋压等将光刻胶(未示出)沉积在衬底40上方。沉积后，例如通过以下方式将光刻胶图案化：将图案化的光掩模放在光刻胶上方，使用光掩模对光刻胶进行曝光，并对光刻胶进行显影以去除光刻胶的已曝光或未曝光部分(取决于是使用正性光刻胶还是负性光刻胶)。光刻胶的图案对应于凹槽42的图案。然后使用光刻胶作为掩模来蚀刻衬底40。蚀刻工艺的类型可以取决于衬底40的材料。例如，为了蚀刻衬底40，可以使用干蚀刻工艺。用于干蚀刻工艺的蚀刻剂的示例包括SF6等。
在图5中，阻挡层44共形地沉积在衬底40的前侧上方和凹槽42中。阻挡层44可以由诸如氮化钛、氮氧化钛、氮化钽、氮氧化钽、其组合等的氮化物或氮氧化物形成。在一些实施例中，阻挡层44通过化学气相沉积(CVD)、原子层沉积(ALD)、物理气相沉积(PVD)、热氧化、其组合等形成。
在图6中，导电材料46沉积在薄阻挡层上方和开口中。导电材料46可以通过电化学镀工艺、CVD、ALD、PVD、其组合等形成。导电材料46的示例是铜、钨、铝、银、金、其组合等。
在图7中，通过例如化学机械抛光(CMP)从衬底40的前侧去除了过量的导电材料46和阻挡层44，从而形成了TSV 47。在CMP之后，导电材料46、阻挡层44和衬底40的表面是共面的(在工艺变化内)。因此，TSV47包括导电材料46和在导电材料46与衬底40之间的阻挡层44。
图8至图10示出了再分布结构65的形成。再分布结构65形成在衬底40的前侧上，并且用于将集成电路器件，如果有的话，和/或电连接到外部器件，诸如随后附接的半导体芯片。再分布结构65可以包括一个或多个介电层和在一个或多个介电层中的相应的一个或多个金属化图案。金属化图案可以包括通孔和/或迹线，以互连任何器件和/或外部器件。金属化图案有时称为再分布线(RDL)。
在图8中，介电层48(有时称为金属间介电(IMD)层48)沉积在衬底40和TSV 47上方。介电层48可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、低K介电材料，诸如未掺杂的硅酸盐玻璃(USG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、其化合物、其复合物、其组合等。可以通过本领域中已知的任何合适的方法来沉积介电层，诸如旋压、CVD、等离子增强CVD(PECVD)、高密度等离子体化学气相沉积(HDP-CVD)等或其组合。
在IMD层48中蚀刻开口49以暴露TSV 47的导电材料46。可以使用例如可接受的光刻技术和蚀刻技术来形成开口49。开口49将成为用于随后形成到TSV 47的通孔的开口。
在图9中，在开口49中并且在介电层48上方形成包括导电通孔50和导电线52的金属化图案。金属化图案包括沿着介电层48的主表面延伸的导电元件52和延伸穿过介电层48以物理耦合到且电耦合到TSV 47的元件50。作为形成金属化图案的示例，在介电层48上方以及延伸穿过介电层48的开口49中形成晶种层(未示出)。然后在晶种层上形成光刻胶(未示出)并将光刻胶图案化。图案化形成穿过光刻胶的开口以暴露出晶种层，其中，开口的图案对应于金属化图案。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀、CVD、PVD等的镀来形成导电材料。导电材料可以包括金属，例如铜、镍、铝、铜铝、钨、钛、其组合等。导电材料和晶种层下方部分的组合形成金属化图案。去除光刻胶和晶种层上未形成导电材料的部分。一旦例如通过使用诸如湿或干蚀刻的可接受的蚀刻工艺去除了光刻胶，就去除了晶种层的暴露部分。介电层48与金属化图案50和52的组合形成再分布层53。
在图10中，重复以上在图8和图9中讨论的步骤和工艺，以在再分布结构65中形成额外显示的再分布层54、58和62。在一些实施例中，可以将形成再分布结构65的上述工艺重复一次或多次，以提供特定设计所需的附加路由层。出于说明目的，示出了四个再分布层53、54、58和62。在一些实施例中，可以使用多于或少于四个再分布层。每个再分布层53、54、58和62的金属化图案52、56和60分别可以具有分别形成的导电线和导电通孔(如图所示)，或者每个可以是具有线和通孔部分的单一图案。
金属化图案可以包括在导电材料和介电层之间的阻挡层，诸如TaN、Ta、TiN、Ti、CoW的一层或多层，并且可以包括其它介电层，诸如由例如氮化硅制成的蚀刻停止层可以形成在介电层之间。
在形成顶部金属化图案，即图10中的金属化图案60之后，在金属化层上方形成一个或多个钝化层。钝化层可以是聚酰亚胺、BPSG、其组合等，并且可以使用旋涂技术、CVD、ALD、其组合等形成。
在图11中，形成穿过钝化层的开口64以暴露顶部金属化图案，即金属化图案60，以便在顶部金属化图案上形成凸块焊盘。可以使用例如可接受的光刻技术和去除技术形成开口64，诸如蚀刻技术、铣削技术、激光技术、其组合等。
参考图12，通过顶部金属化层上的开口64形成导电焊盘66，并且在导电焊盘66上形成导电连接件68。在一些实施例中，导电焊盘66包括凸块下冶金(UBM)。在所示的实施例中，导电焊盘66(UBM)延伸穿过再分布结构65的介电层和/或钝化层的开口64，并且还延伸跨过再分布结构65的顶部表面。在另一实施例中，在再分布结构65的介电层的开口64中形成导电焊盘66。
作为形成焊盘的示例，至少在再分布结构65的介电层中的开口64中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和在钛层上方的铜层。可以使用例如PVD等形成晶种层。然后，在晶种层上形成光刻胶并将光刻胶图案化。可以通过旋涂等形成光刻胶，并且可以将其曝光以用于图案化。光刻胶的图案对应于焊盘。图案化形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，例如铜、钛、钨、铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺，例如使用氧等离子体等，来去除光刻胶。一旦例如通过使用诸如湿或干蚀刻的可接受的蚀刻工艺去除了光刻胶，就去除了晶种层的暴露部分。晶种层的剩余部分和导电材料形成导电焊盘66。在实施例中，其中，导电焊盘66以不同的方式形成，可以利用更多的光刻胶和图案化步骤。
在一些实施例中，导电连接件68包括在金属柱上方具有金属覆盖层的金属柱，该金属覆盖层可以是焊帽。包括柱和覆盖层的导电连接件68有时称为微凸块(μ凸块)68。在一些实施例中，金属柱包括诸如铜、铝、金、镍、钯等的导电材料或其组合，并且可以通过溅射、印刷、电镀、化学镀、CVD等形成。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层。金属覆盖层可以包括镍、锡、锡铅、金、铜、银、钯、铟、镍钯金、镍金等或其组合，并且可以通过镀工艺形成。
在另一实施例中，导电连接件68不包括金属柱并且是焊球和/或凸块，诸如受控塌陷芯片连接(C4)、化学镀镍浸金(ENIG)、化学镀镍化学钯浸金技术(ENEPIG)形成的凸块等。在该实施例中，凸块导电连接件68可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合的导电材料。在该实施例中，通过诸如蒸发、电镀、印刷、焊料转移、焊球放置等的适当方法首先形成焊料层来形成导电连接件68。一旦在结构上形成焊料层，就可以执行回流，以便将材料成形为期望的凸块形状。
在图13中，集成电路管芯77通过导电连接件68附接到中介层200，并且底部填充物76分配在集成电路管芯77和再分布结构65(例如顶部钝化层)之间。在附接到导电连接件68之前，形成集成电路管芯77。
集成电路管芯77的衬底70可以包括晶体管、有源器件、无源器件等。在一实施例中，衬底70可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。衬底70的半导体材料可以是硅、锗、包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或其组合。也可以使用其它衬底，诸如多层或梯度衬底。衬底70可以是掺杂的或未掺杂的。诸如晶体管、电容器、电阻器、二极管等的器件可以形成在有源表面71内和/或上。
包括一个或多个介电层和相应的一个或多金属化图案的互连结构72形成在有源表面71上。一个或多个介电层中的一个或多个金属化图案可以例如通过使用通孔和/或迹线在器件之间路由电信号，并且还可以包含诸如电容器、电阻器、电感器等的各种电气器件。各种器件和金属化图案可以互连以执行一个或多个功能。功能可以包括存储器结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。另外，在互连结构72内和/或上形成诸如导电柱(例如，包括诸如铜之类的金属)的管芯连接件74，以提供与电路和器件的外部电连接。在一些实施例中，管芯连接件74从互连结构72突出以形成柱结构，从而在将集成电路管芯77接合到其它结构时使用。本领域普通技术人员将理解，提供以上示例是出于说明性目的。对于给定的应用，可以适当地使用其它电路。
更具体地，可以在互连结构72中形成IMD层。可以通过本领域已知的任何合适方法(诸如旋压、化学气相沉积(CVD)、等离子增强CVD(PECVD)、高密度等离子体化学气相沉积(HDP-CVD)等)由例如低K介电材料形成IMD层，低K介电材料诸如未掺杂的硅酸盐玻璃(USG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、其化合物、其复合物、其组合等。可以例如通过使用光刻技术在IMD层上沉积和图案化光刻胶材料，以暴露IMD层中要成为金属化图案的部分，从而在IMD层中形成金属化图案。可以使用诸如各向异性干蚀刻工艺的蚀刻工艺在IMD层中产生与IMD层的暴露部分相对应的凹槽和/或开口。凹槽和/或开口可以衬有扩散阻挡层并且填充有导电材料。扩散阻挡层可以包括通过原子层沉积(ALD)等沉积的氮化钽、钽、氮化钛、钛、钴钨等或其组合的一层或多层。金属化图案的导电材料可以包括通过CVD、物理气相沉积(PVD)等沉积的铜、铝、钨、银及其组合等。可以例如通过使用化学机械抛光(CMP)来去除IMD层上的任何过量的扩散阻挡层和/或导电材料。
将包括互连结构72的衬底70分割成单个集成电路管芯77。通常，集成电路管芯77包含相同的电路，诸如器件和金属化图案，但是管芯可以具有不同的电路。分割可以包括锯切、切割等。
集成电路管芯77中的每一个可以包括一个或多个逻辑管芯(例如，中央处理单元、图形处理单元、系统级芯片、现场可编程门阵列(FPGA)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等，或其组合。而且，在一些实施例中，集成电路管芯77可以具有不同的尺寸(例如，不同的高度和/或表面积)，并且在其它实施例中，集成电路管芯77可以具有相同的尺寸(例如，相同的高度和/或表面积)。
集成电路管芯77可以是使用取放工具附接的已知良好管芯，并且在分配底部填充物材料76之前可以使导电连接件68回流。底部填充物材料76可以是液态环氧树脂、可变形凝胶、硅橡胶、其组合。
在图14中，在底部填充物材料76固化之后，通过在各个部件上和周围形成密封剂78来执行密封。形成之后，密封剂78围绕集成电路管芯77和底部填充物76。密封剂78可以由模塑料、环氧树脂等形成，并且可以通过压缩模制、传递模制等施加。可以以液体或半液体形式施加密封剂78，然后随后固化。密封剂78可以形成在集成电路管芯77上方，使得集成电路管芯77被掩埋或覆盖。
如果需要，可以对密封剂78执行平坦化工艺，以暴露集成电路管芯77的衬底70。在工艺变化内，在平坦化工艺之后，衬底70的密封剂78的最上表面是共面的。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，可以省略平坦化。
在图15至图24中示出了中介层200的衬底40的背侧处理。在图15中，图14的组件在背侧处理期间附接到载体衬底82。可以使用粘合剂80将载体衬底82附接到集成电路管芯77或模塑料78。通常，载体衬底82在随后的处理步骤中提供临时的机械和结构支撑。以这种方式，减少或防止了中介层的损伤。载体衬底82可以包括例如玻璃、氧化硅、氧化铝、其组合等。粘合剂80可以是当暴露于UV光时会失去其粘合性能的任何合适的粘合剂，诸如紫外线(UV)胶。
在图16中，衬底40的背侧被平坦化以露出TSV 47的导电材料46和阻挡层44。平坦化工艺可以是例如化学机械抛光(CMP)。
在图17中，将衬底40减薄，以使TSV 47从衬底40的背侧突出。可以使用蚀刻工艺或平坦化工艺来执行减薄工艺。例如，在暴露TSV 47之后，可以执行在阻挡层44的材料和衬底40之间具有高蚀刻速率选择性的一种或多种湿蚀刻工艺，从而使TSV 47从衬底40的背侧突出。蚀刻工艺也可以是例如干蚀刻工艺。在使衬底40减薄之后，在突出的TSV 47之间形成凹槽84。
在减薄工艺之后，中介层的衬底40具有厚度T1。在一些实施例中，衬底40的厚度T1在1μm至50μm的范围内。在一些实施例中，衬底40的厚度T1小于50μm。在一些实施例中，集成电路管芯77中的至少一个的衬底70具有厚度T2。在一些实施例中，集成电路管芯77的衬底70的厚度T2与中介层的衬底40的厚度T1之比在10至50的范围内。在其它实施例中，集成电路管芯77的衬底70的厚度T2与中介层的衬底40的厚度T1之比可以小于10或大于50。
在图18中，介电层86共形地沉积在衬底40的背侧上方。具体地，介电层86形成在凹槽84中并且沿着TSV 47的侧壁和上部表面形成。介电层86可以是例如氧化硅、氮化硅、其组合等。在一些实施例中，介电层86可以通过本领域已知的任何合适的方法来沉积，诸如CVD、PECVD等、或其组合。
在图19中，介电层88沉积在介电层86上方。介电层88可以是例如氧化硅、氮化硅、其组合等。介电层88可以通过本领域中已知的任何合适的方法来沉积，诸如CVD、PECVD等或其组合。在一些实施例中，介电层88的材料组成与介电层86不同。
在图20中，然后例如通过CMP将背侧平坦化，使得TSV 47的阻挡层44和导电材料46暴露在背侧上。在平坦化之后，阻挡层44、导电材料、介电层86和介电层88的表面在工艺变化内共面。
在图21中，钝化层90形成在平坦化的TSV 47以及介电层86和88上方。在一些实施例中，钝化层90在随后的处理中保护和钝化下方的层，以免受到化学物质的影响。钝化层90形成在介电层86和88上方的背侧上，并且可以是例如通过旋涂技术、CVD、ALD、其组合等形成的聚酰亚胺、BPSG、其组合等。
在图22中，形成穿过钝化层90的开口92以暴露例如TSV 47的阻挡层44和导电材料46，以便形成导电焊盘94。可以使用例如可接受的光刻技术和去除技术形成开口92，诸如蚀刻技术、铣削技术、激光技术、其组合等。
在图23中，导电焊盘94通过开口92形成并且耦合到TSV 47的导电材料46，并且在导电焊盘94上形成导电连接件96。在一些实施例中，导电焊盘94包括凸块下冶金(UBM)。在所示的实施例中，导电焊盘94(UBM)延伸穿过钝化层90的开口92，并且还延伸跨过钝化层90的顶部表面。在另一实施例中，在钝化层90的开口92中形成导电焊盘94。
作为形成导电焊盘94的示例，至少在钝化层90中的开口92中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和在钛层上方的铜层。可以使用例如PVD等形成晶种层。然后，在晶种层上形成光刻胶并将光刻胶图案化。可以通过旋涂等形成光刻胶，并且可以将其曝光以用于图案化。光刻胶的图案对应于焊盘。图案化形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，例如铜、钛、钨、铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺，例如使用氧等离子体等，来去除光刻胶。一旦例如通过使用诸如湿或干蚀刻的可接受的蚀刻工艺去除了光刻胶，就去除了晶种层的暴露部分。晶种层的剩余部分和导电材料形成导电焊盘94。在该实施例中，其中，导电焊盘94以不同的方式形成，可以利用更多的光刻胶和图案化步骤。
在一些实施例中，导电连接件96是焊球和/或凸块，诸如可控塌陷芯片连接(C4)、化学镀镍浸金(ENIG)、化学镀镍化学镀钯浸金技术(ENEPIG)形成的凸块等。在该实施例中，凸块导电连接件96可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合的导电材料。在该实施例中，通过诸如蒸发、电镀、印刷、焊料转移、焊球放置等的适当方法首先形成焊料层来形成导电连接件96。一旦在结构上形成焊料层，就可以执行回流，以便将材料成形为期望的凸块形状。
在另一实施例中，导电连接件96包括在金属柱上方具有金属覆盖层的金属柱，该金属覆盖层可以是焊帽。在一些实施例中，金属柱包括诸如铜、铝、金、镍、钯等的导电材料或其组合，并且可以通过溅射、印刷、电镀、化学镀、CVD等形成。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层。金属覆盖层可以包括镍、锡、锡铅、金、铜、银、钯、铟、镍钯金、镍金等或其组合，并且可以通过镀工艺形成。
应当注意，图23示出了直接耦合到TSV 47的导电焊盘94；然而，可以在衬底40的背侧上形成一个或多个金属化层和IMD层，以将导电垫94电耦合到TSV47。背侧金属化层可以通过任何合适的技术(诸如电化学镀(ECP)、化学镀、诸如溅射、印刷和CVD的其它沉积方法、其组合等)由任何合适的导电材料(诸如铜、铜合金、铝、银、金、其组合等)形成。
在图24中，例如通过将粘合剂80暴露于UV辐射来去除载体衬底82。然后使用中介层和任意数量的管芯将组件切割成单个封装件，诸如图1所示的封装件。
图25至图31示出了形成中介层400和附接到中介层400的管芯的各个中间阶段，该中介层400包括诸如图2所示的结构的缓冲结构120。应当理解，提供该顺序是为了说明的目的，并且可以使用其它顺序。该实施例类似于图1和图3至图24中的先前实施例，除了该实施例包括在中介层400和封装件衬底300之间的缓冲结构120之外。与先前描述的实施例类似的关于该实施例的细节在此将不再重复。
图25至图28示出了中介层400上的缓冲结构120的形成。在图25中，在介电层86和88以及TSV 47上方形成第一缓冲层100。图25之前的处理类似于以上图3至图20中描述的处理，并且在此不再赘述。
可以使用旋涂技术、CVD、ALD、其组合等来形成第一缓冲层100。第一缓冲层100可以减轻封装件结构中的应力并防止衬底40和/或集成电路管芯77的变形和破裂。第一缓冲层100可以包括一个或多个聚合物层，诸如聚酰亚胺。在一些实施例中，第一缓冲层100可以是杨氏模量在1吉帕斯卡(GPa)至10GPa的范围内的聚合物层。在一些实施例中，第一缓冲层100形成为厚度在1μm至20μm的范围内。
在图26中，在第一缓冲层100中形成开口102，以便金属化图案104的形成。开口102暴露出TSV 47的导电材料46。开口102可以使用例如可接受的光刻技术和去除技术形成，诸如蚀刻、铣削、激光技术、其组合等。使用可接受的光刻技术和蚀刻技术。
在图27中，在开口102中并在第一缓冲层100上方形成包括导电通孔和导电线的金属化图案104。金属化图案104包括沿着第一缓冲层100的主表面延伸的导电元件和延伸穿过第一缓冲层100以物理耦合到且电耦合到TSV 47的导电元件。作为形成金属化图案104的示例，在第一缓冲层100上方以及在延伸穿过第一缓冲层100的开口102中形成晶种层(未示出)。然后在晶种层上形成光刻胶(未示出)并将光刻胶图案化。图案化形成穿过光刻胶的开口以暴露出晶种层，其中，开口的图案对应于金属化图案104。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀、CVD、PVD等的镀来形成导电材料。导电材料可以包括金属，例如铜、镍、铝、铜铝、钨、钛、其组合等。导电材料和晶种层下方部分的组合形成金属化图案104。去除光刻胶和晶种层上未形成导电材料的部分。一旦例如通过使用诸如湿或干蚀刻的可接受的蚀刻工艺去除了光刻胶，就去除了晶种层的暴露部分。第一缓冲层100和金属化图案104的组合形成背侧再分布层。
在图28中，第二缓冲层106沉积在第一缓冲层100和金属化图案104上方。第一缓冲层100、金属化图案104和第二缓冲层106用于缓冲结构120。可以使用旋涂技术、CVD、ALD、其组合等来形成第二缓冲层106。第二缓冲层106可以与第一缓冲层100一起减轻封装件结构中的应力，并且防止衬底40和/或集成电路管芯77变形和破裂。第二缓冲层106可以包括一个或多个聚合物层，诸如聚酰亚胺。在一些实施例中，第二缓冲层106可以是可以是杨氏模量在1吉帕斯卡(GPa)至10GPa的范围内的聚合物层。在一些实施例中，第二缓冲层106形成为厚度在1μm至20μm的范围内。
在图29中，在第二缓冲层106中形成开口108，以便导电焊盘110的形成。该开口102暴露出金属化图案104，并且可以形成类似于描述上述的开口102在此不再赘述。
在图30中，通过开口108形成导电焊盘110，将导电焊盘110耦合到金属化图案104，并且在导电焊盘110上形成导电连接件112。导电焊盘110类似于上述的导电焊盘94，并且在此不再赘述。导电连接件112类似于上述导电连接件96，并且在此不再赘述。
尽管图25至图30示出了两个缓冲层和单个金属化图案，但是其他实施例可以包括更多的缓冲层和金属化图案。
在图31中，去除了载体衬底82。例如，通过将粘合剂80暴露于UV辐射，将图31的组件从载体衬底82上去除。然后，使用中介层和任意数量的管芯将组件切割成单个封装件，诸如图2所示的封装件。
实施例可实现许多优势。在一些实施例中，中介层的衬底的厚度在1μm至50μm的范围内。由于衬底的薄度，衬底更加柔软并且可以在器件封装件的热处理期间(例如，可靠性/压力测试、回流/接合到封装件衬底等)减小封装件中的应力。此外，与较厚中介层中的通孔相比，中介层中的通孔的电阻、电感和电容得到改善。这是因为通孔的电阻、电感和电容与通孔的长度成正比。因此，由于所公开结构的通孔比较厚的中介层的通孔短，所以所公开结构的电阻、电感和电容均得到改善。在一些实施例中，芯片的厚度与中介层的衬底的厚度之比在10至50的范围内。换句话说，芯片的厚度是中介层的衬底的10到50倍。在其它实施例中，中介层的芯片厚度与中介层的衬底厚度之比小于10或大于50。
各个实施例还在中介层与封装件衬底之间提供缓冲结构，以进一步提高封装件的可靠性并减小中介层的衬底和半导体芯片上的应力。在一些实施例中，缓冲结构可以包括一个或多个聚合物层，诸如聚酰亚胺。此外，缓冲结构可以包括杨氏模量在1吉帕斯卡(GPa)至10GPa的范围内的聚合物层。由于杨氏模量值低，因此缓冲结构具有柔韧性，并且会因破裂或断裂而变形。
一个实施例包括在中介层的衬底中部分地形成第一通孔，该第一通孔延伸到中介层的衬底的第一侧。该方法还包括将第一管芯接合到中介层的衬底的第一侧。该方法还包括使中介层的衬底的第二侧凹进以暴露第一通孔，第一通孔从中介层的衬底的第二侧突出，其中，在凹进之后，中介层的衬底的厚度小于50μm。该方法还包括在中介层的衬底的第二侧上形成第一组导电凸块，第一组导电凸块中的至少一个电耦合到暴露的第一通孔。
实施例可以包括以下特征中的一个或多个。该方法还包括在中介层的第一侧上形成再分布结构，该再分布结构包括多个介电层，多个介电层中有金属化图案，金属化图案电耦合到第一通孔。该方法还包括在第一管芯与中介层的衬底之间形成底部填充物，以及用密封剂密封第一管芯和底部填充物。在使中介层的衬底的第二侧凹进之后，中介层的衬底的厚度在1μm至50μm的范围内。在使中介层的衬底的第二侧凹进之后，第一管芯的厚度是中介层的衬底的十倍。该方法还包括在使中介层的衬底的第二侧凹进之后，在第一通孔的侧壁上以及在中介层的衬底的凹进的第二侧上形成第一介电层；以及在第一介电层上形成第二介电层，第一组导电凸块中的至少一个在第二介电层上。第一介电层是共形层，并且其中，第二介电层是非共形层。该方法还包括在第二介电层上方形成聚合物层；以及在聚合物层中形成金属化图案，第一组导电凸块中的至少一个在聚合物层上。在使中介层的衬底的第二侧凹进之后，第一管芯的厚度是中介层的衬底的五十倍。该方法还包括将封装件衬底接合到第一组导电凸块，第一组导电凸块中的至少一个通过中介层电耦合到第一管芯。
一个实施例包括将第一管芯和第二管芯接合到中介层，该中介层包括再分布结构，该再分布结构包括将第一管芯电连接到第二管芯的一个或多个金属化图案。该方法还包括与第一管芯和第二管芯位于再分布结构的相对侧上的衬底。该方法还包括延伸穿过衬底的多个衬底通孔，多个衬底通孔电耦合到再分布结构的一个或多个金属化图案。该方法还包括在衬底的与再分布结构相对的表面上形成缓冲结构，该缓冲结构包括聚合物层。该方法还包括将穿过缓冲结构图案化多个开口，多个开口中的每一个使多个衬底通孔中的一个暴露。该方法还包括在所述多个开口中形成第一金属化图案，所述第一金属化图案电耦合至所述多个衬底通孔。该方法还包括并且在第一金属化图案上形成多个第一连接件。
实施例可以包括以下特征中的一个或多个。在该方法中，聚合物层为聚酰亚胺。所述聚合物层的杨氏模量在1吉帕斯卡(GPa)至10GPa的范围内。中介层的衬底厚度小于50μm。第一管芯的厚度是中介层的衬底的十倍。该方法还包括在第一管芯、第二管芯和中介层之间形成底部填充物，以及用密封剂密封第一管芯、第二管芯和底部填充物。在凹进之后，多个通孔从中介层的衬底突出。
实施例包括接合到中介层的第一管芯，该中介层包括再分布结构，该再分布结构包括将第一管芯电连接到第二管芯的一个或多个金属化图案。封装件还包括与第一管芯和第二管芯位于再分布结构的相对侧上的衬底。封装件还包括延伸穿过衬底的多个衬底通孔，多个衬底通孔电耦合到再分布结构的一个或多个金属化图案。封装件还包括在衬底的与再分布结构相对的表面上的缓冲结构，该缓冲结构包括聚合物层。封装件还包括在缓冲结构中的第一金属化图案，该第一金属化图案电耦合至多个衬底通孔。封装件还包括在第一金属化图案上且电耦合到第一金属化图案的多个第一连接件。
实施例可以包括以下特征中的一个或多个。中介层的衬底厚度小于50μm的封装件。第一管芯的厚度是中介层的衬底的十倍。
本申请的一些实施例提供了一种形成半导体封装件的方法，包括：在中介层的衬底中部分地形成第一通孔，所述第一通孔延伸到所述中介层的所述衬底的第一侧中；将第一管芯接合到所述中介层的所述衬底的所述第一侧；使所述中介层的所述衬底的第二侧凹进，以暴露所述第一通孔，所述第一通孔从所述中介层的所述衬底的所述第二侧突出，其中，在所述凹进之后，所述中介层的所述衬底的厚度小于50μm；以及在所述中介层的所述衬底的所述第二侧上形成第一组导电凸块，所述第一组导电凸块中的至少一个电耦合到暴露的第一通孔。
在一些实施例中，方法还包括：在所述中介层的所述第一侧上形成再分布结构，所述再分布结构包括多个介电层，所述多个介电层中有金属化图案，所述金属化图案电耦合到所述第一通孔。在一些实施例中，方法还包括：在所述第一管芯与所述中介层的所述衬底之间形成底部填充物；以及用密封剂密封所述第一管芯和所述底部填充物。在一些实施例中，在所述使所述中介层的所述衬底的所述第二侧凹进之后，所述中介层的所述衬底的厚度在1μm至50μm的范围内。在一些实施例中，在使所述中介层的所述衬底的所述第二侧凹进之后，所述第一管芯比所述中介层的所述衬底厚。在一些实施例中，方法还包括：在所述使所述中介层的所述衬底的所述第二侧凹进之后，在所述第一通孔的侧壁上以及在所述中介层的所述衬底的凹进的第二侧上形成第一介电层；以及在所述第一介电层上形成第二介电层，所述第一组导电凸块中的至少一个在所述第二介电层上。在一些实施例中，所述第一介电层是共形层，并且其中，所述第二介电层是非共形层。在一些实施例中，方法还包括：在所述第二介电层上方形成聚合物层；以及在所述聚合物层中形成金属化图案，所述第一组导电凸块中的所述至少一个在所述聚合物层上。在一些实施例中，所述聚合物层的杨氏模量在1吉帕斯卡(GPa)至10GPa的范围内。在一些实施例中，方法还包括：将封装件衬底接合到所述第一组导电凸块，所述第一组导电凸块中的所述至少一个通过所述中介层电耦合到所述第一管芯。
本申请的另一些实施例提供了一种形成半导体封装件的方法，包括：将第一管芯和第二管芯接合到中介层，所述中介层包括：再分布结构，所述再分布结构包括一个或多个金属化图案，所述一个或多个金属化图案将所述第一管芯电连接到所述第二管芯；衬底，所述衬底与所述第一管芯和所述第二管芯位于所述再分布结构的相对侧上；以及多个衬底通孔，所述多个衬底通孔延伸穿过所述衬底，所述多个衬底通孔电耦合到所述再分布结构的所述一个或多个金属化图案；在所述衬底的与所述再分布结构相对的表面上形成缓冲结构，所述缓冲结构包括聚合物层；穿过所述缓冲结构图案化多个开口，所述多个开口中的每一个使所述多个衬底通孔中的一个暴露；在所述多个开口中形成第一金属化图案，所述第一金属化图案电耦合到所述多个衬底通孔；以及在所述第一金属化图案上形成多个第一连接件。
在一些实施例中，所述聚合物层是聚酰亚胺。在一些实施例中，所述聚合物层的杨氏模量在1吉帕斯卡(GPa)至10GPa的范围内。在一些实施例中，所述中介层的所述衬底的厚度小于50μm。在一些实施例中，所述第一管芯比所述中介层的所述衬底厚。在一些实施例中，方法还包括：在所述第一管芯、所述第二管芯和所述中介层之间形成底部填充物；以及用密封剂密封所述第一管芯、所述第二管芯和所述底部填充物。在一些实施例中，方法还包括：使所述衬底的与所述再分布结构相对的所述表面凹进，其中，在所述凹进之后，所述多个通孔从所述中介层的所述衬底突出。
本申请的又一些实施例提供了一种半导体封装件，包括：第一管芯，接合到中介层，所述中介层包括：再分布结构，所述再分布结构包括一个或多个金属化图案，所述一个或多个金属化图案将所述第一管芯电连接到所述第二管芯；衬底，所述衬底与所述第一管芯和所述第二管芯位于所述再分布结构的相对侧上；以及多个衬底通孔，所述多个衬底通孔延伸穿过所述衬底，所述多个衬底通孔电耦合到所述再分布结构的所述一个或多个金属化图案；缓冲结构，位于所述衬底的与所述再分布结构相对的表面上，所述缓冲结构包括聚合物层；第一金属化图案，位于所述缓冲结构中，所述第一金属化图案电耦合到所述多个衬底通孔；以及多个第一连接件，电耦合到所述第一金属化图案。
在一些实施例中，所述中介层的所述衬底的厚度小于50μm。在一些实施例中，所述第一管芯比所述中介层的所述衬底厚。
前述概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本公开的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (20)

1.一种形成半导体封装件的方法，包括：
在中介层的衬底中部分地形成第一通孔，所述第一通孔延伸到所述中介层的所述衬底的第一侧中；
将第一管芯接合到所述中介层的所述衬底的所述第一侧；
使所述中介层的所述衬底的第二侧凹进，以暴露所述第一通孔，所述第一通孔从所述中介层的所述衬底的所述第二侧突出，其中，在所述凹进之后，所述中介层的所述衬底的厚度小于50μm；
在所述中介层的所述衬底的所述第二侧上形成聚合物层；
在所述聚合物层中形成金属化图案；
在所述聚合物层上形成第一组导电凸块，所述第一组导电凸块中的至少一个电耦合到所述金属化图案和暴露的第一通孔；
在使所述中介层的所述衬底的所述第二侧凹进之后，在所述第一通孔的侧壁上以及在所述中介层的所述衬底的凹进的第二侧上形成第一介电层；以及
在所述第一介电层上形成第二介电层，所述聚合物层位于所述第二介电层上。
2.根据权利要求1所述的方法，还包括：
在所述中介层的所述第一侧上形成再分布结构，所述再分布结构包括多个介电层，所述多个介电层中有金属化图案，所述金属化图案电耦合到所述第一通孔。
3.根据权利要求1所述的方法，还包括：
在所述第一管芯与所述中介层的所述衬底之间形成底部填充物；以及
用密封剂密封所述第一管芯和所述底部填充物。
4.根据权利要求1所述的方法，其中，在所述使所述中介层的所述衬底的所述第二侧凹进之后，所述中介层的所述衬底的厚度在1μm至50μm的范围内。
5.根据权利要求1所述的方法，其中，在使所述中介层的所述衬底的所述第二侧凹进之后，所述第一管芯比所述中介层的所述衬底厚。
6.根据权利要求1所述的方法，其中，所述中介层的所述衬底包括硅。
7.根据权利要求1所述的方法，其中，所述第一介电层是共形层，并且其中，所述第二介电层是非共形层。
8.根据权利要求1所述的方法，其中，所述第一通孔包括导电材料。
9.根据权利要求1所述的方法，其中，所述聚合物层的杨氏模量在1吉帕斯卡(GPa)至10吉帕斯卡的范围内。
10.根据权利要求1所述的方法，还包括：
将封装件衬底接合到所述第一组导电凸块，所述第一组导电凸块中的所述至少一个通过所述中介层电耦合到所述第一管芯。
11.一种形成半导体封装件的方法，包括：
将第一管芯和第二管芯接合到中介层，所述中介层包括：
再分布结构，所述再分布结构包括一个或多个金属化图案，所述一个或多个金属化图案将所述第一管芯电连接到所述第二管芯；
衬底，所述衬底与所述第一管芯和所述第二管芯位于所述再分布结构的相对侧上；以及
多个衬底通孔，所述多个衬底通孔延伸穿过所述衬底，所述多个衬底通孔电耦合到所述再分布结构的所述一个或多个金属化图案；
在所述衬底的与所述再分布结构相对的表面上形成缓冲结构，所述缓冲结构包括聚合物层；
穿过所述缓冲结构图案化多个开口，所述多个开口中的每一个使所述多个衬底通孔中的一个暴露；
在所述多个开口中形成第一金属化图案，所述第一金属化图案电耦合到所述多个衬底通孔；以及
在所述第一金属化图案上形成多个第一连接件。
12.根据权利要求11所述的方法，其中，所述聚合物层是聚酰亚胺。
13.根据权利要求11所述的方法，其中，所述聚合物层的杨氏模量在1吉帕斯卡(GPa)至10吉帕斯卡的范围内。
14.根据权利要求11所述的方法，其中，所述中介层的所述衬底的厚度小于50μm。
15.根据权利要求11所述的方法，其中，所述第一管芯比所述中介层的所述衬底厚。
16.根据权利要求11所述的方法，还包括：
在所述第一管芯、所述第二管芯和所述中介层之间形成底部填充物；以及
用密封剂密封所述第一管芯、所述第二管芯和所述底部填充物。
17.根据权利要求11所述的方法，还包括：
使所述衬底的与所述再分布结构相对的所述表面凹进，其中，在所述凹进之后，所述多个衬底通孔从所述中介层的所述衬底突出。
18.一种半导体封装件，包括：
第一管芯，接合到中介层，所述中介层包括：
再分布结构，所述再分布结构包括一个或多个金属化图案，所述一个或多个金属化图案将所述第一管芯电连接到第二管芯；
衬底，所述衬底与所述第一管芯和所述第二管芯位于所述再分布结构的相对侧上；以及
多个衬底通孔，所述多个衬底通孔延伸穿过所述衬底，所述多个衬底通孔电耦合到所述再分布结构的所述一个或多个金属化图案；
缓冲结构，位于所述衬底的与所述再分布结构相对的表面上，所述缓冲结构包括聚合物层；
第一金属化图案，位于所述缓冲结构中，所述第一金属化图案电耦合到所述多个衬底通孔；以及
多个第一连接件，电耦合到所述第一金属化图案。
19.根据权利要求18所述的半导体封装件，其中，所述中介层的所述衬底的厚度小于50μm。
20.根据权利要求18所述的半导体封装件，其中，所述第一管芯比所述中介层的所述衬底厚。
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