CN110660783B - 半导体器件封装件和方法 - Google Patents

半导体器件封装件和方法 Download PDF

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Publication number
CN110660783B
CN110660783B CN201811509903.7A CN201811509903A CN110660783B CN 110660783 B CN110660783 B CN 110660783B CN 201811509903 A CN201811509903 A CN 201811509903A CN 110660783 B CN110660783 B CN 110660783B
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die
topmost
dummy
carrier substrate
integrated circuit
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CN110660783A (zh
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余振华
叶松峯
陈明发
陈宪伟
刘惠雯
袁景滨
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在实施例中，一种方法包括：堆叠多个第一管芯以形成器件堆叠件；暴露器件堆叠件的最顶部管芯的测试焊盘；使用最顶部管芯的测试焊盘测试器件堆叠件；以及在测试器件堆叠件之后，在最顶部管芯中形成接合焊盘，其中，接合焊盘与测试焊盘不同。本发明的实施例还涉及半导体器件封装件和方法。

Description

半导体器件封装件和方法
技术领域
本发明的实施例涉及半导体器件封装件和方法。
背景技术
随着集成电路(IC)的发展，由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体产业已经经历了快速增长。在大多数情况下，集成密度的这种改进来自最小部件尺寸的不断减小，这允许将更多的组件集成到给定区域中。
这些集成改进本质上是二维的(2D)，因为集成组件占据的区域大致是在半导体晶圆的表面上。集成电路的密度增加和面积的相应减小通常超过了将集成电路芯片直接接合到衬底上的能力。中介层已经用于将来自芯片的球接触区重新分配至中介层的更大区域。此外，中介层已经允许包括多个芯片的三维(3D)封装件。也已经开发出其他封装件来结合3D方面。
发明内容
本发明的实施例提供了一种形成半导体器件的方法，包括：堆叠多个第一管芯以形成器件堆叠件；暴露所述器件堆叠件的最顶部管芯的测试焊盘；使用所述最顶部管芯的所述测试焊盘测试所述器件堆叠件；以及在测试所述器件堆叠件之后，在所述最顶部管芯中形成接合焊盘，其中，所述接合焊盘与所述测试焊盘不同。
本发明的另一实施例提供了一种形成半导体器件的方法，包括：将第一管芯接合至第一载体衬底；在所述第一管芯上堆叠多个第二管芯和多个伪器件以形成器件堆叠件；将第二载体衬底接合至所述器件堆叠件的所述多个第二管芯和所述多个伪器件；从所述第一管芯去除所述第一载体衬底；在所述第一管芯上形成导电凸块；使用所述第一管芯的所述导电凸块测试所述第一管芯和所述器件堆叠件；以及分割所述第二载体衬底和所述伪器件的部分以形成第一器件封装件。
本发明的又一实施例提供了一种半导体器件，包括：第一管芯，具有第一功能；器件堆叠件，位于所述第一管芯上，所述器件堆叠包括多个层，每个层包括：第二管芯，具有第二功能；伪器件，与所述第二管芯相邻，所述伪器件包括对准标记；以及密封剂，设置在所述伪器件和所述第二管芯之间；以及第一衬底，位于所述器件堆叠件上，所述第一衬底包括对准标记。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1是根据一些实施例的集成电路器件的截面图。
图2A至图2L是根据一些实施例的在形成器件封装件的工艺期间的中间步骤的各个图。
图3是根据一些实施例的伪器件的截面图。
图4A至图4D是根据各个实施例的对准标记的平面图。
图5A至图5J是根据一些实施例的在形成器件封装件的工艺期间的中间步骤的各个图。
图6A和图6B示出根据各个实施例的器件封装件的变型。
图7A至图7C是示出根据各个实施例的处于不同制造阶段的器件堆叠件的顶视图。
图8A至图8C是根据一些实施例的器件封装件层的平面图。
图9A至图9H是根据一些实施例的在形成器件封装件的工艺期间的中间步骤的各个图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，在载体衬底上形成器件堆叠件。器件堆叠件可以是例如包括多个存储器管芯的存储器立方体。然后从载体衬底去除器件堆叠件，并且使用专用测试垫进行测试。仅已知良好器件堆叠件用于后续处理，这可以提高制造产量。此外，在一些实施例中，将伪器件添加至器件堆叠件层。伪器件可以改善器件堆叠件的散热。最后，在一些实施例中，伪器件包括对准标记。通过使用用于对准的伪器件，可以从器件堆叠件的管芯省略对准标记，这可以增加管芯的可用布线面积。
图1是根据一些实施例的集成电路器件50的截面图。集成电路器件50可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、芯片上系统(SoC)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。可以在晶圆(未示出)中形成集成电路器件50，其中，晶圆可以包括在后续步骤中分割以形成多个集成电路器件50的不同器件区。将堆叠集成电路器件50以在后续处理中形成器件封装件。集成电路器件50包括衬底52、导电通孔54、互连结构56、测试焊盘58、介电层60、接合焊盘62和导电通孔64。
衬底52可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。衬底52的半导体材料可以是硅、锗、包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或它们的组合。还可以使用诸如多层衬底或梯度衬底的其他衬底。衬底52可以是掺杂的或未掺杂的。可以在衬底52的有源表面(例如，面朝上的表面)中和/或上形成诸如晶体管、电容器、电阻器、二极管等的器件(未示出)。
导电通孔54形成为从衬底52的有源表面延伸到衬底52中。在一些实施例中，导电通孔54在最初形成时不延伸到衬底52的背面(例如，面朝下、与有源表面相对的表面)。导电通孔54有时也称为衬底通孔或当衬底52是硅衬底时，称为硅通孔(TSV)。可以通过例如蚀刻、铣削、激光技术、它们的组合等在衬底52中形成凹槽来形成导电通孔54。可以诸如通过使用氧化技术在凹槽中形成薄的介电材料。可以诸如通过CVD、ALD、PVD、热氧化、它们的组合等在衬底52的有源表面上方且在开口中共形地沉积薄的阻挡层。阻挡层可以由诸如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、它们的组合等的氧化物、氮化物或氮氧化物形成。可以在阻挡层上方且在开口中沉积导电材料。可以通过电化学镀工艺、CVD、ALD、PVD、它们的组合等形成导电材料。导电材料的实例是铜、钨、铝、银、金、它们的组合等。通过例如化学机械抛光(CMP)从衬底52的有源表面去除多余的导电材料和阻挡层。导电通孔54共同地包括阻挡层和导电材料，其中，阻挡层位于导电材料和衬底52之间。
在衬底52的有源表面上、在导电通孔54上方形成具有一个或多个介电层和相应的金属化图案的互连结构56。介电层可以是金属间介电(IMD)层。例如，可以通过本领域内已知的任何合适的方法(诸如，旋涂、化学汽相沉积(CVD)、等离子体增强的CVD(PECVD)、高密度等离子体化学汽相沉积(HDP-CVD))由低K介电材料(诸如，未掺杂的硅酸盐玻璃、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成IMD层。一个或多个介电层中的一个或多个金属化图案可以诸如通过使用通孔和/或迹线布线在衬底52的器件之间的电信号，并且还可以包括诸如电容器、电阻器、电感器等的各个电子器件。此外，导电通孔54电连接至金属化图案。金属化图案可以由诸如铜、铝等或它们的组合的导电材料形成。可以互连各个器件和金属化图案以实施一个或多个功能。该功能可以包括存储器结构、处理结构、传感器、放大器、功率分配器、输入/输出电路等。额外地，在互连结构56中和/或上形成诸如导电柱或接触焊盘的连接件以提供至电路和器件的外部电连接。提供上述实例仅用于说明目的，并且其他实施例可以使用更少或额外的元件。可以适当使用其他电路以用于给定应用。
测试焊盘58是形成在互连结构56中和/或上的连接件的子组。测试焊盘58用于后续的器件测试步骤，并且在集成电路器件50的正常操作期间不电连接或有效。在一些实施例中，测试焊盘58由比互连结构56中的金属化图案的导电材料更低成本的导电材料(例如，铝)形成。
介电层60覆盖测试焊盘58并且位于互连结构56上方。介电层60包括诸如氮化硅、氧化硅等的一层或多层不可光图案化的介电材料。在一些实施例中，介电层60后续用于接合，并且可以是诸如氧化硅的氧化物。可以使用CVD、PVD、ALD、旋涂工艺、它们的组合等形成介电层60。
接合焊盘62形成在介电层60中并且通过导电通孔64物理地连接且电连接至互连结构56。接合焊盘62和导电通孔64包括导电材料，其中，该导电材料可以是包括诸如铜、银、金、钨、钴、铝或它们的合金的金属或金属合金的金属材料。在一些实施例中，使用双镶嵌工艺形成接合焊盘62和导电通孔64。作为这种工艺的实例，可以在介电层60中形成用于接合焊盘62和导电通孔64的开口，在开口中沉积薄的晶种层，并且使用诸如ECP或化学镀将导电材料从晶种层填充在开口中。可以实施诸如CMP的平坦化工艺，从而使得接合焊盘62和介电层60的顶面齐平。在一些实施例中，接合焊盘62和测试焊盘58由不同的导电材料形成。
图2A至图2L是根据一些实施例的在形成器件封装件的工艺期间的中间步骤的各个截面图。如将在下面更详细讨论的，图2A至图2L示出通过堆叠多个第一集成电路器件(诸如图1中所示的集成电路器件50)形成器件堆叠件102的工艺，并且在实施例中，第一集成电路器件可以是存储器管芯。以自顶向下(或反向)的方式形成器件堆叠件102，其中，第一集成电路器件50的最顶部器件面朝下附接至载体，并且器件堆叠件102的下面的层后续附接至最顶部器件。器件堆叠件102在形成之后进行测试以减少或防止对已知坏芯片堆叠件的后续处理。
后续地，将器件堆叠件102附接至第二集成电路器件120(参见例如图2I)以形成第一器件封装件100(参见例如图2I)。第二集成电路器件120可以具有与集成电路器件50类似的结构，并且在实施例中第二集成电路器件120可以是逻辑管芯。在实施例中，第一器件封装件100是晶圆上芯片(CoW)封装件，但是应当理解，实施例可以应用于其他3DIC封装件。然后通过将第一器件封装件100安装至衬底来形成第二器件封装件150(参见例如图2L)。在实施例中，第二器件封装件150是衬底上晶圆上芯片(CoWoS)封装件，但是应当理解，实施例可以应用于其他3DIC封装件。
现在参考图2A，在第一载体衬底104上沉积接合层106，并且最顶部集成电路器件50A附接至接合层106。第一载体衬底104可以是玻璃载体衬底、陶瓷载体衬底、硅晶圆等。可以在第一载体衬底104上同时形成多个器件封装件。接合层106可用于将最顶部集成电路器件50A附接至第一载体衬底104。在一些实施例中，第一载体衬底104是硅晶圆。在这种实施例中，接合层106包括诸如氧化硅或氮化硅的含硅介电材料，并且可以使用CVD、PVD、旋涂等形成。介电材料可以用于诸如氧化物至氧化物接合的接合，其中，最顶部集成电路器件50A的介电层60接合至接合层106。在一些实施例中，第一载体衬底104是玻璃。在这种实施例中，接合层106包括诸如光热转换(LTHC)释放涂层、紫外(UV)胶等的释放层。释放层可以是粘合剂，并且可以用于将最顶部集成电路器件50A粘附至第一载体衬底104。最顶部集成电路器件50A可以在附接之前进行测试，从而使得仅使用已知良好管芯来形成器件堆叠件102。
最顶部集成电路器件50A可以类似于上面参考图1讨论的集成电路器件50，除了在粘附至第一载体衬底104之前不形成接合焊盘62和导电通孔64之外。如将在下面进一步讨论的，器件堆叠件102在形成之后进行测试。因为最顶部集成电路器件50A位于器件堆叠件102的最顶层，所以最顶部集成电路器件50A的测试焊盘58将用于器件测试。可以在测试之后形成最顶部集成电路器件50A的接合焊盘62和导电通孔64，以防止在测试期间损坏接合焊盘62。
在图2B中，在最顶部集成电路器件50A周围且在第一载体衬底104上方形成最顶部密封剂110A。最顶部密封剂110A可以是模塑料、环氧树脂等，并且可以通过压缩模制、传递模制等来施加。可以在最顶部集成电路器件50A和第一载体衬底104上方形成最顶部密封剂110A，从而使得它们被掩埋或覆盖。然后固化最顶部密封剂110A。通过例如CMP削薄最顶部密封剂110A和最顶部集成电路器件50A，以暴露最顶部集成电路器件50A的导电通孔54。在削薄之后，最顶部密封剂110A和导电通孔54的表面与最顶部集成电路器件50A的背面齐平。
在图2C中，中间集成电路器件50B附接至最顶部集成电路器件50A。特别地，中间集成电路器件50B的有源表面附接至最顶部集成电路器件50A的背面。与最顶部集成电路器件50A不同，中间集成电路器件50B在粘附至最顶部集成电路器件50A时确实包括接合焊盘62和导电通孔64。中间集成电路器件50B可以在附接之前进行测试，从而使得仅使用已知良好管芯来形成器件堆叠件102。
在一些实施例中，通过混合接合附接集成电路器件50A和50B。在实施接合之前，可以对集成电路器件50A和50B实施表面处理。表面处理可以是等离子体处理工艺，并且用于产生等离子体的工艺气体可以是含氢气体，其中，该含氢气体包括含有氢气(H2)和氩气(Ar)的第一气体、含有H2和氮气(N2)的第二气体、或含有H2和氦(He)的第三气体。通过该处理，介电层60的表面处的OH基团的数量增加。接下来，可以实施预接合工艺，其中，集成电路器件50A和50B对准。集成电路器件50A和50B压在一起以在最顶部集成电路器件50A的衬底52和中间集成电路器件50B的介电层60之间形成弱键。在预接合工艺之后，对集成电路器件50A和50B进行退火以增强弱键并形成熔融接合。在退火期间，脱除OH键的H，从而在集成电路器件50A和50B之间形成Si-O-Si键，从而增强该键。在混合接合期间，在最顶部集成电路器件50A的导电通孔54和中间集成电路器件50B的接合焊盘62之间也发生直接的金属至金属接合。因此，所得到的接合是包括Si-O-Si键和金属-金属直接接合的混合接合。
在图2D中，在中间集成电路器件50B周围和第一载体衬底104上方形成中间密封剂110B。中间密封剂110B可以由从最顶部密封剂110A的候选材料选择的材料形成，或可以包括不同的材料。可以通过从形成最顶部密封剂110A的候选方法中选择的方法形成，或可以通过不同方法形成中间密封剂110B。
在图2E中，重复上述步骤，直到器件堆叠件102包括由最底部密封剂110C围绕的最底部集成电路器件50C。最底部集成电路器件50C可以不变薄，从而使得最底部集成电路器件50C的导电通孔54保持电绝缘。最底部集成电路器件50C可以在附接之前进行测试，从而使得仅使用已知良好管芯来形成器件堆叠件102。
应当理解，器件堆叠件102可包括任何数量的层。在所示实施例中，器件堆叠件102包括三层。在另一实施例中，器件堆叠件102包括两层或多于三层。
在图2F中，从第一载体衬底104去除器件堆叠件102，翻转器件堆叠件102并将器件堆叠件102附接至第二载体衬底112。在第一载体衬底104是硅晶圆并且接合层106是介电层的实施例中，可以通过蚀刻或研磨掉硅晶圆和介电层来实现去除。在第一载体衬底104是玻璃并且粘合层106是释放层的实施例中，可以通过将诸如激光或UV光的光投射到释放层上来实现去除，从而使得在光的热量下释放层分解并且脱粘玻璃。第二载体衬底112可以是硅晶圆，并且器件堆叠件102可以使用接合层114通过诸如氧化物至氧化物接合的接合来附接至第二载体衬底112。接合层114可以是与熔融接合兼容的诸如氧化硅的氧化物。可以诸如通过CVD等将接合层114施加至器件堆叠件102的背侧(诸如施加至最底部集成电路器件50C的背侧)，或可以施加在第二载体衬底112的表面上方。
在图2G中，通过使用探针116测试器件堆叠件102。通过图案化最顶部集成电路器件50A的介电层60以形成开口118来暴露最顶部集成电路器件50A的测试焊盘58。可以使用合适的光刻和蚀刻方法图案化介电层60。在一些实施例中，在介电层60上方形成光刻胶材料(未示出)。随后，照射(曝光)和显影光刻胶材料以去除光刻胶材料的部分。后续地，例如，使用合适的蚀刻工艺去除介电层60的暴露部分以形成开口118。然后探针116物理地连接且电连接至由开口118暴露的测试焊盘58。测试焊盘58用于测试器件堆叠件102，从而使得仅已知良好器件堆叠件用于进一步处理。测试可以包括测试各个集成电路器件的功能，或可以包括基于集成电路器件的设计预期的已知开路或短路的测试。在测试期间，可以以菊花链(daisy-chain)方式测试器件堆叠件102的所有集成电路器件。
在图2H中，去除探针116并填充开口118。可以通过在开口118中形成(例如，沉积)介电层60的更多介电材料来填充开口118，并且实施诸如CMP的平坦化以去除开口118外部的多余介电材料。然后使用上述技术在最顶部集成电路器件50A的介电层60中形成接合焊盘62和导电通孔64。值得注意的是，接合焊盘62与测试焊盘58不同。在测试完成之后，测试焊盘58可以在最顶部集成电路器件50A中保持未使用状态。
在图2I中，第二集成电路器件120附接至器件堆叠件102，从而形成第一器件封装件100。第二集成电路器件120可以实施与集成电路器件50A、50B和50C不同的功能。例如，集成电路器件50A、50B和50C可以是存储器器件，第二集成电路器件120可以是逻辑器件(例如，中央处理单元(CPU)、图形处理单元(GPU)、芯片上系统(SoC)、微控制器等)。可以使用最顶部集成电路器件50A的介电层60和接合焊盘62通过混合接合来将第二集成电路器件120附接至最顶部集成电路器件50A。可以在第二集成电路器件120周围并且在器件堆叠件102上方形成密封剂121。密封剂121可以由从最顶部密封剂110A的候选材料中选择的材料形成，或可以包括不同的材料。密封剂121可以通过从形成最顶部密封剂110A的候选方法中选择的方法形成，或可以通过不同方法来形成。
在图2J中，通过使用探针122测试第一器件封装件100。使用第二集成电路器件120的测试焊盘58测试第一器件封装件100。可以形成暴露第二集成电路器件120的测试焊盘58的开口124，并且可以使用与用于测试器件堆叠件102的方法类似的方法来测试第二集成电路器件120。测试可以包括测试第一器件封装件100的集成电路器件的功能，或可以包括基于集成电路器件的设计预期的已知开路或短路的测试。
在图2K中，去除探针122并填充开口124。可以使用与填充开口118的方法类似的方法填充开口124。然后在第二集成电路器件120上形成凸块126，并且在凸块126上形成导电连接件128。
凸块126可以是金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍钯浸金技术(ENEPIG)形成的凸块、球栅阵列(BGA)凸块等。在实施例中，凸块126是C4凸块。可以通过溅射、印刷、电镀、化学镀、CVD等形成凸块126。凸块126可以是无焊料的并且具有大致垂直的侧壁。在一些实施例中，在凸块126的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金等或它们的组合并且可以通过镀工艺形成。
导电连接件128可以由诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料形成。在一些实施例中，首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等的方法形成焊料层来形成导电连接件128。一旦已经在结构上形成焊料层，就可以实施回流，以将导电连接件128成形为期望的凸块形状。在一些实施例中，凸块126和导电连接件128都可以是焊料。
一旦完成第一器件封装件100的形成，就从形成在同一载体晶圆上的相邻器件封装件分割第一器件封装件100。可以通过例如锯切或激光切割进行分割。在一些实施例中，在分割之后保留第二载体衬底112。如将在下面进一步讨论的，第二载体衬底112有助于第一器件封装件100的散热。在一些实施例中，可以去除第二载体衬底112，并且可选地，可以附接诸如冷却系统的其他结构。在所示实施例中，在第一器件封装件100中电隔离最顶部集成电路器件50A的导电通孔54。这些导电通孔54可以是未使用的，从而使得相同的管芯可以用于在器件堆叠件102中堆叠。
在图2L中，通过将第一器件封装件100安装至封装衬底152来形成第二器件封装件150。封装衬底152可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、它们的组合等的化合物材料。额外地，封装衬底152可以是SOI衬底。通常，SOI衬底包括诸如外延的硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底152基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是诸如FR4的玻璃纤维树脂。用于芯材料的可选材料包括双马来酰亚胺-三嗪BT树脂，或者可选地，其他PCB材料或膜。诸如ABF或其他层压件的构建膜可用于封装衬底152。
封装衬底152可以包括有源器件和无源器件(未示出)。诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于产生用于第二器件封装件150的设计的结构和功能需求。可以使用任何合适的方法来形成器件。
封装衬底152还可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘154。金属化层可以形成在有源器件和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由具有互连导电材料层的通孔的介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)来形成。在一些实施例中，封装衬底152大致没有有源器件和无源器件。
在一些实施例中，回流导电连接件128以将第一器件封装件100附接至接合焊盘154，从而将第二集成电路器件120接合至封装衬底152。导电连接件128将封装衬底152(包括封装衬底152中的金属化层)电连接和/或物理连接至第一器件封装件100。在一些实施例中，在将无源器件(例如，表面安装器件(SMD)，未示出)安装至封装衬底152之前，可以将该无源器件附接至第二器件封装件150(例如，接合至接合焊盘154)。在这种实施例中，无源器件可以与导电连接件128接合至第二器件封装件150的相同表面。
在用第二器件封装件150附接至封装衬底152之后剩余的环氧树脂焊剂的环氧树脂部分的至少一些回流导电连接件128之前，导电连接件128可以具有形成在其上的环氧树脂焊剂(未示出)。剩余的环氧树脂部分可以用作底部填充物以减少应力并保护由于回流导电连接件128而产生的接头。
底部填充物(未示出)可以形成在第二集成电路器件120和封装衬底152之间，围绕导电连接件128。底部填充物可以在附接第一器件封装件100之后通过毛细管流动工艺形成，或可以在附接第一器件封装件100之前通过合适的沉积方法形成。
图3是根据一些实施例的伪器件300的截面图。伪器件300不实施电功能，并且其中没有形成有源器件或无源器件。而是，如将在下面进一步讨论的(例如，相对于图5A至图5J的实施例和图9A至图9H的实施例)，伪器件300可以包括在实施例器件封装件(例如，器件封装件550和950，参见下文)中以改善最终封装件的散热。伪器件300包括衬底302、隔离膜304、蚀刻停止层306、金属间介电(IMD)层308、对准标记310和接合膜312。
在衬底302上形成隔离膜304。衬底302可以由从衬底52的候选材料选择的材料形成，或可以包括不同的材料。衬底302可以通过从形成衬底52的候选方法中选择的方法形成，或可以通过不同的方法形成。隔离膜304有助于电隔离对准标记310。隔离膜304可以由诸如碳化硅、氮化硅等的介电材料形成，并且可以通过CVD、PVD等形成。在实施例中，隔离膜304形成为小于约
Figure BDA0001900449760000121
的厚度。
在隔离膜304上形成蚀刻停止层306。蚀刻停止层306可以由碳化硅、氮化硅、氮氧化硅、碳氮化硅等形成。可以通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、旋涂电介质工艺等或它们的组合来形成蚀刻停止层306。在实施例中，蚀刻停止层306形成为具有从约
Figure BDA0001900449760000131
至约
Figure BDA0001900449760000132
的厚度。
在蚀刻停止层306上方形成IMD层308。IMD层308可以是由k值低于约3.0的低k介电材料形成的层。IMD层308可以来自k值小于2.5的超低k(ELK)介电材料。在一些实施例中，IMD层308可以由Black Diamond(应用材料公司的注册商标)、含氧和/或含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。IMD层308可以是多孔材料。IMD层308也可以来自诸如氮化硅、氧化硅等的介电材料。在实施例中，IMD层308形成为具有从约
Figure BDA0001900449760000133
至约
Figure BDA0001900449760000134
的厚度。在一些实施例中，选择蚀刻停止层306和IMD层308的材料以在蚀刻停止层306和IMD层308之间实现高蚀刻选择性，并且因此蚀刻停止层306可用于在后续的处理步骤中停止IMD层308的蚀刻。
对准标记310形成在IMD层308中，并且可以延伸穿过蚀刻停止层306和隔离膜304。可以使用单镶嵌工艺形成对准标记310。作为形成对准标记310的实例，可以通过蚀刻工艺在IMD层308中形成开口(未示出)。蚀刻工艺可以去除IMD层308的材料并且可以不去除蚀刻停止层306的材料。一旦暴露蚀刻停止层306，可以实施不同的蚀刻工艺以使开口延伸穿过蚀刻停止层306。开口也可以至少部分地延伸到隔离膜304中。在开口中可选地形成一个或多个扩散阻挡层(未示出)，并且然后在扩散阻挡层(如果存在的话)上方形成导电材料。扩散阻挡层可以由TaN、Ta、TiN、Ti、CoW等形成，并且可以通过诸如ALD等的沉积工艺形成在开口中。导电材料可以包括铜、铝、钨、银以及它们的组合等，并且可以通过电化学镀工艺、CVD、ALD、PVD等或它们的组合在位于开口中的扩散阻挡层上方形成。在实施例中，导电材料是铜，并且扩散阻挡层是防止铜扩散到IMD层308中的薄的阻挡层。在形成扩散阻挡层和导电材料之后，可以通过例如平坦化工艺(诸如CMP)去除多余的扩散阻挡层和导电材料。
在对准标记310和IMD层308上形成接合膜312。接合膜312用于在后续步骤中进行诸如氧化物至氧化物接合的接合，并且由可用于与半导体衬底形成氧化物至氧化物接合的材料形成。在实施例中，接合膜312由诸如氧化硅的氧化物形成，并且可以使用CVD、PVD、ALD、旋涂工艺、它们的组合等形成。在实施例中，接合膜312形成为具有从约0.8μm至约2μm的厚度。
图4A至图4D是根据各个实施例的对准标记310的平面图。如图所示，对准标记310可以形成为在平面图中具有各种形状。例如，对准标记310可以具有闭合的正方形形状(参见图4A)、圆形(参见图4B)、十字形(参见图4C)或开口正方形形状(参见图4D)。应当理解，也可以使用其他形状。
图5A至图5J是根据一些实施例的在形成器件封装件的工艺期间的中间步骤的各个截面图。在图5A至图5J中，通过堆叠多个伪器件(诸如上面参考图3和图4A至图4D描述的伪器件300)和第一集成电路器件(诸如上面参考图1描述的集成电路器件50)来形成器件堆叠件502。器件堆叠件502可以在形成之后进行测试。然后用器件堆叠件502形成后续的器件封装件。形成具有伪器件300的器件堆叠件502有助于所得到的器件封装件的散热。此外，伪器件300中的对准标记310可以改善后续处理中的器件堆叠精度。器件封装件可以是CoW或CoWoS封装件，但是应当理解，实施例可以应用于其他3DIC封装件。
首先参考图5A，多个最顶部集成电路器件50A和伪器件300A粘附至第一载体衬底508。在一些实施例中，最顶部集成电路器件50A在粘附至第一载体衬底508时没有接合焊盘。最顶部集成电路器件50A可以在附接之前进行测试，从而使得仅使用已知良好管芯来形成器件堆叠件502。
第一载体衬底508可以由硅晶圆等形成，并且在硅晶圆中或上方形成对准标记510。可以以与伪器件300A的对准标记310类似的方式形成对准标记510。
最顶部集成电路器件50A和伪器件300A面朝下放置在第一载体衬底508上，并且使用诸如氧化物至氧化物接合的接合来分别粘附至介电层60和接合膜312。可以通过例如拾取和放置工艺进行放置。在放置期间，伪器件300A的对准标记310与第一载体衬底508的对准标记510对准，这可允许在拾取和放置工艺期间更准确地放置。可以在拾取和放置期间对准最顶部集成电路器件50A的拐角。在一些实施例中，在伪器件300A之前放置集成电路器件50A。在一些实施例中，在集成电路器件50A之前放置伪器件300A。关于如何使用对准标记310的细节将在下面进一步详细讨论。
在图5B中，在最顶部集成电路器件50A、伪器件300A周围并且在第一载体衬底508上方形成最顶部密封剂514A。最顶部密封剂514A可以由从最顶部密封剂110A(参见图2B)的候选材料中选择的材料形成，或可以包括不同的材料。最顶部密封剂514A可以通过从形成最顶部密封剂110A的候选方法中选择的方法形成，或可以通过不同的方法形成。通过例如CMP削薄最顶部密封剂514A、最顶部集成电路器件50A和伪器件300A，从而暴露最顶部集成电路器件50A的导电通孔54。
在图5C中，重复上述步骤以形成器件堆叠件502的额外层。中间集成电路器件50B和伪器件300B附接至最顶部集成电路器件50A和伪器件300A。同样，最底部集成电路器件50C和伪器件300C附接至中间集成电路器件50B和伪器件300B。中间集成电路器件50B和最底部集成电路器件50C在粘附时包括接合焊盘62。这样，每层的集成电路器件通过混合接合附接至下面的层。每个集成电路器件可以在附接之前进行测试，从而使得仅使用已知良好管芯来形成器件堆叠件502。
应当理解，器件堆叠件502可包括任何数量的层。在所示实施例中，器件堆叠件502包括四层(例如，最顶部集成电路器件50A和伪器件300A；两层中间集成电路器件50B和伪器件300B；以及最底部集成电路器件50C和伪器件300C)。在另一实施例中，器件堆叠件502包括诸如五层或两层的更多或更少数量的层。
在图5D中，第二载体衬底516使用接合层518通过诸如氧化物至氧化物接合的接合附接至器件堆叠件502。第二载体衬底516可以由硅晶圆等形成，并且在硅晶圆中或上方形成对准标记520。可以以与伪器件300A的对准标记310类似的方式形成对准标记520。第二载体衬底516的对准标记520与伪器件300A、300B和300C的对准标记310对准，从而使得可以更精确地放置第二载体衬底516。接合层518可以由从接合层114的候选材料中选择的材料形成，或可以包括不同的材料。接合层518可以通过从形成接合层114(参见图2F)的候选方法中选择的方法形成，或可以通过不同的方法形成。在实施例中，接合层518是与氧化物至氧化物接合兼容的诸如氧化硅的氧化物。
在图5E中，从第一载体衬底508去除器件堆叠件502并翻转器件堆叠件502。在第一载体衬底508是硅晶圆并且接合层518是介电层的实施例中，可以通过蚀刻或研磨掉硅晶圆和介电层来实现去除。然后可以测试器件堆叠件502，从而使得仅使用已知良好器件堆叠件进行进一步处理。类似于器件堆叠件102，最顶部集成电路器件50A可以包括用于测试的测试焊盘(未示出)。可以暴露用于测试的测试焊盘，然后在测试之后覆盖测试焊盘以使它们电隔离。测试焊盘可以由与接合焊盘62不同的材料形成。
在图5F中，在最顶部集成电路器件50A的介电层60中形成接合焊盘62。在测试之后，可以通过双镶嵌工艺形成接合焊盘62。值得注意的是，接合焊盘62与测试焊盘58(图5F中未示出，但如上图1所示)不同。
在图5G中，第二集成电路器件522通过与最顶部集成电路器件50A的接合焊盘62的混合接合而附接至器件堆叠件502，从而形成第一器件封装件500。第二集成电路器件522可以实施与集成电路器件50A、50B和50C不同的功能。在附接之前，可以测试第二集成电路器件522，从而使得仅使用已知良好管芯来形成第一器件封装件500。
在第二集成电路器件522周围形成密封剂524。密封剂524可以由从最顶部密封剂110A(参见图2B)的候选材料中选择的材料形成，或可以包括不同的材料。密封剂524可以通过从形成最顶部密封剂110A的候选方法中选择的方法形成，或可以通过不同的方法形成。通过例如CMP削薄密封剂524和第二集成电路器件522，从而使得它们具有齐平的表面。
在图5H中，在第二集成电路器件522的介电层60中形成开口，并且在开口中形成凸块526。凸块526可以由从凸块126(参见图2K)的候选材料中选择的材料形成，或可以包括不同的材料。凸块526可以通过从形成凸块126的候选方法中选择的方法形成，或可以通过不同的方法形成。
然后在凸块526上形成导电连接件528。导电连接件528可以由从导电连接件128(参见图2K)的候选材料中选择的材料形成，或可以包括不同的材料。导电连接件528可以通过从形成导电连接件128的候选方法中选择的方法形成，或可以通过不同的方法形成。然后可以使用导电连接件528通过探针测试第一器件封装件500，从而使得仅使用已知良好器件进行进一步处理。
在图5I中，从相邻的器件封装件分割第一器件封装件500。可以沿着划线530通过例如锯切或激光切割来进行分割。尽管未示出，但应当理解，可以沿着划线530设置第二载体衬底516的对准标记520。这样，分割工艺可以导致切割或去除一些对准标记520，从而使得第一器件封装件500中的第二载体衬底516的部分具有对准标记520的片段或部分。
在图5J中，通过将第一器件封装件500安装至封装衬底552来形成第二器件封装件550。封装衬底552可以类似于封装衬底152(参见图2L)。封装衬底552可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘554。第一器件封装件500的导电连接件528连接至封装衬底552的接合焊盘554以形成第二器件封装件550。
伪器件300A、300B和300C可以在第二集成电路器件522和第二载体衬底516之间形成热路径。这样，可以改善所得到的第二器件封装件550的散热。此外，通过在伪器件300A、300B和300C中形成对准标记310，可以从集成电路器件50A、50B和50C中省略对准标记。因此可以增加各个集成电路器件中的可用布线面积。
图6A和图6B示出根据各个实施例的第二器件封装件550的变型。在第一变型(例如，图6A)中，可以省略伪器件。这样，仅第二载体衬底516包括位于第二器件封装件550中的对准标记520。在形成期间，第二载体衬底516的对准标记520可以与第一载体衬底508的对准标记510(参见图5D)对准。在第二变型(例如，图6B)中，可以省略伪器件300和对准标记310。所示的变型可以具有较低的制造成本。
图7A至图7C是示出根据各个实施例的处于不同制造阶段的器件堆叠件502的顶视图。在所示实例中，图7A可以对应于放置最顶部集成电路器件50A(如图5A所示)，图7B可以对应于放置最顶部伪器件300A(如图5A所示)，并且图7C可以对应于放置中间集成电路器件50B和伪器件300B(如图5C所示)。示出对准标记310和510的使用。在图7A中，在第一载体衬底508上方放置集成电路器件50的第一层。在集成电路器件50之间设置第一载体衬底508的对准标记510。在图7B中，在位于集成电路器件50之间的第一载体衬底508上方设置伪器件300的第一层。第一层伪器件300的对准标记310与对准标记510的第一子组510A对准。在图7C中，在第一层上放置集成电路器件50和伪器件300的第二层。第二层伪器件300的对准标记310与对准标记510的第二子组510B对准。伪器件300的材料对于用于对准标记310的对准的光是透明的。此外，对准标记510的第一子组510A和第二子组510B可以具有不同的形状(参见例如图4A至图4D)。例如，第一层伪器件300可以与具有第一形状的下面的对准标记510对准，并且第二层伪器件300可以与具有第二形状的下面的对准标记510对准。此外，一些伪器件300可以具有多个横向偏移的对准标记310(参见图7C)，以确保在对准期间适当地旋转伪器件300。此外，在平面图或顶视图中，不同层中的伪器件300的对准标记310不重叠。
图8A至8C是根据一些实施例的第一器件封装件500(参见例如图5A至图5I)的一个层的平面图。相对于集成电路器件50示出伪器件300的布局。伪器件300可以以多种方式布置，并且可以具有多种形状。在一些实施例中(例如，图8A)，沿着集成电路器件50的两个边缘布置伪器件300。在一些实施例中(例如，图8B)，沿着集成电路器件50的四个边缘布置伪器件300。在一些实施例中(例如，图8C)，单个伪器件300围绕集成电路器件50。其他伪器件布局也是可能的。
图9A至图9H是根据一些实施例的在形成器件封装件的工艺期间的中间步骤的各个截面图。在图9A至图9H中，通过在第二集成电路器件上堆叠多个伪器件和第一集成电路器件来形成器件堆叠件902。第一集成电路器件可以具有与集成电路器件50(参见图1)类似的结构，并且在实施例中可以是存储器管芯。第二集成电路器件可以具有与集成电路器件50(参见图1)类似的结构，并且在实施例中，第二集成电路器件可以是逻辑管芯。伪器件可以具有与伪器件300(参见图3)类似的结构。器件堆叠件902在形成之后进行测试。
在图9A中，第一集成电路器件904附接至第一载体衬底906。第一载体衬底906可以由硅晶圆等形成，并且在硅晶圆中或上方形成对准标记908。可以以与伪器件300(参见图3)的对准标记310类似的方式形成对准标记908。第一集成电路器件904可以放置在第一载体衬底906上并且使用第一集成电路器件904的介电层60通过诸如氧化物至氧化物接合的接合而进行附接。第一集成电路器件904可以在附接之前进行测试，从而使得仅已知良好管芯用于处理。
在图9B中，在第一集成电路器件904周围形成第一密封剂912。第一密封剂912可以由从最顶部密封剂110A(参见图2B)的候选材料中选择的材料形成，或可以包括不同的材料。第一密封剂912可以通过从形成最顶部密封剂110A的候选方法中选择的方法形成，或可以通过不同的方法形成。通过例如CMP削薄第一密封剂912和第一集成电路器件904，从而暴露第一集成电路器件904的导电通孔54。
在图9C中，在第一集成电路器件904上形成器件堆叠件902。器件堆叠件902包括多层集成电路器件50A-50D、伪器件300A-300D和密封剂918A-918D。可以不平坦化集成电路器件50D和伪器件300D的最底层，从而使得集成电路器件50D的导电通孔54保持绝缘。可以使用例如诸如氧化物至氧化物接合的接合来附接每个层。在放置期间，伪器件300A-300D的对准标记310与第一载体衬底906的对准标记908对准。
在图9D中，使用介电层922通过诸如氧化物至氧化物接合的接合而将第二载体衬底920附接至器件堆叠件902，从而形成第一器件封装件900。第二载体衬底920可以由从第二载体衬底112的候选材料中选择的材料形成，或可以包括不同的材料。第二载体衬底920包括对准标记924，在放置期间，对准标记924与集成电路器件50A-50D的对准标记310对准。
在图9E中，从第一集成电路器件904去除第一载体衬底906。在第一载体衬底906是硅晶圆的实施例中，可以通过蚀刻或研磨掉硅晶圆和介电层来实现去除。
在图9F中，在第一集成电路器件904的介电层60中形成开口，并且在开口中形成凸块926。凸块926可以由从凸块126(参见图2K)的候选材料中选择的材料形成，或可以包括不同的材料。凸块926可以通过从形成凸块126的候选方法中选择的方法形成，或可以通过不同的方法形成。
然后在凸块926上形成导电连接件928。导电连接件928可以由从导电连接件128的候选材料中选择的材料形成，或可以包括不同的材料。导电连接件928可以通过从形成导电连接件128的候选方法中选择的方法形成，或可以通过不同的方法形成。然后可以使用导电连接件928通过探针测试第一器件封装件900，从而使得仅使用已知良好器件进行进一步处理。
在图9G中，从相邻的器件封装件分割第一器件封装件900。可以沿着划线930通过例如锯切或激光切割来进行分割。可以沿着划线930设置第二载体衬底920的对准标记924。这样，分割工艺可以导致切割或去除一些对准标记924，从而使得第一器件封装件900中的第二载体衬底920的部分具有对准标记924的片段或部分。
在图9H中，通过将第一器件封装件900安装至封装衬底952来形成第二器件封装件950。封装衬底952可以类似于封装衬底152(参见图2L)。封装衬底952可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘954。第一器件封装件900的导电连接件928连接至封装衬底952的接合焊盘954，以形成第二器件封装件950。
实施例可以实现优势。通过在进一步处理之前测试器件堆叠件(例如存储器立方体)，可以使用已知良好立方体进行处理，从而提高器件封装件产量。此外，在器件封装件中使用伪器件可以改善所得到的器件封装件的热性能。最后，将对准标记放置在伪器件中可以允许存储器立方体中的器件省略对准标记，这可以增加存储器立方体中的器件的布线面积。
在实施例中，一种方法包括：堆叠多个第一管芯以形成器件堆叠件；暴露器件堆叠件的最顶部管芯的测试焊盘；使用最顶部管芯的测试焊盘测试器件堆叠件；以及在测试器件堆叠件之后，在最顶部管芯中形成接合焊盘，其中，接合焊盘与测试焊盘不同。
在一些实施例中，该方法还包括：在测试器件堆叠件之后，覆盖最顶部管芯的测试焊盘。在该方法的一些实施例中，堆叠多个第一管芯包括：将最顶部管芯接合至第一载体衬底，其中，在接合期间，最顶部管芯包括位于测试焊盘上方的介电层，并且没有接合焊盘；以及在最顶部管芯上方堆叠最底部管芯，其中，在堆叠期间，最底部管芯包括接合焊盘和位于接合焊盘上方的介电层。在该方法的一些实施例中，将最顶部管芯接合至第一载体衬底包括与最顶部管芯的介电层形成氧化物至氧化物键，并且将最底部管芯堆叠在最顶部管芯上方包括实施与最底部管芯的接合焊盘和介电层的混合接合。在该方法的一些实施例中，堆叠多个第一管芯还包括：用最顶部密封层密封最顶部管芯；以及在密封最顶部管芯之后，用最底部密封层密封最底部管芯。在该方法的一些实施例中，堆叠多个第一管芯还包括：用最顶部密封层密封最顶部伪器件；以及在密封最顶部伪器件之后，用最底部密封层密封最底部伪器件。在一些实施例中，该方法还包括：在最顶部伪器件和最底部伪器件中形成对准标记。在一些实施例中，该方法还包括：在第一载体衬底中形成对准标记；并且将最顶部伪器件和最底部伪器件的对准标记与第一载体衬底的对准标记对准。在一些实施例中，该方法还包括：将器件堆叠件的最底部管芯接合至第二载体衬底；从第一载体衬底去除器件堆叠件。在一些实施例中，该方法还包括：使用接合焊盘将第二管芯接合至器件堆叠件的最顶部管芯。
在实施例中，一种方法包括：将第一管芯接合至第一载体衬底；在第一管芯上堆叠多个第二管芯和多个伪器件以形成器件堆叠件；将第二载体衬底接合至器件堆叠件的多个第二管芯和多个伪器件；从第一管芯去除第一载体衬底；在第一管芯上形成导电凸块；使用第一管芯的导电凸块测试第一管芯和器件堆叠件；以及分割第二载体衬底和伪器件的部分以形成第一器件封装件。
在该方法的一些实施例中，第一载体衬底包括第一对准标记，其中，伪器件包括第二对准标记，并且还包括：当在第一管芯上堆叠伪器件时，将多个伪器件的第二对准标记与第一载体衬底的第一对准标记对准。在该方法的一些实施例中，第二载体衬底包括第三对准标记，并且还包括：当第二载体衬底接合至伪器件时，将第二载体衬底的第三对准标记与多个伪器件的第二对准标记对准。在该方法的一些实施例中，第二对准标记的第一子组具有第一形状，并且第二对准标记的第二子组具有第二形状，在器件堆叠件的不同层中设置对准标记的第一子组和第二子组。在该方法的一些实施例中，分割伪器件的部分包括在分割期间切割第二对准标记。在一些实施例中，该方法还包括：在不使用对准标记的情况下在第一载体衬底上方将第一管芯和第二管芯对准。
在实施例中，一种器件包括：第一管芯，具有第一功能；器件堆叠件，位于第一管芯上，其中，器件堆叠件包括多个层，每个层包括：具有第二功能的第二管芯；伪器件，与第二管芯相邻，其中，伪器件包括对准标记；以及密封剂，设置在伪器件和第二管芯之间；以及第一衬底，位于器件堆叠件上，第一衬底包括对准标记。
在该器件的一些实施例中，每个层的伪器件包括对准标记。在该器件的一些实施例中，不同层中的对准标记具有不同的形状。在该器件的一些实施例中，每个层中的伪器件的对准标记在平面图中不重叠。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成半导体器件的方法，包括：
堆叠多个第一管芯和分别与所述多个第一管芯相邻的多个伪器件以形成器件堆叠件；
暴露所述器件堆叠件的最顶部管芯的测试焊盘；
使用所述最顶部管芯的所述测试焊盘测试所述器件堆叠件；以及
在测试所述器件堆叠件之后，在所述最顶部管芯中形成接合焊盘，其中，所述接合焊盘与所述测试焊盘不同，
其中，堆叠所述多个第一管芯包括：
将所述最顶部管芯接合至第一载体衬底，其中，在所述接合期间，所述最顶部管芯包括位于所述测试焊盘上方的介电层，并且没有所述接合焊盘；
在所述最顶部管芯上方堆叠最底部管芯，其中，在所述堆叠期间，所述最底部管芯包括所述接合焊盘和位于所述接合焊盘上方的介电层。
2.根据权利要求1所述的方法，还包括：
在测试所述器件堆叠件之后，覆盖所述最顶部管芯的所述测试焊盘。
3.根据权利要求1所述的方法，其中，堆叠多个第一管芯和分别与所述多个第一管芯相邻的多个伪器件以形成器件堆叠件还包括：
分别在所述多个第一管芯和所述多个伪器件之间形成密封剂。
4.根据权利要求1所述的方法，其中，将所述最顶部管芯接合至所述第一载体衬底包括与所述最顶部管芯的所述介电层形成氧化物至氧化物接合，并且将所述最底部管芯堆叠在所述最顶部管芯上方包括实施与所述最底部管芯的所述接合焊盘和所述介电层的混合接合。
5.根据权利要求1所述的方法，其中，堆叠所述多个第一管芯还包括：
用最顶部密封层密封所述最顶部管芯；以及
在密封所述最顶部管芯之后，用最底部密封层密封所述最底部管芯。
6.根据权利要求5所述的方法，其中，堆叠所述多个第一管芯还包括：
用所述最顶部密封层密封最顶部伪器件；以及
在密封所述最顶部伪器件之后，用所述最底部密封层密封最底部伪器件。
7.根据权利要求6所述的方法，还包括：
在所述最顶部伪器件和所述最底部伪器件中形成对准标记。
8.根据权利要求7所述的方法，还包括：
在所述第一载体衬底中形成对准标记；以及
将所述最顶部伪器件和所述最底部伪器件的对准标记与所述第一载体衬底的对准标记对准。
9.根据权利要求3所述的方法，还包括：
将所述器件堆叠件的所述最底部管芯接合至第二载体衬底；以及
从所述第一载体衬底去除所述器件堆叠件。
10.根据权利要求1所述的方法，还包括：
使用所述接合焊盘将第二管芯接合至所述器件堆叠件的所述最顶部管芯。
11.一种形成半导体器件的方法，包括：
将第一管芯接合至第一载体衬底；
在所述第一管芯上堆叠多个第二管芯和多个伪器件以形成器件堆叠件；
将第二载体衬底接合至所述器件堆叠件的所述多个第二管芯和所述多个伪器件；
从所述第一管芯去除所述第一载体衬底；
在所述第一管芯上形成导电凸块；
使用所述第一管芯的所述导电凸块测试所述第一管芯和所述器件堆叠件；以及
分割所述第二载体衬底和所述伪器件的部分以形成第一器件封装件。
12.根据权利要求11所述的方法，其中，所述第一载体衬底包括第一对准标记，其中，所述伪器件包括第二对准标记，并且还包括：
当在所述第一管芯上堆叠所述伪器件时，将所述多个伪器件的所述第二对准标记与所述第一载体衬底的所述第一对准标记对准。
13.根据权利要求12所述的方法，其中，所述第二载体衬底包括第三对准标记，并且还包括：
当将所述第二载体衬底接合至所述伪器件时，将所述第二载体衬底的所述第三对准标记与所述多个伪器件的所述第二对准标记对准。
14.根据权利要求13所述的方法，其中，所述第二对准标记的第一子组具有第一形状，并且所述第二对准标记的第二子组具有第二形状，在所述器件堆叠件的不同层中设置所述对准标记的第一子组和第二子组。
15.根据权利要求12所述的方法，其中，分割所述伪器件的部分包括在所述分割期间切割所述第二对准标记。
16.根据权利要求11所述的方法，还包括：在不使用对准标记的情况下，在所述第一载体衬底上方将所述第一管芯和所述第二管芯对准。
17.一种半导体器件，包括：
第一管芯，具有第一功能；
器件堆叠件，位于所述第一管芯上，所述器件堆叠包括多个层，每个层包括：
第二管芯，具有第二功能；
伪器件，与所述第二管芯相邻，所述伪器件包括对准标记；以及
密封剂，设置在所述伪器件和所述第二管芯之间；以及
第一衬底，位于所述器件堆叠件上，所述第一衬底包括对准标记，
其中，所述器件堆叠件的最顶部第二管芯包括位于测试焊盘上方的介电层，并且没有接合焊盘；
所述器件堆叠件的最底部第二管芯包括所述接合焊盘和位于所述接合焊盘上方的介电层。
18.根据权利要求17所述的半导体器件，其中，每个所述层的所述伪器件包括所述对准标记。
19.根据权利要求18所述的半导体器件，其中，不同的所述层中的对准标记具有不同的形状。
20.根据权利要求17所述的半导体器件，其中，每个所述层中的所述伪器件的对准标记在平面图中不重叠。
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