CN112164688B - 芯片堆叠结构及管芯堆叠结构的制造方法 - Google Patents

芯片堆叠结构及管芯堆叠结构的制造方法 Download PDF

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CN112164688B
CN112164688B CN202011054090.4A CN202011054090A CN112164688B CN 112164688 B CN112164688 B CN 112164688B CN 202011054090 A CN202011054090 A CN 202011054090A CN 112164688 B CN112164688 B CN 112164688B
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chip
substrate
contact conductor
die
stack structure
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CN112164688A (zh
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林明哲
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种芯片堆叠结构及管芯堆叠结构的制造方法。该芯片堆叠结构包括第一芯片和第二芯片。第二芯片位于第一芯片上。第一芯片包括第一衬底、第一内连线结构、第一焊垫和第一接触导体。第一内连线结构位于第一衬底的第一表面上。第一焊垫位于第一内连线结构上。第一接触导体位于第一衬底中，且暴露于第一衬底的相对于第一表面的第二表面。第二芯片包括第二衬底、第二内连线结构、第二焊垫和第二接触导体。第二内连线结构位于第二衬底上。第二焊垫位于第二内连线结构上。第二接触导体位于第二衬底中，其中第一接触导体直接实体接触第二焊垫。本发明的芯片堆叠结构及管芯堆叠结构的制造方法的制作工艺简单且具有高制作工艺良率。

Description

芯片堆叠结构及管芯堆叠结构的制造方法
本申请是中国发明专利申请(申请号：201710600400.X，申请日：2017年07月21日，发明名称：芯片堆叠结构及管芯堆叠结构的制造方法)的分案申请。
技术领域
本发明涉及一种半导体结构及其制造方法，且特别是涉及一种芯片堆叠结构及管芯堆叠结构的制造方法。
背景技术
随着电子制造技术的发展，越来越多的电子产品以可携性、高功能性以及轻薄短小为发展目标，致使其所搭配的芯片的功能性及其所包含的电路装置也势必会越来越多且越来越复杂。在此需求下，三维集成电路(three dimension integrated circuit,3D IC)的设计逐渐受到重视。
然而，三维集成电路除了需要面对晶片薄型化、芯片堆叠等相关技术层面的问题外，集成电路的前段与后段制作工艺也出现了隐藏于制造细节上的问题，其高成本与低良率产量为此项技术的主要问题。因此，如何降低三维集成电路的制造成本并提升其制作工艺良率，实为目前研发人员亟欲解决的议题之一。
发明内容
本发明提供一种芯片堆叠结构及管芯堆叠结构的制造方法，其制作工艺简单且具有高制作工艺良率。
本发明的一实施例提供一种芯片堆叠结构，其包括第一芯片和第二芯片。第二芯片位于第一芯片上。第一芯片包括第一衬底、第一内连线结构、第一焊垫和第一接触导体。第一内连线结构位于第一衬底的第一表面上。第一焊垫位于第一内连线结构上。第一接触导体位于第一衬底中，且暴露于第一衬底的相对于第一表面的第二表面。第二芯片包括第二衬底、第二内连线结构、第二焊垫和第二接触导体。第二内连线结构位于第二衬底上。第二焊垫位于第二内连线结构上。第二接触导体位于第二衬底中，其中第一接触导体直接实体接触第二焊垫。
在本发明一实施例中，第一接触导体未覆盖第一衬底的第二表面。
在本发明的一实施例中，还包括承载板，其位于第一芯片的下方。
在本发明一实施例中，承载板包括承载芯片，且第一芯片的第一焊垫连接至承载芯片的焊垫。
在本发明一实施例中，承载芯片的厚度大于第一芯片的厚度。
在本发明一实施例中，还包括介电层，其位于第一芯片和第二芯片之间。
在本发明一实施例中，第二芯片的主动面朝向第一芯片的背面。
本发明的另一实施例提供一种芯片堆叠结构，其包括第一芯片和第二芯片。第二芯片位于第一芯片上。第一芯片包括第一衬底、第一内连线结构、第一焊垫和第一接触导体。第一内连线结构位于第一衬底的第一表面上。第一焊垫位于第一内连线结构上。第一接触导体位于第一衬底中，且暴露于第一衬底的相对于第一表面的第二表面。第二芯片包括第二衬底、第二内连线结构、第二焊垫和第二接触导体。第二内连线结构位于第二衬底上。第二焊垫位于第二内连线结构上。第二接触导体位于第二衬底中，其中第一接触导体直接实体接触于第二焊垫，第一接触导体具有宽度A，第二焊垫具有宽度B，且5≤B/A。
在本发明一实施例中，第一接触导体未覆盖第一衬底的所述第二表面。
在本发明一实施例中，还包括承载板，其位于第一芯片的下方。
在本发明一实施例中，承载板包括承载芯片，且第一芯片的第一焊垫连接至承载芯片的焊垫。
在本发明一实施例中，承载芯片的厚度大于第一芯片的厚度。
在本发明一实施例中，还包括介电层，其位于第一芯片和第二芯片之间。
在本发明一实施例中，第二芯片的主动面朝向第一芯片的背面。
本发明的一实施例提供一种管芯堆叠结构的制造方法，其包括以下步骤。提供第一晶片，其包括第一管芯，且第一管芯包括第一衬底材料层和依序形成于第一衬底材料层上的第一内连线结构和第一焊垫，且第一衬底材料层中具有第一接触导体。提供第二晶片，其包括第二管芯，且第二管芯包括第二衬底材料层和依序形成于第二衬底材料层上的第二内连线结构和第二焊垫，其中第二衬底材料层中具有第二接触导体。移除部分第一衬底材料层，以形成第一衬底，且第一接触导体暴露于第一衬底的远离第一内连线结构的表面。将第二晶片覆盖第一晶片，使得第一接触导体直接实体接触第二焊垫。
在本发明一实施例中，第一接触导体未覆盖第一衬底的远离第一内连线结构的表面。
在本发明一实施例中，在移除部分第一衬底材料层之前，还包括将第一晶片设置于承载板上。
在本发明一实施例中，承载板包括承载晶片，且承载晶片包括第三管芯，其中第一管芯的第一焊垫连接至第三管芯的焊垫。
在本发明一实施例中，第二管芯的主动面面对第一管芯的背面。
在本发明一实施例中，在移除部分第一衬底材料层之后，还包括于第一衬底的远离第一内连线结构的表面上形成介电层，其中介电层暴露第一接触导体。
基于上述，本发明上述实施例所提出的芯片堆叠结构及管芯堆叠结构的制造方法中，由于第一接触导体直接实体接触第二焊垫，故可省略于第一衬底的第二表面上形成用以连接第一接触导体和第二焊垫的焊垫，致使制作工艺得以简化，进而提升芯片堆叠结构的制作工艺良率并降低其制造成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1A至图1E为本发明一实施例的管芯堆叠结构的制造方法的剖视图；
图2为本发明另一实施例的管芯堆叠结构的剖视图；
图3为本发明另一实施例的芯片堆叠结构的剖视图。
符号说明
10：承载板
100、100a、200、200a：晶片
101、101a、201、201a：管芯
101b、201b：芯片
12、102、202：衬底材料层
102a、202a：衬底
14、22、104、114、116、204、214、216：介电层
16、106、206：导线
18、108、208：内连线结构
20、110、210：焊垫
112、212：接触导体
218：重布线层
300：管芯堆叠结构
300a：芯片堆叠结构
S1：第一表面
S2：第二表面
t1、t2：厚度
A、B：宽度
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而，本发明也可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的参考号码表示相同或相似的元件，以下段落将不再一一赘述。
图1A至图1E为依照本发明一实施例的管芯堆叠结构的制造方法的剖视图。图2为依照本发明另一实施例的管芯堆叠结构的剖视图。图3为依照本发明另一实施例的芯片堆叠结构的剖视图。
请参照图1A，提供晶片100。晶片100包括多个管芯，图1A中仅显示其中一管芯101(即第一管芯)。管芯101包括衬底材料层102、内连线结构108、焊垫110、接触导体112和介电层114。衬底材料层102包括半导体基底。半导体基底例如是掺杂硅基底、未掺杂硅基底或绝缘体上覆硅(silicon-on-insulator,SOI)基底。掺杂硅基底可以为P型掺杂、N型掺杂或其组合。在一些实施例中，衬底材料层102之中及/或之上可包括主动元件，例如电荷耦合元件(CCD)、P型金属氧化物半导体晶体管(PMOS)、N型金属氧化物半导体晶体管(NMOS)、互补式金属氧化物半导体(CMOS)晶体管、光电二极管或其组合。衬底材料层102之上也可包括被动元件如电容、电阻、电感、或其组合。在一些实施例中，衬底材料层102还包括内层介电层(inter layer dielectric,ILD)及/或接触窗，但本发明不以此为限。
内连线结构108形成于衬底材料层102上。内连线结构108包括介电层104和多个形成于介电层104中的导线106。介电层104例如是金属层间介电层(inter metaldielectric,IMD)，其材料可以是介电材料。举例来说，介电材料可以是氧化硅、四乙氧基硅氧烷(TEOS)氧化硅、氮化硅、氮氧化硅、无掺杂硅玻璃(USG)、硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、介电常数低于4的低介电常数材料或其组合。低介电常数材料例如是氟掺杂硅玻璃(FSG)、硅倍半氧化物、芳香族碳氢化合物(Aromatic hydrocarbon)、有机硅酸盐玻璃、聚对二甲苯(Parylene)、氟化聚合物(Fluoro-Polymer)、聚芳醚(Poly(arylethers))、多孔聚合物(Porous polymer)或其组合。硅倍半氧化物例如是氢硅倍半氧化物(Hydrogensilsesquioxnane，HSQ)、甲基硅倍半氧化物(Methyl silsesquioxane，MSQ)或混合有机硅烷聚合物(Hybrido-organo siloxane polymer，HOSP)。芳香族碳氢化合物例如是SiLK。有机硅酸盐玻璃例如是碳黑(black diamond，BD)、3MS或4MS。氟化聚合物例如是PFCB、CYTOP、Teflon。聚芳醚例如是PAE-2或FLARE。多孔聚合物例如是XLK、Nanofoam、Awrogel或Coral。介电层104的形成方法例如是原子层沉积法(ALD)、化学气相沉积法(CVD)、旋转涂布法(SOG)或其组合。导线106包括导体层及/或介层窗，其材料可以是导体材料。举例来说，导体材料例如是金属、金属合金、金属氮化物、金属硅化物或其组合。在一些示范实施例中，金属与金属合金例如Cu、Al、Ti、Ta、W、Pt、Cr、Mo或其合金。金属氮化物例如是氮化钛、氮化钨、氮化钽、氮化硅钽(TaSiN)、氮化硅钛(TiSiN)、氮化硅钨(WSiN)或其组合。金属硅化物例如是硅化钨、硅化钛、硅化钴、硅化锆、硅化铂、硅化钼、硅化铜、硅化镍或其组合。在一些实施例中，导线106的形成方法可以是单镶嵌制作工艺(single damascene process)、双镶嵌制作工艺(dual damascene process)或其组合。导线106将主动元件/被动元件电连接至后续将述的接触导体112及/或焊垫。
衬底材料层102中具有接触导体112。接触导体112的材料可以是导体材料。举例来说，导体材料例如是金属、金属合金、金属氮化物、金属硅化物或其组合。在一些示范实施例中，金属与金属合金例如Cu、Al、Ti、Ta、W、Pt、Cr、Mo或其合金。金属氮化物例如是氮化钛、氮化钨、氮化钽、氮化硅钽、氮化硅钛、氮化硅钨或其组合。金属硅化物例如是硅化钨、硅化钛、硅化钴、硅化锆、硅化铂、硅化钼、硅化铜、硅化镍或其组合。在一些实施例中，接触导体112为硅穿孔(through silicon via,TSV)，且根据形成的顺序，其形成方法大略可分为先导孔(via-first)制作工艺、中导孔(via-middle)制作工艺和后导孔(via-last)制作工艺。举例来说，先导孔制作工艺是在晶片进行前段制作工艺(front-end-of-line,FEOL)之前，即将接触导体112形成于衬底材料层102中；后导孔制作工艺是在晶片进行后段制作工艺(back-end-of-the-line,BEOL)之后，才将接触导体112形成于衬底材料层102中；中导孔制作工艺则是在前段制作工艺和后段制作工艺之间(即中段制作工艺(middle-end-of-the-line,MEOL))，将接触导体112形成于衬底材料层102中。在本实施例中，接触导体112是通过中导孔制作工艺形成于衬底材料层102中并通过介电材料(未显示于图中)与衬底材料层102电绝缘，但本发明不以为限，其也可以是通过先导孔制作工艺或是后导孔制作工艺形成于衬底材料层102中。
焊垫110形成于内连线结构108上。焊垫110的材料可以是导体材料。举例来说，导体材料例如是如前针对接触所述的金属、金属合金、金属氮化物、金属硅化物或其组合。焊垫110的形成方法例如是金属图案化制作工艺或金属镶嵌制作工艺。
介电层114形成于内连线结构108上且暴露焊垫110。介电层114的材料可以是如前针对介电层104所述的介电材料。在一些实施例中，介电层114的形成方法可以是先于内连线结构108上形成覆盖焊垫110的介电材料层(未示出)。接着，移除位于焊垫110上的介电材料层，以形成暴露出焊垫110的介电层114。或者，介电层114的形成方法可以是先于内连线结构108上形成介电材料层(未示出)，接着移除欲形成焊垫110处的部分介电材料层，然后形成焊垫110。在一些实施例中，可使用平坦化制作工艺来移除位于焊垫110上的介电材料层。平坦化制作工艺例如是化学机械研磨(chemical mechanical polishing,CMP)制作工艺。
请继续参照图1A，提供承载板10。在一些实施例中，承载板10可以是与晶片100相似的承载晶片。也就是说，承载板10也包括多个管芯，图1A中显示其中一管芯11(即第三管芯)。管芯11包括衬底材料层12、内连线结构18(包括介电层14和导线16)、焊垫20和介电层22，且其相对位置、材料及形成方法分别如同上述管芯101的衬底材料层102、内连线结构108、焊垫110和介电层114，于此不再重复赘述。在一些实施例中，承载板10(承载晶片)可不需在衬底材料层12中形成接触导体，但本发明不以此为限。
请同时参照图1A和图1B，将晶片100覆盖于承载板10上。在一些实施例中，承载板10可以是与晶片100相似的承载晶片，其中管芯101的焊垫110朝向承载板10，并连接至承载板10(即承载晶片)中的管芯11的焊垫20。如此一来，由于承载板10为晶片，故后续制作工艺中不需移除(一般用来承载晶片的载板不具有主动元件及/或内连线结构，故在后续制作工艺中会将其移除)，因此，不仅可简化制作工艺并省去载板的费用，且可额外增加芯片的堆叠密度。在一些实施例中，可使用混合接合(hybrid bond,HB)的方式将管芯101的焊垫110连接至承载板10(即承载晶片)中的管芯11的焊垫20，并将管芯101的介电层114连接至承载板10的介电层22。
请同时参照图1B和图1C，移除部分衬底材料层102以形成衬底102a，其中接触导体112暴露并突出于衬底102a的第二表面S2。在一些实施例中，移除部份衬底材料层102的方法是依序对衬底材料层102的远离内连线结构108的表面(即管芯101的背面)进行薄化制作工艺(thinning process)和蚀刻制作工艺，使得接触导体112暴露并突出于衬底102a的第二表面S2。薄化制作工艺例如是对衬底材料层102的远离内连线结构108的表面进行研磨(grinding)制作工艺。蚀刻制作工艺例如是干蚀刻、湿蚀刻或其组合。在一些实施例中，接触导体112未覆盖衬底102a的远离内连线结构108的表面(即第二表面S2)。另外，衬底102a的厚度小于衬底材料层12、102的厚度。在一些实施例中，衬底102a具有厚度t1，且3μm＜t1＜100μm；而衬底材料层12、102具有厚度t2，且t2约为775μm。也就是说，在承载板10为承载晶片的实施例中，其衬底材料层12的厚度大于衬底102a的厚度(即承载晶片的厚度(管芯11的厚度)大于管芯101a的厚度)，因此，当管芯101a承载于其上时，仍可避免管芯101a的厚度太薄而不易于其上进行后续制作工艺的问题。
请参照图1D，在衬底102a的第二表面S2上形成介电层116，其中介电层116暴露第一接触导体112。介电层116的材料例如是介电材料。介电材料例如是氧化硅、四乙氧基硅氧烷(TEOS)氧化硅无掺杂硅玻璃(USG)等或其组合。在一些实施例中，介电层116的形成方法是先于衬底102a的第二表面S2上形成覆盖接触导体112的介电材料层(未示出)。接着，移除位于接触导体112上的介电材料层，以形成暴露接触导体112的介电层116。介电材料层的形成方法例如是ALD、CVD、SOG或其组合。移除位于接触导体112上的介电材料层的方法可以是平坦化制作工艺，例如CMP。在一些实施例中，介电层116的顶面与接触导体112的顶面为共平面，且介电层116环绕突出于第二表面S2上的接触导体112。
请参照图1E，提供晶片200。晶片200包括多个管芯，图1E中显示其中一管芯201(即第二管芯)。管芯201包括衬底材料层202、内连线结构208(包括介电层204和导线206)、焊垫210、接触导体212和介电层214。在一些实施例中，晶片200与晶片100相似，故其管芯201中的衬底材料层202、内连线结构208、焊垫210、接触导体212和介电层214的相对位置、材料及其形成方法大致相似于管芯101的衬底材料层102、内连线结构108、焊垫110、接触导体112和介电层114，于此不在重复赘述。
接着，将晶片200覆盖晶片100a，使得管芯201对接管芯101a，且管芯101a的接触导体112直接实体接触管芯201的焊垫210。如此一来，可省略于介电层116上形成另一用以连接接触导体112和焊垫210的焊垫，致使制作工艺得以简化，进而提升后续形成芯片堆叠结构的制作工艺良率并降低其制造成本。在一些实施例中，可使用混合接合的方式将管芯101a的接触导体112直接实体接触管芯201的焊垫210。在一些实施例中，接触导体112具有宽度A；焊垫210具有宽度B，且5≤B/A，尤其5≤B/A≤10甚至B/A>10。如此一来，即便触导体112和焊垫210发生对准偏差，接触导体112仍可良好地电连接于焊垫210，且不会影响到其他相邻的接触导体112及/或焊垫210(例如太靠近邻近的接触导体112及/或焊垫210，会受到电迁移(electron migration,EM)效应的影响，而导致有短路的风险)。在本实施例中，管芯201的主动面朝向管芯101a的背面，亦即，本实施例是采用晶面对晶背(back-to-front)的堆叠方式进行说明，但本发明不以此为限。在一些实施例中，也可以是采用晶面对晶面(front-to-front)或是晶背对晶背(back-to-back)的堆叠方式。另外，请参照图1A及图1E，在本实施例中，是以在承载板10上堆叠两个晶片(晶片100、200)为例进行说明，但本发明不以此为限，其可再对晶片200进行如图1C至图1E的制作工艺，以形成晶片200a，并于其上堆叠一个或是多个晶片。
请同时参照图1E及图2，在本实施例中，是以在承载板10上堆叠两个晶片为例进行说明，因此，管芯201为管芯堆叠结构的最上层管芯，然而本发明不以此为限。对管芯201进行如上述图1C及图1D的制作工艺，以形成管芯201a，其接触导体212暴露并突出于衬底202a的远离内连线结构208的表面，且介电层216形成于衬底102a的远离内连线结构208的表面并暴露接触导体212。在一实施例中，介电层216的材料及其形成方法大致与介电层116相似，于此不再重复赘述。接着，于介电层216上形成重布线层(redistribution layer,RDL)218，以定义管芯堆叠结构300的最上层管芯的焊垫。重布线层218电连接至相对应的接触导体212。重布线层218的材料可以是上面针对接触导体所述的导体材料。举例来说，导体材料例如是上述金属、金属合金、金属氮化物、金属硅化物或其组合。
请参照图3，对管芯堆叠结构300进行单体化制作工艺(singulation)，以将管芯堆叠结构300切割成多个相互分离的芯片堆叠结构300a。以下，将通过图3来说明本实施例的芯片堆叠结构300a。此外，本实施例的芯片堆叠结构300a的制造方法虽然是以上述制造方法为例进行说明，但本发明的芯片堆叠结构300a的制造方法并不以此为限。
请参照图3，芯片堆叠结构300a包括芯片101b(即第一芯片)和芯片201b(即第二芯片)。芯片101b与芯片201b分别对应管芯101a和管芯201a(如图2所示)。芯片201b位于芯片101b上。芯片101b包括衬底102a(第一衬底)、内连线结构108(第一内连线结构)、焊垫110(第一焊垫)、接触导体112(第一接触导体)和介电层114。内连线结构108位于衬底102a的第一表面S1上。焊垫110位于内连线结构108上。接触导体112位于衬底102a中，且暴露于衬底102a的相对于第一表面S1的第二表面S2。芯片201b包括衬底202a(第二衬底)、内连线结构208(第二内连线结构)、焊垫210(第二焊垫)、接触导体212(第二接触导体)和介电层214。内连线结构208位于衬底202a上。焊垫210位于内连线结构208上，其中芯片101b的接触导体112直接实体接触芯片201b的焊垫210。接触导体112具有宽度A，焊垫210具有宽度B，且5≤B/A例如5≤B/A≤10甚至B/A>10。另外，接触导体112未覆盖衬底102a的第二表面S2。在一些实施例中，芯片堆叠结构300a还包括承载板10，其位于芯片101b的下方。在一些实施例中，承载板10为承载芯片。芯片101b的焊垫110连接至承载板10(即承载芯片)的焊垫20，其中承载芯片的厚度大于芯片101b的厚度。在一些实施例中，芯片堆叠结构300a还包括介电层116，其位于芯片101b和第二芯片201b之间。在一些实施例中，芯片201b的主动面朝向芯片101b的背面。
综上所述，上述实施例所述的芯片堆叠结构及其制造方法中，由于第一芯片的第一接触导体直接实体接触第二芯片的第二焊垫，故可省略于第一衬底的第二表面上形成用以连接第一接触导体和第二焊垫的焊垫，致使制作工艺得以简化，进而提升芯片堆叠结构的制作工艺良率并降低其制造成本。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (10)

1.一种芯片堆叠结构，其特征在于，包括：
第一芯片，包括：
第一衬底；
第一内连线结构，位于所述第一衬底的第一表面上；
第一焊垫，位于所述第一内连线结构上；以及
第一接触导体，位于所述第一衬底中，且暴露于所述第一衬底的相对于所述第一表面的第二表面；
第二芯片，位于所述第一芯片上，所述第二芯片包括：
第二衬底；
第二内连线结构，位于所述第二衬底上；
第二焊垫，位于所述第二内连线结构上；以及
第二接触导体，位于所述第二衬底中；
第一介电层，位于所述第一芯片与所述第二芯片之间且包括环绕所述第一接触导体的部分，其中所述第一介电层的所述部分直接实体接触所述第二焊垫，且所述第一介电层的上表面与所述第一接触导体的上表面为共平面；以及
重布线层，位于所述第二接触导体上并电连接至所述第二接触导体，
其中所述第一接触导体直接实体接触所述第二焊垫，所述第一接触导体具有宽度A，所述第二焊垫具有宽度B，且5≤B/A。
2.根据权利要求1所述的芯片堆叠结构，还包括：
承载板，位于所述第一芯片的下方。
3.根据权利要求2所述的芯片堆叠结构，其中所述承载板包括承载芯片，且所述第一芯片的所述第一焊垫连接至所述承载芯片的焊垫。
4.根据权利要求3所述的芯片堆叠结构，其中所述承载芯片的厚度大于所述第一芯片的厚度。
5.根据权利要求1所述的芯片堆叠结构，其中所述第二芯片的主动面朝向所述第一芯片的背面。
6.根据权利要求1所述的芯片堆叠结构，其中所述第一接触导体为硅穿孔。
7.根据权利要求1所述的芯片堆叠结构，还包括：
第二介电层，位于所述重布线层与所述第二接触导体之间。
8.根据权利要求7所述的芯片堆叠结构，其中所述第二接触导体暴露于所述第二介电层。
9.根据权利要求1所述的芯片堆叠结构，其中所述第一接触导体并未直接实体接触所述第一焊垫。
10.根据权利要求1所述的芯片堆叠结构，其中所述第二接触导体并未直接实体接触所述第二焊垫。
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