WO2012013162A1 - 一种硅通孔互连结构及其制造方法 - Google Patents

一种硅通孔互连结构及其制造方法 Download PDF

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Publication number
WO2012013162A1
WO2012013162A1 PCT/CN2011/077824 CN2011077824W WO2012013162A1 WO 2012013162 A1 WO2012013162 A1 WO 2012013162A1 CN 2011077824 W CN2011077824 W CN 2011077824W WO 2012013162 A1 WO2012013162 A1 WO 2012013162A1
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Prior art keywords
semiconductor substrate
layer
silicon via
via conductor
insulating layer
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PCT/CN2011/077824
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English (en)
French (fr)
Inventor
尹海洲
骆志炯
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昆山智拓达电子科技有限公司
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Priority to CN201180037684.7A priority Critical patent/CN104011848A/zh
Publication of WO2012013162A1 publication Critical patent/WO2012013162A1/zh

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    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates to semiconductor packaging technology, and more particularly to a through silicon via interconnect structure and a method of fabricating the same. Background technique
  • TSV packaging technology is the latest technology for interconnecting chips and chips by making vertical conduction between the chip and the chip. Unlike previous IC package bonding and bump overlay technology, TSV package technology enables the highest density of chips stacked in three dimensions, minimizes form factor, and greatly improves chip speed and low power consumption.
  • the TSV package generally includes the steps of: forming a via hole from one surface of the semiconductor substrate, and depositing an insulating layer in the via hole; filling the via hole with a metal (eg, copper, tungsten, etc.) to form a through silicon via; The semiconductor substrate is thinned until a through silicon via is exposed from the other surface of the semiconductor substrate; finally, the plurality of thinned semiconductor substrates are bonded.
  • a metal eg, copper, tungsten, etc.
  • the two or two More than one semiconductor substrate 100 is connected by a through-silicon via conductor 101, wherein the material of the through-silicon via conductor 101 is copper.
  • An insulating layer 102 is present between the semiconductor substrate 100 and the through-silicon via conductor 101 for isolating the semiconductor substrate 100 and the through-silicon via conductor 101 from being short-circuited.
  • a fill material 103 is present between the interconnected two semiconductor substrates 100.
  • the fill material is typically an insulator that can help bond the adjacent two semiconductor substrates 100.
  • the deformed material effectively reduces the stress effect of the through-silicon via conductor on the semiconductor substrate during thermal expansion.
  • a method of fabricating a through silicon via interconnect comprising the steps of:
  • the cross-sectional shape of the hole may be various shapes such as a circle, a square, a strip, a polygon, and the like;
  • Another aspect of the present invention also provides a through silicon via interconnect structure including a semiconductor substrate, a through silicon via conductor extending through the semiconductor substrate, and the semiconductor lining a first insulating layer between the bottom and the through-silicon via conductor, comprising: [0010] a buffer layer between the through-silicon via conductor and the first insulating layer;
  • At least one contact pad, at least one end of the through silicon via is connected to the contact pad, and the contact pad is fixed on the semiconductor substrate.
  • the substrate is interconnected by bonding between the through-silicon via conductor and the contact pad or between the two contact pads.
  • the buffer layer is a void, a low-k dielectric material, a porous material or a deformable material.
  • the buffer layer has a lower Young's modulus than single crystal silicon, that is, softer than single crystal silicon.
  • the present invention has the following advantages: effectively reducing the through-silicon via conductor and the semiconductor lining by forming a cavity between the through-silicon via conductor and the semiconductor substrate or filling the low-k dielectric material
  • the deformation of the through-silicon via conductor is caused, the deformation of the through-silicon via conductor is effectively reduced, and the stress generated by the deformation on the semiconductor substrate is effectively reduced.
  • FIG. 1 is a schematic cross-sectional view showing a through-silicon via interconnection structure in the prior art
  • FIG. 2 is a flow chart of a method of fabricating a through silicon via interconnect structure in accordance with the present invention
  • FIG. 3 through 18 are cross-sectional views showing various stages of fabricating a semiconductor structure in accordance with the flow shown in Fig. 2 in accordance with a preferred embodiment of the present invention.
  • first and second features are formed in direct contact
  • additional features formed between the first and second features.
  • first and second features may not be in direct contact.
  • components illustrated in the drawings are not necessarily drawn to scale. The invention omits the well-known components and processing techniques and processes The description is made to avoid unnecessarily limiting the invention.
  • FIG. 2 is a flow chart of a method of fabricating a through silicon via interconnect structure in accordance with the present invention.
  • the method shown in Fig. 2 will be specifically described with reference to Figs. 3 to 18.
  • the through-silicon via completed before the Back End of Line (BEOL) step is generally referred to as the first via
  • the through-silicon via performed after the BEOL step is generally referred to as the through pass. Holes, hereinafter, only the subsequent through holes are taken as an example to explain the manufacturing method of the through silicon via interconnection structure provided by the present invention.
  • step S101 is performed to provide a semiconductor substrate 200 having a first surface and a second surface corresponding to the first surface.
  • the semiconductor substrate 200 is a bulk silicon substrate on which an active region has been formed, wherein the semiconductor substrate 200 has a first surface and a second surface corresponding to the first surface, the active region being located below the first surface of the semiconductor substrate 100 (shown by the position of the dashed line in the figure), which may include various NMOS devices, PMOS devices And/or other integrated circuits.
  • the semiconductor substrate 200 may also be an SOI (Silicon On Insulator) substrate or a substrate containing a III-V semiconductor material.
  • the semiconductor substrate 200 has a thickness ranging from 400 ⁇ m to 800 ⁇ m.
  • a dielectric layer 201 is generally disposed on the first surface of the semiconductor substrate 200 for protecting an active region in the semiconductor substrate 200.
  • the material of the dielectric layer 201 includes silicon dioxide and silicon nitride. One or any combination thereof, and other suitable dielectric materials.
  • step S102 is performed to form a recessed hole 202 from the first surface of the semiconductor substrate 200, and a first insulating layer 203 is formed on the sidewall and the bottom surface of the recessed hole 202, and A sacrificial layer 204 is formed on an insulating layer 203.
  • a recessed hole 202 is formed from the first surface of the semiconductor substrate 200 by using, for example, deep plasma etching, KOH solution wet etching, or laser processing.
  • the cross section of the recess 202 (a cross section parallel to the first surface of the semiconductor substrate 200) is generally circular, and the recess 202 has a diameter ranging from 2 ⁇ ⁇ -10 ⁇ ⁇ , depth range from 20 ⁇ m to 100 ⁇ m.
  • the cross section of the dimple 202 may also be other shapes such as a square, a strip, a polygon, or the like as needed.
  • a first insulating layer 203 and a sacrificial layer 204 are sequentially deposited to cover the sidewalls and the bottom surface of the semiconductor substrate 200 and the recess 202, please refer to FIG. 5.
  • the material of the first insulating layer 203 is preferably silicon nitride and has a thickness ranging from 10 nm to 150 nm.
  • the sacrificial layer 204 is to be removed in a subsequent process, so the material of the sacrificial layer 204 is preferably easy to etch, and with the first insulating layer 203 and the through-silicon via conductor (will be in the subsequent process) Different materials are generated to facilitate removal by selective etching.
  • the sacrificial layer 204 has a thickness ranging from 0.2 ⁇ m to 1 ⁇ m.
  • step S103 a conductive material is filled in the recess 202 to form a through-silicon via conductor 205, and a first contact pad 207 electrically connected to the through-silicon via conductor 205 is formed.
  • a through-silicon via conductor is first formed, as shown in FIG. 6, a seed layer (not shown) is formed on the surface of the sacrificial layer 204, and then filled in the recessed hole 202 by, for example, electroplating.
  • Conductive material In this embodiment, the conductive material is copper. In other embodiments, the conductive material may further comprise one of nickel, tungsten, or any combination thereof.
  • the conductive material is planarized until the upper surface of the conductive material is flush with the upper surface of the sacrificial layer 204 (in this document, the term "flush" means between The height difference is within the range allowed by the process error to form the through silicon via conductor 205.
  • the conductive material, sacrificial layer 204, and first insulating layer 203 are planarized until the dielectric layer 201 is exposed (in other embodiments, if the semiconductor liner The dielectric layer is not present on the first surface of the bottom 200, and the conductive material and the sacrificial layer 204 are planarized until the first insulating layer 203 is exposed, and the first insulating layer 203 is left for isolating the semiconductor substrate 200 and protected The source region), at this time, the sacrificial layer 204 exists only in the recess 202 (please refer to FIG. 6) and is located between the through-silicon via conductor 205 and the first insulating layer 203.
  • the second insulating layer 206 is formed, wherein the material of the second insulating layer 206 is preferably one of silicon nitride, oxide, or any combination thereof, and has a thickness ranging from 1 ⁇ m to 10 ⁇ m.
  • the second insulating layer 206 is etched to form a first opening 300, wherein the first opening 300 exposes the through-silicon via conductor 205, the sacrificial layer 204, and a portion of the periphery of the sacrificial layer 204.
  • a cross section of the first opening 300 (a cross section parallel to the first surface of the semiconductor substrate 200) is circular and has a diameter ranging from 8 ⁇ m to 15 ⁇ m.
  • the cross section of the first opening 300 may also be other shapes such as a square, a strip, a polygon, or the like as needed.
  • a seed layer (not shown) is preferably formed in the first opening 300, and then the conductive material is filled in the first opening 300 by, for example, electroplating, and is planarized.
  • the upper surface of the conductive material is flush with the upper surface of the second insulating layer 206 to form a first contact pad 207 electrically connected to the upper end of the through-silicon via conductor 205, wherein, in this embodiment,
  • the material of the first contact pad 207 is the same as that of the through-silicon via conductor 205, and is metal copper. In other embodiments, the material of the first contact pad 207 may also be the same as the through-silicon via conductor 205. Metals with different materials, such as aluminum.
  • the first contact pad 207 is formed such that the through-silicon via conductor 205 can be fixed to the semiconductor substrate 200.
  • step S104 the semiconductor substrate 200 is thinned from the second surface of the semiconductor substrate 200 until the through-silicon via conductor 205 is exposed.
  • the semiconductor substrate 200 is fixed on a carrier 208, wherein the carrier 208 may be a silicon wafer, or may be glass or plastic.
  • a first contact pad 207 on the first surface of the semiconductor substrate 200 is attached to the carrier 208 to expose the second surface of the semiconductor substrate 200. Then, the second surface of the semiconductor substrate 200 is ground or planarized until the through-silicon via conductor 205 is exposed.
  • the semiconductor substrate 200, the first insulating layer 203, and the sacrificial layer 204 may be further etched by selective etching without etching the
  • the through-silicon via conductors 205 are such that a portion of the through-silicon via conductors 205 protrude from the semiconductor substrate 200, the first insulating layer 203, and the sacrificial layer 204, wherein the selective etching has a depth ranging from 50 nm to 500 nm.
  • the semiconductor substrate 200 continues to etch without etching the first insulating layer 203, the sacrificial layer 204, and the through-silicon via conductor 205 such that a portion of the through-silicon via conductor 205, sacrificial layer 204, and The first insulating layer 203 protrudes from the semiconductor substrate 200.
  • an insulating material is deposited to cover the second surface of the semiconductor substrate 200, the through-silicon via conductor 205, the sacrificial layer 204, and the first insulating layer 203, and the insulating material is planarized until exposed.
  • the through-silicon via conductor 205 is then removed by, for example, photolithography to remove the insulating material on the underside of the sacrificial layer 204; or in the second case described above, the through-silicon via conductor 205 is at the lower end of the sacrificial layer 204 Flat, when the insulating material is planarized until the through-silicon via conductor 205 is exposed, the sacrificial layer 204 is also exposed, and the insulating material on the underside of the sacrificial layer 204 is removed without photolithography, thereby forming the semiconductor lining
  • the second surface of the bottom 200 forms a third insulating layer 209.
  • the material of the third insulating layer 209 is the same as the material of the first insulating layer 203, and may be different from the material of the first insulating layer 203.
  • the third insulating layer 209 can effectively isolate the adjacent two semiconductor substrates to prevent the second of the semiconductor substrate. The surface is in contact with the first contact pad over the other semiconductor substrate, thereby causing a short circuit.
  • step S105 is performed to remove the sacrificial layer 204, and a void layer 211 is formed between the through-silicon via conductor 205 and the first insulating layer 203.
  • the through-silicon via can be selectively removed by, for example, wet etching.
  • step S106 the above steps are performed to form the semiconductor substrate 200 after stacking and bonding.
  • the semiconductor substrate 200 and the carrier are first used.
  • the 208 is separated, and then the plurality of thinned semiconductor substrates 200 are precisely aligned, and the lower end of the through-silicon via conductor 205 of the semiconductor substrate is bonded to another semiconductor lining by, for example, copper-copper bonding.
  • the first contact pads 207 above the first surface of the bottom are bonded, thereby connecting a plurality of the semiconductor substrates 200 to form a through-silicon via interconnection structure (FIG. 13 only shows a schematic diagram of interconnection of two semiconductor substrates).
  • the dashed line indicates the interconnection surface between the two semiconductor substrates, wherein the bonding is a technique well known to those skilled in the art and will not be described herein.
  • the lower end of the through-silicon via conductor 205 may be further formed.
  • the second contact pad 212 is connected. Referring to FIG. 14 to FIG. 17, the forming step is as follows: depositing an insulating material on the second surface of the thinned semiconductor substrate 200 to form a fourth insulating layer 210, wherein the The material of the four insulating layers 210 is preferably one of silicon nitride, silicon oxide, or any combination thereof, and has a thickness ranging from 1.5 ⁇ m to 10 ⁇ m.
  • a seed layer is preferably formed on the lower side of the third insulating layer 209 in the second opening 301 ( Not shown), and filling the second opening 301 with a conductive material by, for example, electroplating, by process control, selecting a condition that is not easy to fill the hole, so that the void layer 21 1 can be substantially not filled, and most of the maintenance is a gap, and then a flattening operation, the upper surface of the conductive material is flush with the upper surface of the fourth insulating layer 210, and a second contact pad 212 electrically connected to the lower end of the through-silicon via conductor 205 is formed.
  • the second contact The material of 212 may be the same as the material of the first contact pad 207, or may be different from the material of the first contact pad 207; finally, as shown in FIG. 17, the plurality of semiconductor substrates 200 are stacked Connection (Fig. 17 only shows a schematic diagram of two semiconductor substrate interconnections, and a broken line indicates an interconnection surface between two semiconductor substrates), wherein two adjacent semiconductor substrates 200, half The second contact pad 212 under the second surface of the conductor substrate 200 is bonded to the first contact pad 207 over the first surface of the other semiconductor substrate 200.
  • the formation of the second contact pad 212 not only further fixes the through-silicon via conductor 205 and the semiconductor substrate 200, but also effectively increases the bonding area between the through-silicon via conductors of the two semiconductor substrates. Thus, the robustness of the through-silicon via interconnect structure is ensured.
  • the void layer 211 may also be filled in a low manner by, for example, deposition and planarization.
  • the K dielectric material 213 may either absorb the deformed material 213 as shown in FIG.
  • the low-k dielectric material 213 comprises one of fluorine-doped silicon oxide, carbon-doped silicon oxide, porous silicon oxide, porous carbon-doped silicon oxide, or any combination thereof.
  • the material 213 which can absorb deformation includes porous silicon, porous silicon oxide, one of polymers, or any combination thereof.
  • the void layer 211 or the low-k dielectric material layer 213 filled in the void layer 211 or the material layer 213 which can absorb the deformation may be referred to as a buffer layer 211, 213.
  • a void layer is formed between the semiconductor substrate and the through-silicon via conductor or is filled with a low-k dielectric material, so that the semiconductor substrate and the a parasitic capacitance between the through-silicon via conductors; and a void layer 211 formed between the semiconductor substrate and the through-silicon via conductor or filled with a material capable of absorbing deformation so that the temperature can be changed to cause the through-silicon
  • the hole conductor is deformed, the deformation effect on the semiconductor substrate by the deformation is effectively reduced by absorbing the deformation of the through-silicon via conductor.
  • the step of forming the sacrificial layer 204 may be replaced by forming the buffer layer 204 that is not subsequently removed, and the material of the buffer layer 204 may be a single layer or a multi-layer structure. Some of these materials employ the above-described low-k dielectric materials, deformable materials, or a combination thereof. This may omit the subsequent step of removing the sacrificial layer to form the void layer and filling the low-k dielectric material or deforming the material.
  • the present invention also provides a through-silicon via interconnect structure.
  • a through-silicon via conductor 205 of the bulk substrate 200, and the semiconductor via 200 and the through-silicon via conductor are located.
  • the material of the body 205 is copper.
  • the material of the through-silicon via conductor 205 may also be one of nickel and tungsten or any combination thereof; the through-silicon via conductor 205 and the first There is a buffer layer between the insulating layer 203, for example, a void layer 211; a first contact pad 207 is present, and one end of the through-silicon via conductor 205 is electrically connected to the first contact pad 207 and passes through the first contact pad 207.
  • the semiconductor substrate 200 is fixed, wherein the material of the first contact pad 207 is preferably the same as the material of the through-silicon via conductor 205, and may be different from the material of the through-silicon via conductor 205.
  • the two or more semiconductor substrates are interconnected by bonding of the through-silicon via conductor 205 and the first contact pad 207, that is, two semiconductor linings interconnected as in FIG.
  • the lower end of one of the semiconductor substrate 200 through-silicon via conductors 205 is bonded to the first contact pad 207 over the first surface of the other semiconductor substrate 200 (the dashed line indicates between the two semiconductor substrates 200) The interconnect surface), thereby forming a through silicon via interconnect structure.
  • the through silicon via interconnect structure provided by the present invention further includes a second contact pad 212, and the other end of the through silicon via conductor 205 is electrically connected to the second contact pad 212. Connecting, and further fixing with the semiconductor substrate 200 through the second contact pad 212.
  • the second contact pad 212 can also effectively increase the bonding area between the through-silicon via conductors of the two interconnected semiconductor substrates, thereby ensuring the robustness of the through-silicon via interconnect structure.
  • the material of the second contact pad 212 may be the same as or different from the material of the first contact pad 207.
  • the buffer layer between the through-silicon via conductor 205 and the first insulating layer 203 may also be a low-k dielectric material layer 213, which may absorb deformation.
  • the material layer 213 that can absorb deformation includes one of porous silicon, porous silicon oxide, polymer, or any combination thereof.
  • the through silicon via interconnect structure provided by the present invention is layered with a conventional through silicon via interconnect structure, for example, a void layer or a low-k dielectric material layer, thereby effectively reducing the semiconductor substrate and Parasitic capacitance between the through-silicon via conductors; in addition, due to the semiconductor substrate A gap layer is formed between the through-silicon via conductors or filled with a material capable of absorbing deformation, so that the deformation of the through-silicon via conductor can be effectively reduced when the temperature changes to cause deformation of the through-silicon via conductor, thereby effectively reducing the deformation and deformation A stress effect on the semiconductor substrate.
  • a conventional through silicon via interconnect structure for example, a void layer or a low-k dielectric material layer

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Abstract

提供一种硅通孔互联结构的制造方法，该方法包括以下步骤：提供半导体衬底（200）；从所述半导体衬底（200）的第一表面形成凹孔（202），并在所述凹孔（202）的侧壁和底面上形成第一绝缘层（203），以及在所述第一绝缘层（203）上形成牺牲层（204）；在所述凹孔（202）内填充硅通孔导体（205），以及在所述半导体衬底（200）的第一表面上形成与该硅通孔导体（205）电性连接的第一接触垫（207）；从所述半导体衬底（200）的第二表面对该半导体衬底（200）进行减薄，直至暴露出所述硅通孔导体（205）；去除所述牺牲层（204），在所述硅通孔导体（205）和第一绝缘层（203）之间形成空隙层（211）；将多个所述半导体衬底（200）堆叠后进行键合。相应地，提供一种硅通孔互连结构。该制造方法和互连结构可以有效地降低硅通孔与半导体衬底（200）之间的寄生电容，以及有效地减小硅通孔导体（205）在热膨胀中对所述半导体衬底（200）产生的应力作用。

Description

一种硅通孔互连结构及其制造方法 技术领域
[0001]本发明涉及半导体封装技术，尤其涉及一种硅通孔互连结构及 其制造方法。 背景技术
[0002]硅通孔 (Through-Silicon-Via， TSV)封装技术是通过在芯片和芯 片之间制作垂直导通， 实现芯片和芯片之间互连的最新技术。 与以 往的 IC封装键合以及使用凸点的叠加技术不同， TSV封装技术能够 使芯片在三维方向堆叠的密度最大， 外形尺寸最小， 并且大大改善 了芯片速度和低功耗的性能。 中， TSV 封装一般包括如下步骤： 从半导体衬底的一个表面形成通 孔， 并在该通孔内沉积绝缘层； 使用金属 (例如铜、 钨等)填充所述通 孔形成硅通孔； 对所述半导体衬底进行减薄， 直至从所述半导体衬 底的另一个表面暴露出硅通孔； 最后将多个减薄后的半导体衬底相 键合。基于上述步骤所形成的硅通孔互连结构请参考图 1，如图所示， 两个半导体衬底为例， 虚线表示两个半导体衬底之间的互连面）， 该 两个或两个以上的半导体衬底 100通过硅通孔导体 101相连接， 其 中， 硅通孔导体 101 的材料为铜。 在所述半导体衬底 100和硅通孔 导体 101之间存在绝缘层 102，用于隔离所述半导体衬底 100和硅通 孔导体 101， 以防止其二者发生短接。 此外， 在互连的两个半导体衬 底 100之间还存在填充材料 103， 填充材料一般为绝缘体， 可以帮助 键合相邻的两个半导体衬底 100。
[0004]在 G. Katti等人于 2009年 12月在美国华盛顿 D.C.的国际电子 器件会议 ( International Electron Device Meeting )上发表的论文 "3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding" 中， 作者指出随着硅通孔封装密度的增加， 硅通孔导体与 硅衬底之间的寄生电容会导致严重的 RC延迟；另外对于基于铜填充 的硅通孔封装技术的可靠性的研究发现硅通孔互连结构中用于将芯 片互连的铜的热膨胀系数与硅的热膨胀系数不同， 在芯片制备工艺 的高温步骤中， 由于热膨胀系数不同， 从而导致硅通孔中的铜会往 外膨胀， 对环绕在铜周围的区域产生应力， 严重时会造成芯片的断
[0005]因此，亟需提出一种可以解决上述问题的硅通孔互连结构及其 制造方法。 发明内容
一种硅通孔互连结构及其制造方法，通过
Figure imgf000004_0001
形变的材料， 有效地减小了硅通孔导体在热膨胀中对半导体衬底的 应力作用。
[0007]#居本发明的一个方面， 提供一种硅通孔互连的制造方法， 该 方法包括以下步骤：
a)提供半导体衬底， 该半导体衬底具有第一表面以及与该第一表面 相对应的第二表面；
b)从所述半导体衬底的第一表面形成凹孔， 并在所述凹孔的侧壁和 底面上形成第一绝缘层， 以及在所述第一绝缘层上形成牺牲层， 其 中该凹孔的横截面形状可以是圆形、 方形、 条形、 多边形等各种形 状；
c)在所述凹孔内填充导电材料形成硅通孔导体， 以及在所述半导体 衬底的第一表面上形成与该硅通孔导体电性连接的第一接触垫； d)从所述半导体衬底的第二表面对该半导体衬底进行减薄， 直至暴 露所述硅通孔导体和牺牲层； e)去除所述牺牲层， 在所述硅通孔导体和第一绝缘层之间形成空隙 层；
f) 将多个所述半导体衬底堆叠后进行键合。
[0008]根据本发明的另一个方面， 还提供一种硅通孔互连结构的制造 方法， 该方法包括以下步骤：
a)提供半导体衬底， 该半导体衬底具有第一表面以及与该第一表面 相对应的第二表面；
b)从所述半导体衬底的第一表面形成凹孔， 并在所述凹孔的侧壁和 底面上形成第一绝缘层， 以及在所述第一绝缘层上形成緩冲层； c)在所述凹孔内填充导电材料形成硅通孔导体， 以及在所述半导体 衬底的第一表面上形成与该硅通孔导体电性连接的第一接触垫； d)从所述半导体衬底的第二表面对该半导体衬底进行减薄， 直至暴 露所述硅通孔导体和緩冲层；
f)将多个所述半导体衬底堆叠后进行键合。
[0009]本发明另一方面还提出了一种硅通孔互连结构，该硅通孔互连 结构包括半导体衬底、 贯穿所述半导体衬底的硅通孔导体、 以及位 于所述半导体衬底和硅通孔导体之间的第一绝缘层， 其中包括： [0010]位于所述硅通孔导体与所述第一绝缘层之间的緩冲层；
[0011 ]至少一个接触垫， 所述硅通孔的至少一端与该接触垫相连接， 并且所述接触垫固定于所述半导体衬底上。 衬底通过所述硅通孔导体与所述接触垫之间或者两个接触垫之间的 键合形成互连。
[0013]其中所述緩冲层为空隙、 低 K介电材料、 多孔材料或者可形变 材料。 緩冲层具有比单晶硅低的杨氏模量， 也就是比单晶硅软。
[0014]与现有技术相比， 本发明具有以下优点： 通过在硅通孔导体与 半导体衬底之间形成空腔或填充低 K介电材料， 有效地降低了硅通 孔导体与半导体衬底之间的寄生电容， 以及通过在硅通孔导体与半 导体衬底之间形成空腔或填充可以吸收形变的材料， 在温度发生变 化导致硅通孔导体形变的时候， 通过吸收硅通孔导体的形变， 有效 地减小形变对所述半导体衬底产生的应力作用。 附图说明
[0015]通过阅读参照以下附图所作的对非限制性实施例所作的详细描 述， 本发明的其它特征、 目的和优点将会变得更明显：
图 1为现有技术中硅通孔互连结构的剖面示意图；
图 2为根据本发明的硅通孔互连结构制造方法的流程图；
图 3至图 18为根据本发明的一个优选实施例按照图 2所示流程制造 半导体结构的各个阶段的剖面示意图。
[0016]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0017]下面详细描述本发明的实施例，所述实施例的示例在附图中示 出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有 相同或类似功能的元件。 下面通过参考附图描述的实施例是示例性 的， 仅用于解释本发明， 而不能解释为对本发明的限制。
[0018]下文的公开提供了许多不同的实施例或例子用来实现本发明 的不同结构。 为了简化本发明的公开， 下文中对特定例子的部件和 设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发 明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种 重复是为了简化和清楚的目的， 其本身不指示所讨论各种实施例和 / 或设置之间的关系。 此外， 本发明提供了的各种特定的工艺和材料 的例子， 但是本领域普通技术人员可以意识到其他工艺的可应用于 性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上"的结构可以包括第一和第二特征形成为直接接触的实施例，也可 以包括另外的特征形成在第一和第二特征之间的实施例， 这样第一 和第二特征可能不是直接接触。 应当注意， 在附图中所图示的部件 不一定按比例绘制。 本发明省略了对公知组件和处理技术及工艺的 描述以避免不必要地限制本发明。
[0019]本发明提供了一种硅通孔互连结构的制造方法， 请参考图 2， 图 2 为根据本发明的硅通孔互连结构制造方法的流程图。 下面， 将 结合图 3至图 18对图 2所示的方法进行具体说明。 需要说明的是， 阶段， 在后段工艺（Back End of Line， BEOL)步骤之前完成的硅通孔 通常被称作先通孔， 在 BEOL 步骤之后所执行的硅通孔通常被称作 后通孔， 下文中仅以后通孔为例对本发明提供的硅通孔互连结构制 造方法进行说明。
[0020]首先， 执行步骤 S101， 提供半导体衬底 200， 该半导体衬底 200具有第一表面以及与该第一表面相对应的第二表面。
[0021]具体地， 如图 3所示， 在本实施例中， 所述半导体衬底 200为 已经形成有源区的体硅衬底， 其中， 所述半导体衬底 200 具有第一 表面以及和该第一表面相对应的第二表面， 所述有源区位于所述半 导体衬底 100的第一表面下方（如图中虚线标志的位置所示），其可以 包括各种 NMOS器件、 PMOS器件、 和 /或其他集成电路。 在其它实 施例中， 所述半导体衬底 200还可以是 SOI (绝缘体上硅 )衬底或含 有 III-V半导体材料的衬底。 所述半导体衬底 200的厚度范围为 400 μ ιη-800 μ ιη。 此外， 在所述半导体衬底 200的第一表面上通常存在 介质层 201， 用于保护所述半导体衬底 200中的有源区， 所述介质层 201的材料包括二氧化硅、 氮化硅中的一种或其任意组合， 以及其他 合适的介电材料。
[0022]接着， 执行步骤 S102， 从所述半导体衬底 200的第一表面形 成凹孔 202，并在所述凹孔 202的侧壁和底面上形成第一绝缘层 203， 以及在所述第一绝缘层 203上形成牺牲层 204。
[0023]具体地， 如图 4所示， 利用例如深层等离子体刻蚀、 KOH溶 液湿法刻蚀或者激光加工等方式， 从所述半导体衬底 200 的第一表 面形成凹孔 202， 其中， 所述凹孔 202的横截面（与所述半导体衬底 200第一表面平行的截面）通常为圆形，所述凹孔 202的直径范围为 2 μ ιη-10 μ ιη, 深度范围为 20 μ m-100 μ m。 根据需要所述凹坑 202的 横截面也可以是方形、 条形、 多边形等其他形状。
[0024]形成凹孔 202之后，依次沉积第一绝缘层 203以及牺牲层 204， 覆盖所述半导体衬底 200以及所述凹孔 202的侧壁和底面， 请参考 图 5。 其中， 所述第一绝缘层 203的材料优选为氮化硅， 其厚度范围 为 10nm-150nm。 所述牺牲层 204由于在后续工艺中将会被去除， 所 以， 所述牺牲层 204 的材料优选为易于刻蚀、 且与所述第一绝缘层 203以及硅通孔导体 (将在后续工艺中生成)不同的材料， 以便于通过 选择性刻蚀进行去除。 因此， 可以采用多晶硅、 非晶硅、 锗硅合金、 氧化物、 硅碳合金中的一种或其任意组合作为所述牺牲层 204 的材 料。 所述牺牲层 204的厚度范围为 0.2 μ ιη-1 μ ιη。
[0025]然后， 执行步骤 S103， 在所述凹孔 202 内填充导电材料形成 硅通孔导体 205， 以及形成与该硅通孔导体 205电性连接的第一接触 垫 207。
[0026]具体地， 首先形成硅通孔导体， 如图 6 所示， 在所述牺牲层 204的表面形成种子层（未示出）， 然后通过例如电镀的方式在所述凹 孔 202 中填充导电材料。 在本实施例中， 所述导电材料为铜， 在其 它实施例中， 所述导电材料还可以包括镍、 钨中的一种或其任意组 合。 填充结束后， 至少对所述导电材料进行平坦化， 直至所述导电 材料的上表面与所述牺牲层 204的上表面齐平（本文件内， 术语 "齐 平" 意指两者之间的高度差在工艺误差允许的范围内）， 以形成硅通 孔导体 205。 为了使得最终所形成的芯片体积尽量小， 优选地， 平坦 化所述导电材料、 牺牲层 204以及第一绝缘层 203， 直至暴露所述介 质层 201(在其它实施例中， 如果所述半导体衬底 200第一表面上不 存在介质层， 则平坦化所述导电材料和牺牲层 204 直至暴露所述第 一绝缘层 203，保留所述第一绝缘层 203用于隔离半导体衬底 200以 及保护有源区）， 此时， 所述牺牲层 204仅存在于在凹孔 202(请参考 图 6)内， 并且位于所述硅通孔导体 205与所述第一绝缘层 203之间。
[0027]接着， 参考图 7， 通过例如沉积等方式在所述介质层 201之上 形成第二绝缘层 206，其中，该第二绝缘层 206的材料优选为氮化硅、 氧化物中的一种或者其任意组合， 其厚度范围为 1 μ ιη-10 μ ιη。 参考 图 8， 刻蚀所述第二绝缘层 206形成第一开口 300， 其中， 所述第一 开口 300暴露了所述硅通孔导体 205、牺牲层 204、以及该牺牲层 204 周边的部分区域， 在本实施例中， 所述第一开口 300的横截面（与所 述半导体衬底 200第一表面平行的截面）为圆形， 其直径范围为 8 μ ιη-15 μ ιη。根据需要所述第一开口 300的横截面也可以是方形、条形、 多边形等其他形状。 参考图 9， 优选地在所述第一开口 300内先形成 种子层 (未示出）， 然后通过例如电镀的方式在所述第一开口 300内填 充导电材料， 并通过平坦化操作， 使所述导电材料的上表面与所述 第二绝缘层 206的上表面齐平， 形成与所述硅通孔导体 205上端电 性连接的第一接触垫 207， 其中， 在本实施例中， 所述第一接触垫 207的材料与所述硅通孔导体 205的材料相同， 均为金属铜， 在其它 实施例中， 所述第一接触垫 207 的材料也可以为与所述硅通孔导体 205材料不同的金属， 例如铝等。 所述第一接触垫 207的形成， 使得 所述硅通孔导体 205可以与所述半导体衬底 200相固定。
[0028]在步骤 S104中， 从所述半导体衬底 200的第二表面对该半导 体衬底 200进行减薄， 直至暴露所述硅通孔导体 205。
[0029]具体地， 如图 10所示， 将所述半导体衬底 200固定在承载器 208上，其中，所述承载器 208可以为硅晶圆，也可以为玻璃或塑料。 位于所述半导体衬底 200第一表面上的第一接触垫 207与所述承载 器 208相贴合， 暴露所述半导体衬底 200的第二表面。 然后， 对所 述半导体衬底 200 的第二表面进行磨削或平坦化处理， 直至暴露出 所述硅通孔导体 205。 优选地， 在暴露出所述硅通孔导体 205之后， 还可以通过选择性刻蚀对所述半导体衬底 200、第一绝缘层 203以及 牺牲层 204继续进行刻蚀， 而不刻蚀所述硅通孔导体 205， 使得部分 所述硅通孔导体 205从所述半导体衬底 200、第一绝缘层 203以及牺 牲层 204中突出出来，其中，选择性刻蚀的深度范围为 50nm-500nm。 在平坦化处理暴露出所述硅通孔导体 205 之后， 也可以选择性只对 所述半导体衬底 200继续进行刻蚀， 而不刻蚀所述第一绝缘层 203、 所述牺牲层 204和硅通孔导体 205， 使得部分所述硅通孔导体 205、 牺牲层 204和所述第一绝缘层 203从所述半导体衬底 200中突出出 来。
[0030]接着，如图 11所示，沉积绝缘材料以覆盖所述半导体衬底 200 的第二表面、 硅通孔导体 205、 牺牲层 204以及第一绝缘层 203， 平 坦化该绝缘材料直至暴露所述硅通孔导体 205，然后通过例如光刻的 方式去除位于牺牲层 204 下侧的绝缘材料； 或者上文所述的第二种 情况中， 硅通孔导体 205与牺牲层 204在下端齐平， 当平坦化该绝 缘材料直至暴露所述硅通孔导体 205 时， 牺牲层 204也暴露出来， 则不需光刻的方式去除位于牺牲层 204 下侧的绝缘材料， 从而在所 述半导体衬底 200的第二表面形成第三绝缘层 209。 其中， 所述第三 绝缘层 209的材料与所述第一绝缘层 203的材料相同， 也可以和所 述第一绝缘层 203 的材料不同。 在后续将多个具有硅通孔结构的半 导体衬底相键合时， 所述第三绝缘层 209 可以有效地将相邻的两个 半导体衬底进行隔离， 以防止一半导体衬底的第二表面与另一半导 体衬底上方的第一接触垫相接触， 从而造成短路。
[0031]然后， 执行步骤 S105， 去除所述牺牲层 204， 在所述硅通孔导 体 205和第一绝缘层 203之间形成空隙层 211。
[0032]具体地， 由于所述牺牲层 204的材料与所述硅通孔导体 205以 及第一绝缘层 205 具有不同的选择性， 所以可以采用例如湿法刻蚀 选择性地去除位于硅通孔导体 205和第一绝缘层 203之间的牺牲层 204, 从而在所述硅通孔导体 205与所述第一绝缘层 203之间形成空 隙层 211， 如图 12所示。 因为所述硅通孔导体 205通过第一接触垫 207与半导体衬底 200相固定， 所以， 去除所述牺牲层 204之后， 所 述硅通孔导体 205不会与所述半导体衬底 200分离开。
[0033]在步骤 S106中， 将上述步骤形成所述半导体衬底 200堆叠后 进行键合。
[0034]具体地， 如图 13所示， 首先将所述半导体衬底 200和承载器 208分离开， 然后将多个减薄后的所述半导体衬底 200精确对准， 通 过例如铜-铜键合等方式， 将一半导体衬底的硅通孔导体 205的下端 与另一半导体衬底第一表面上方的第一接触垫 207键合， 从而使多 个所述半导体衬底 200连接起来，形成硅通孔互连结构（图 13仅给出 了两个半导体衬底互连的示意图， 虚线表示两个半导体衬底之间的 互连面）， 其中， 键合为本领域技术人员所公知的技术， 在此不再赘 述。
[0035]可选地， 为了使得相邻的两个半导体衬底键合得更为牢固， 在 形成所述第三绝缘层 209之后， 还可以进一步形成与所述硅通孔导 体 205下端电性连接的第二接触垫 212， 请参考图 14至图 17， 其形 成步骤如下： 在减薄后的所述半导体衬底 200 的第二表面沉积绝缘 材料形成第四绝缘层 210， 其中， 该第四绝缘层 210的材料优选为氮 化硅、 氧化硅中的一种或者其任意组合， 其厚度范围为 1.5 μ ιη- 10 μ m。 刻蚀所述第四绝缘层 210并停止于第三绝缘层 209， 形成第二开 口 301， 其中， 与所述第一开口 300(参考图 8)相似， 所述第二开口 301暴露了所述硅通孔导体 205、 牺牲层 204、 以及该牺牲层 204周 边的部分区域； 接着， 如图 15所示， 选择性去除所述牺牲层 204， 在所述硅通孔导体 205与所述第一绝缘层 203之间形成空隙层 21 1 ; 形成所述空隙层 21 1后， 如图 16所示， 优选地在所述第二开口 301 内的第三绝缘层 209的下侧先形成种子层（未示出）， 并通过例如电镀 的方式在所述第二开口 301 内填充导电材料， 通过工艺控制， 选择 不容易填孔的条件， 这样空隙层 21 1 可以基本没有被填充， 大部分 维持为空隙， 然后通过平坦化操作， 使所述导电材料的上表面与所 述第四绝缘层 210的上表面齐平， 形成与所述硅通孔导体 205下端 电性连接的第二接触垫 212， 其中， 所述第二接触垫 212的材料可以 与所述第一接触垫 207的材料相同，也可以为与所述第一接触垫 207 的材料不同； 最后， 如图 17所示， 将所述多个半导体衬底 200堆叠 互连（图 17仅给出了两个半导体衬底互连的示意图，虚线表示两个半 导体衬底之间的互连面）， 其中， 相邻的两个半导体衬底 200， 一半 导体衬底 200第二表面下方的第二接触垫 212与另一半导体衬底 200 第一表面上方的第一接触垫 207键合。 所述第二接触垫 212的形成， 不但进一步将所述硅通孔导体 205与半导体衬底 200进行固定， 而 且还有效地增加了两个半导体衬底的硅通孔导体之间键合的面积， 从而保证了硅通孔互连结构的牢固性。
[0036]可选地，在所述硅通孔导体 205和所述第一绝缘层 203之间形 成空隙层 211 之后， 还可以通过例如沉积和平坦化等方式在所述空 隙层 211 内填充低 K介电材料 213或者可以吸收形变的材料 213， 如图 18所示。 其中， 所述低 K介电材料 213包括掺氟氧化硅、 碳掺 杂氧化硅、 多孔氧化硅、 多孔碳掺杂氧化硅的一种或其任何组合。 所 述可以吸收形变的材料 213包括多孔硅、 多孔氧化硅、 聚合物的一种 或其任意组合。 所述空隙层 211或者在空隙层 211 中填充的低 K介 电材料层 213 或者可以吸收形变的材料层 213 都可以称为緩冲层 211、 213。
[0037]在上述步骤完成后， 在所述半导体衬底和所述硅通孔导体之间形 成了空隙层或者填充了低 K介电材料， 从而可以有效地降低所述半导 体衬底和所述硅通孔导体之间的寄生电容； 以及， 在所述半导体衬底和 所述硅通孔导体之间形成了空隙层 211 或者填充了可以吸收形变的材 料，从而可以在温度发生变化导致硅通孔导体形变的时候， 通过吸收硅 通孔导体的形变， 有效地减小形变对所述半导体衬底产生的应力作用。
[0038]上文所述的实施例中， 也可以将形成牺牲层 204的步骤替换为形 成不被后续去除的緩冲层 204， 该緩冲层 204的材料可以是单层或多层 结构， 其中有些材料采用上述低 K介电材料、 可以形变材料或其组合。 这样可以省略后续去除牺牲层形成空隙层又填充低 K介电材料或者可 以形变材料的步骤。
[0039]相应地， 本发明还提供了一种硅通孔互连结构， 请参考图 13， 该 体衬底 200的硅通孔导体 205、 以及位于所述半导体衬底 200和硅通孔 导体 205之间的第一绝缘层 203， 其中， 在本实施例中， 所述硅通孔导 体 205的材料为铜，在其它实施例中， 所述硅通孔导体 205的材料还可 以是镍、钨中的一种或其任意组合； 在所述硅通孔导体 205与所述第一 绝缘层 203之间存在緩冲层， 例如空隙层 211; 存在第一接触垫 207， 所述硅通孔导体 205的一端与该第一接触垫 207电性连接，并通过该第 一接触垫 207与所述半导体衬底 200进行固定， 其中， 所述第一接触垫 207的材料优选和所述硅通孔导体 205的材料相同， 也可以为和所述硅 通孔导体 205的材料不同的其他导电材料；所述两个或两个以上半导体 衬底通过所述硅通孔导体 205和所述第一接触垫 207的键合形成互连， 即，如图 13中互连的两个半导体衬底 200所示，其中一半导体衬底 200 硅通孔导体 205的下端与另一半导体衬底 200第一表面上方的第一接触 垫 207相键合 (虚线表示两个半导体衬底 200之间的互连面）， 从而形成 硅通孔互连结构。
[0040]可选地，请参考图 17，本发明所提供的硅通孔互连结构还包括第 二接触垫 212， 所述硅通孔导体 205的另一端与该第二接触垫 212电性 连接，并通过该第二接触垫 212进一步与所述半导体衬底 200进行固定。 此外，所述第二接触垫 212还可以有效地增加互连的两个半导体衬底的 硅通孔导体之间的键合面积，从而保证了硅通孔互连结构的牢固性。 所 述第二接触垫 212的材料可以与所述第一接触垫 207的材料相同，也可 以不同。
[0041]可选地，请参考图 18，在所述硅通孔导体 205与所述第一绝缘层 203之间的緩冲层例如还可以为低 K介电材料层 213、 可以吸收形变的 材料层 213、 或它们的组合， 其中， 所述低 K介电材料层 213包括掺氟 氧化硅、 碳掺杂氧化硅、 多孔氧化硅、 多孔碳掺杂氧化硅中的一种或 其任何组合；所述可以吸收形变的材料层 213包括多孔硅、多孔氧化硅、 聚合物中的一种或其任意组合。
[0042]本发明所提供的硅通孔互连结构， 与传统的硅通孔互连结构相 层， 例如， 空隙层或者低 K介电材料层， 从而有效地降低了所述半导 体衬底与硅通孔导体之间的寄生电容； 此外， 由于在所述半导体衬底与 硅通孔导体之间形成了空隙层或者填充了可以吸收形变的材料，从而可 以在温度发生变化导致硅通孔导体形变的时候，通过吸收硅通孔导体的 形变， 有效地减 '』、形变对所述半导体衬底产生的应力作用。
[0043]其中， 对硅通孔互连结构各实施例中各部分的结构组成、 材料及 形成方法等均可与前述硅通孔互连结构形成方法实施例中描述的相同， 不再赘述。
[0044]虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离 本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实 施例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人 员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以 变化。
[0045]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的 工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内 容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以 后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其 中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体 相同的结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利 要求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含 在其保护范围内。

Claims

权 利 要 求
1. 一种硅通孔互连结构的制造方法， 该方法包括以下步骤： a) 提供半导体衬底 (200)， 该半导体衬底 (200)具有第一表面以及与 该第一表面相对应的第二表面；
b) 从所述半导体衬底 (200)的第一表面形成凹孔 (202)， 并在所述凹 孔 (202)的侧壁和底面上形成第一绝缘层 (203)， 以及在所述第一绝缘层 (203)上形成牺牲层 (204); 所述半导体衬底 (200)的第一表面上形成与该硅通孔导体 (205)电性连接 的第一接触垫 (207);
d) 从所述半导体衬底 (200)的第二表面对该半导体衬底 (200)进行减 薄， 直至暴露所述硅通孔导体 (205)和牺牲层（204 ) ；
e)去除所述牺牲层 (204)，在所述硅通孔导体 (205)和第一绝缘层 (203) 之间形成空隙层 (211);
f) 将多个所述半导体衬底 (200)堆叠后进行键合。
2. 根据权利要求 1所述的制造方法，其中，所述步骤 e)之后还包括： g) 在所述空隙层 (211)中填充低 K介电材料 (213)或者可以吸收形变 的材料 (213)。
3. 根据权利要求 2所述的制造方法， 其中：
所述低 K介电材料 (213)包括掺氟氧化硅、碳掺杂氧化硅、 多孔氧化 硅、 多孔碳掺杂氧化硅的一种或其任何组合；
所述可以吸收形变的材料 (213)包括多孔硅、 多孔氧化硅、 聚合物中 的一种或其任意组合。
4. 根据权利要求 1所述的制造方法， 其中：
在所述半导体衬底 (200)的第一表面的下方存在有源区。
5. 根据权利要求 1或 2所述的制造方法， 其中：
所述牺牲层 (204)的材料包括多晶硅、 非晶硅、 锗硅合金、 氧化物、 硅碳合金中的一种或其任意组合。
6. 根据权利要求 1或 2所述的制造方法， 其中， 所述牺牲层 (204) 的厚度范围为 0.2 μ m-1 μ m。
7. 根据权利要求 1或 2所述的制造方法， 其中， 在所述凹孔（ 202 ) 内填充导电材料形成硅通孔导体的步骤还包括：
在所述牺牲层 (204)的表面沉积种子层；
将导电材料填充至所述凹孔 (202)内；
平坦化所述导电材料与所述半导体衬底（200 ) 的第一表面或者第 一绝缘层 ( 203 )上表面齐平， 形成硅通孔导体 (205)。
8. 根据权利要求 1或 2所述的制造方法， 其中， 形成与该硅通孔导 体电性连接的第一接触垫的步骤还包括：
形成第二绝缘层 (206)以覆盖所述半导体衬底 (200)的第一表面； 刻蚀所述第二绝缘层 (206)形成第一开口（300)，以暴露所述硅通孔导 体 (205)、 所述牺牲层 (204)、 以及至少部分所述牺牲层 (204)周边的区域； 在所述第一开口（300)内填充导电材料；
平坦化所述导电材料， 使其上表面与所述第二绝缘层 (206)上表面齐 平， 形成第一接触垫 (207)。
9. 根据权利要求 1所述的制造方法， 所述步骤 e)包括：
形成第四绝缘层 (210)以覆盖所述半导体衬底 (200)的第二表面； 刻蚀所述第四绝缘层 (210)形成第二开口（301)，以暴露所述硅通孔导 体 (205)、 所述牺牲层 (204)、 以及至少部分所述牺牲层 (204)周边的区域； 去除所述牺牲层 (204)形成空隙层（211 ) ；
在所述第二开口（301)内填充导电材料；
平坦化所述导电材料， 使其上表面与所述第四绝缘层 (210)上表面齐 平， 形成与所述硅通孔导体 (205)电性连接的第二接触垫 (212)。
10. 根据权利要求 9所述的制造方法， 其中去除所述牺牲层 (204)形 成空隙层 （211 ) 的步骤和在所述第二开口（301)内填充导电材料的步骤 之间还包括：
在所述空隙层 (211)中填充低 K介电材料 (213)或者可以吸收形变的 材料 (213)。
11. 根据权利要求 1所述的制造方法， 在所述步骤 d)和所述步骤 e) 之间还包括：
dl) 在所述半导体衬底 (200)的第二表面形成第三绝缘层 (209)。
12. 根据权利要求 1所述的制造方法， 在所述步骤 d)和所述步骤 e) 之间还包括：
d2)对暴露出来的半导体衬底 (200)的第二表面进行刻蚀， 使得所述 硅通孔导体（205 )从所述半导体衬底 (200)的第二表面突出出来。
13. 一种硅通孔互连结构的制造方法， 该方法包括以下步骤： a) 提供半导体衬底 (200)， 该半导体衬底 (200)具有第一表面以及与 该第一表面相对应的第二表面；
b) 从所述半导体衬底 (200)的第一表面形成凹孔 (202)， 并在所述凹 孔 (202)的侧壁和底面上形成第一绝缘层 (203)， 以及在所述第一绝缘层 (203)上形成緩冲层； 所述半导体衬底 (200)的第一表面上形成与该硅通孔导体 (205)电性连接 的第一接触垫 (207);
d) 从所述半导体衬底 (200)的第二表面对该半导体衬底 (200)进行减 薄， 直至暴露所述硅通孔导体 (205)和緩冲层；
f) 将多个所述半导体衬底 (200)堆叠后进行键合；
其中所述緩冲层的材料包括低 K介电材料或者可以吸收形变的材 料。
14. 根据权利要求 13所述的制造方法， 其中：
所述低 K介电材料包括掺氟氧化硅、 碳掺杂氧化硅、 多孔氧化硅、 多孔碳掺杂氧化硅的一种或其任何组合；
所述可以吸收形变的材料包括多孔硅、 多孔氧化硅、 聚合物中的一 种或其任意组合。
15. 一种硅通孔互连结构，该硅通孔互连结构包括半导体衬底 (200)、 贯穿所述半导体衬底 (200)的硅通孔导体 (205)、以及位于所述半导体衬底 (200)和硅通孔导体 (205)之间的第一绝缘层 (203)， 其特征在于包括： 位于所述硅通孔导体 (205)与所述第一绝缘层 (203)之间的緩冲层 ( 211、 213 ) ；
至少一个接触垫 (207、 212), 所述硅通孔导体 (205)的至少一端与该 接触垫 (207、 212)相连接， 并通过该接触垫 (207、 212)与所述半导体衬底 (200)进行固定； 以及 所述接触垫 (207)之间或者两个所述接触垫 (207)之间的键合形成互连。
16. 根据权利要求 15所述的结构， 其中：
所述緩冲层（211、 213 ) 为空隙层 (211)、 低 K介电材料层 (213)或 者可以吸收形变的材料层 (213)。
17. 根据权利要求 16所述的结构， 其中：
所述低 K介电材料层 (213)包括掺氟氧化硅、碳掺杂氧化硅、 多孔氧 化硅、 多孔碳掺杂氧化硅中的一种或其任何组合。
18. 根据权利要求 16所述的结构， 其中：
所述可以吸收形变的材料层 (213)包括多孔硅、 多孔氧化硅、 聚合物 中的一种或其任意组合。
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CN103295915A (zh) * 2012-03-05 2013-09-11 北京北方微电子基地设备工艺研究中心有限责任公司 Tsv转接板的制作方法及tsv转接板
CN104752321A (zh) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN107980171A (zh) * 2016-12-23 2018-05-01 苏州能讯高能半导体有限公司 半导体芯片、半导体晶圆及半导体晶圆的制造方法
WO2019241571A1 (en) * 2018-06-13 2019-12-19 Invensas Bonding Technologies, Inc. Large metal pads over tsv
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
CN112086370A (zh) * 2019-06-13 2020-12-15 南亚科技股份有限公司 集成电路元件及其制备方法
CN112164688A (zh) * 2017-07-21 2021-01-01 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
CN112466842A (zh) * 2020-11-24 2021-03-09 复旦大学 一种多功能tsv结构及其制备方法
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CN113539945A (zh) * 2020-04-16 2021-10-22 长鑫存储技术有限公司 半导体结构及其形成方法
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
CN114852948A (zh) * 2022-04-29 2022-08-05 清华大学 基于硅通孔的mems传感器集成装置及其制造方法
CN115692312A (zh) * 2023-01-05 2023-02-03 湖北江城芯片中试服务有限公司 半导体结构的制备方法及半导体结构
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CN116960058A (zh) * 2023-09-20 2023-10-27 湖北江城芯片中试服务有限公司 转接板的制备方法及转接板
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
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WO2013130425A1 (en) * 2012-02-27 2013-09-06 Qualcomm Incorporated Structure and method for strain-relieved tsv
US8779559B2 (en) 2012-02-27 2014-07-15 Qualcomm Incorporated Structure and method for strain-relieved TSV
CN104137250A (zh) * 2012-02-27 2014-11-05 高通股份有限公司 应变缓减的tsv的结构和方法
US9355904B2 (en) 2012-02-27 2016-05-31 Qualcomm Incorporated Method for strain-relieved through substrate vias
CN104137250B (zh) * 2012-02-27 2017-02-22 高通股份有限公司 应变缓减的tsv的结构和方法
CN103295915A (zh) * 2012-03-05 2013-09-11 北京北方微电子基地设备工艺研究中心有限责任公司 Tsv转接板的制作方法及tsv转接板
CN104752321A (zh) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN104752321B (zh) * 2013-12-27 2018-01-02 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN107980171A (zh) * 2016-12-23 2018-05-01 苏州能讯高能半导体有限公司 半导体芯片、半导体晶圆及半导体晶圆的制造方法
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
CN112164688A (zh) * 2017-07-21 2021-01-01 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11552041B2 (en) 2017-09-24 2023-01-10 Adeia Semiconductor Bonding Technologies Inc. Chemical mechanical polishing for hybrid bonding
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
US11955445B2 (en) 2018-06-13 2024-04-09 Adeia Semiconductor Bonding Technologies Inc. Metal pads over TSV
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
WO2019241571A1 (en) * 2018-06-13 2019-12-19 Invensas Bonding Technologies, Inc. Large metal pads over tsv
US11728313B2 (en) 2018-06-13 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Offset pads over TSV
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11756880B2 (en) 2018-10-22 2023-09-12 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
CN112086370A (zh) * 2019-06-13 2020-12-15 南亚科技股份有限公司 集成电路元件及其制备方法
CN112086370B (zh) * 2019-06-13 2022-12-02 南亚科技股份有限公司 集成电路元件及其制备方法
US11764148B2 (en) 2019-06-13 2023-09-19 Nanya Technology Corporation Method of forming integrated circuit device with bonding structure
CN113539945A (zh) * 2020-04-16 2021-10-22 长鑫存储技术有限公司 半导体结构及其形成方法
CN113539945B (zh) * 2020-04-16 2023-09-29 长鑫存储技术有限公司 半导体结构及其形成方法
US11929347B2 (en) 2020-10-20 2024-03-12 Adeia Semiconductor Technologies Llc Mixed exposure for large die
CN112466842B (zh) * 2020-11-24 2022-10-21 复旦大学 一种多功能tsv结构及其制备方法
CN112466842A (zh) * 2020-11-24 2021-03-09 复旦大学 一种多功能tsv结构及其制备方法
CN114852948A (zh) * 2022-04-29 2022-08-05 清华大学 基于硅通孔的mems传感器集成装置及其制造方法
CN114852948B (zh) * 2022-04-29 2024-04-02 清华大学 基于硅通孔的mems传感器集成装置及其制造方法
CN115692312B (zh) * 2023-01-05 2023-05-02 湖北江城芯片中试服务有限公司 半导体结构的制备方法及半导体结构
CN115692312A (zh) * 2023-01-05 2023-02-03 湖北江城芯片中试服务有限公司 半导体结构的制备方法及半导体结构
US12125784B2 (en) 2023-08-17 2024-10-22 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures
CN116960058A (zh) * 2023-09-20 2023-10-27 湖北江城芯片中试服务有限公司 转接板的制备方法及转接板
CN116960058B (zh) * 2023-09-20 2024-01-26 湖北江城芯片中试服务有限公司 转接板的制备方法及转接板

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