CN113539945A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN113539945A
CN113539945A CN202010299490.5A CN202010299490A CN113539945A CN 113539945 A CN113539945 A CN 113539945A CN 202010299490 A CN202010299490 A CN 202010299490A CN 113539945 A CN113539945 A CN 113539945A
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hole
layer
concave hole
forming
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CN113539945B (zh
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张志伟
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Abstract

该发明涉及半导体封装制程领域，公开了一种半导体结构及其形成方法。该形成方法包括：提供半导体衬底，所述半导体衬底表面具有显露的导电结构；在所述半导体衬底和所述显露的导电结构的表面形成钝化层；刻蚀所述钝化层以形成凹孔，所述凹孔的底部暴露出所述导电结构的一端；在所述凹孔表面形成黏附层；进行刻蚀，以形成所述凹孔底部内的孔洞。本发明改进金属层接触面的结构工艺，将金属层与钝化层凹孔底部孔洞作为金属热膨胀时的缓冲，来控制化学机械工艺中背面通孔显露装置的稳定性，从而使得封装后半导体结构的性能改善、可靠性增强。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体封装制程领域，具体涉及一种半导体结构及其形成方法。
背景技术
随着半导体集成电路器件特征尺寸的不断缩小，对半导体封装制程技术的要求也在不断提高。现有的硅通孔封装技术是通过在芯片和芯片之间制作垂直导通，实现芯片和芯片之间互连，该技术能够使芯片在三维方向堆叠的密度最大，外形尺寸最小，并且大大改善了芯片速度和低功耗的性能。
在硅通孔封装技术的制造流程中，涉及到晶圆异键合制成，其需要控制金属层接触面的深度在1至5纳米，对现有工艺技术要求极高，非常难控制。当金属层深度过深，金属之间会出现断路，无法接通；当金属层深度过浅，金属层由键合面挤压，造成键合分离或是与邻近的金属层短路。因此，如何控制化学机械工艺中背面通孔显露装置的稳定性，避免当化学机械平坦化时，出现金属层深度过深的断路问题以及金属层深度过浅的短路问题是目前亟待解决的技术问题。
发明内容
本发明的目的在于提供一种半导体结构及其形成方法，能够使得封装后半导体结构的性能改善、可靠性增强。
为解决上述技术问题，本发明中提供了一种半导体结构的形成方法，包括如下步骤：
提供半导体衬底，所述半导体衬底表面具有显露的导电结构；
在所述半导体衬底和所述显露的导电结构的表面形成钝化层；
刻蚀所述钝化层以形成凹孔，所述凹孔的底部暴露出所述导电结构的一端；
在所述凹孔表面形成黏附层；
进行刻蚀，以形成所述凹孔底部内的孔洞。
可选的，在所述凹孔表面形成黏附层还包括：沿着所述凹孔的侧壁至所述凹孔底部的方向，所述黏附层的厚度逐渐减小，直至暴露出所述凹孔的侧壁。
可选的，所述暴露出凹孔的侧壁的高度为1-5微米。
可选的，形成所述孔洞的步骤进一步包括：采用各向同性刻蚀工艺，通过刻蚀所述暴露出凹孔侧壁形成所述孔洞，所述孔洞连续排布于所述凹孔底部四周内。
可选的，所述孔洞的横截面的形状为圆形或者椭圆形；所述孔洞的尺寸为1至5微米。
可选的，所述凹孔的尺寸为5-30微米。
可选的，所述黏附层的材料包括：钽、氮化钽或其组合。
可选的，在黏附层表面沉积种子层。
可选的，在形成所述凹孔底部内的孔洞后，还包括：形成一阻挡层于所述孔洞内的表面。
可选的，所述阻挡层厚度为80-120纳米。
可选的，填充金属层至所述凹孔内。
相应的，本发明的的技术方案还提供一种半导体结构，包括：
半导体衬底，所述半导体衬底表面具有显露的导电结构；
钝化层，沉积于所述半导体衬底和所述显露的导电结构的表面；
凹孔，位于所述钝化层内，所述凹孔的底部暴露出所述导电结构的一端；
黏附层，沉积于所述凹孔表面；
孔洞，位于所述凹孔底部；
金属层，填充于所述凹孔内。
可选的，阻挡层，沉积于所述孔洞内的表面。
可选的，所述孔洞连续排布于所述凹孔底部四周内。
本发明的优点在于，相较于现有的硅通孔封装技术，本发明主要改进了半导体金属接触孔的结构工艺，将金属层与钝化层凹孔之间的孔洞作为异质键合时金属热膨胀时的缓冲，来控制化学机械工艺中背面通孔显露结构的稳定性，进而也增强了晶圆键合的能力。从而使得封装后半导体结构的性能改善、可靠性增强。
附图说明
图1至图9为本发明的一种具体实施方式中的半导体结构及其形成方法依次实施各步骤所得到结构示意图；
图10A和图10B为本发明的一种具体实施方式中的半导体结构俯视剖面图。
附图标记：
100：半导体衬底；200：导电结构；101：钝化层；w：凹孔；102：黏附层；201：孔洞；103：阻挡层；300：金属层。
具体实施方式
以下结合附图和具体实施方式对本发明提出的一种半导体结构及其形成方法作进一步详细说明。
步骤一，提供半导体衬底，所述半导体衬底表面具有显露的导电结构。
在本实施例中，所述半导体衬底表面具有显露的导电结构的形成方式可以为：
请参阅图1，提供一半导体衬底100，所述半导体衬底100内具有一导电结构200，所述导电结构200的一端位于半导体衬底100的第二表面，所述导电结构200的另一端内置于所述半导体衬底100的第一表面。在一实施例中，所述半导体衬底100为晶圆，所述第一表面为所述晶圆的晶背，所述第二表面为所述晶圆的晶面。请参阅图2，通过研磨工艺，去除部分第一表面的所述半导体衬底层，暴露出所述导电结构200，所述导电结构200显露于所述半导体衬底100的第一表面，从而形成所述具有显露的导电结构200的半导体衬底100。
提供半导体衬底100，所述半导体衬底100可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，半导体衬底100为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是掺杂硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。
所述显露的导电结构200穿过所述半导体衬底100的表面；所述显露的导电结构200可以但不限于是钨、铜等相关集成电路导电材料。进一步的，在所述导电结构200的侧壁有氧化硅或氮化硅隔离层，用于防止导电材料铜扩散到半导体衬底中。
步骤二，请参阅图3为在所述半导体衬底100和所述显露的导电结构200的表面形成钝化层101。
具体地说，通过沉积工艺在所述半导体衬底100表面和所述显露的导电结构200的表面沉积钝化层101。在薄膜沉积工艺中，主要的沉积方式有两种：化学气相沉积，将一种或数种物质的气体，以某种方式激活后，在衬底表面发生化学反应，并沉积出所需固体薄膜的生长技术。物理气相沉积，利用某种物理过程实现物质的转移，即将原子或分子转移到硅衬底表面，并沉积成薄膜的技术。沉积薄膜的技术还有旋涂法、电镀法等。本实施方式中，钝化层101的具体沉积方式可以是多样的。例如，采用化学气相沉积的方式，在半导体衬底100的表面，沉积预设厚度分布的钝化层101。进一步的，可以单独运用控制导入气流的流速、控制导入气流的流量、控制沉积时长或控制沉积温度的控制手段，通过提高对气流和温度的控制精度，可以确保所有原子沉积时排列整齐，形成单晶层，最终在半导体衬底100及显露的导电结构200的表面得到一层厚度均匀的钝化层101。
常用的沉积材料有二氧化硅、氮化硅等隔离互连层的绝缘材料。因此，钝化层101的材料可以包括但不限于二氧化硅、氮化硅、氮氧化硅等相关集成电路绝缘材料。
步骤三，请参阅图4为刻蚀所述钝化层101表面以形成凹孔w，所述凹孔w的底部暴露出所述导电结构200的一端。
具体地说，在刻蚀钝化层101的步骤之前还包括：在钝化层101表面形成图形化的第一掩膜层(未示出)。所述第一掩膜层图形间隔排列。根据第一掩膜层上设计为间隔排列的图案，刻蚀钝化层101，将第一掩膜层图形转移到了钝化层101上。
进一步的，所述凹孔的尺寸为5-30微米，即所述凹孔的深度为5-30微米，例如10微米，15微米，20微米或25微米。所述凹孔的形状可以为圆形，方形或其他不规则形状。本领域技术人员可以理解，在封装工艺中，其中硅通孔工艺需要将半导体衬底、导电结构、通孔相连通，以满足后续其他工艺步骤。
步骤四，请参阅图5，在所述凹孔w表面形成黏附层102。
具体地说，通过溅镀工艺在上述刻蚀后凹孔w的表面沉积黏附层102。所述黏附层102覆盖所述凹孔的部分侧壁，且覆盖所述凹孔的底部及所述钝化层101远离所述凹孔底部的表面。在一实施方式中，沿着所述凹孔的侧壁至所述凹孔底部的方向，所述黏附层102的厚度逐渐减小，直至暴露出所述凹孔的侧壁。由于溅镀工艺会导致垂直面覆盖率不佳，最不容易覆盖的地方是凹孔的角落。在本实施方式中，通过控制沉积速度，可以使所述凹孔的侧壁沉积形成倒三角状的黏附层102，所述凹孔的侧壁靠近底部的位置均没有沉积黏附层102。其中凹孔下侧壁未被黏附层102覆盖的高度为1-5微米，例如2微米或4微米。同时，所述黏附层102的材料包括：钽、氮化钽或其组合。所述黏附层102的厚度为35-45纳米，例如为40纳米。因此，通过控制溅镀工艺形成所述黏附层102，可以控制所述凹孔下侧壁未被黏附层覆盖的高度尺寸，从而控制后期形成的孔洞201的尺寸。且沉积形成的黏附层102能使后期种子层更均匀致密的沉积在衬底上。
进一步的，在另一实施方式中，可以在黏附层102表面沉积种子层(未示出)。所述种子层的材料为铜种子。所述种子层的厚度为80-120纳米，例如为100纳米。为了更便于后续工艺中填充金属层，可以提前准备在本步骤中形成铜种子层。同时，在本实施方式的步骤中也可以先不用沉积种子层，而在后续电镀金属层之前形成金属黏附层。
步骤五，请参阅图6，进行刻蚀，以形成所述凹孔底部内的孔洞201。
在一实施方式中，可采用各向同性刻蚀工艺，通过刻蚀所述暴露出凹孔的侧壁形成所述孔洞201，所述孔洞201连续排布于所述凹孔底部四周内。
具体地说，通过湿法刻蚀，可以使原先凹孔内未被沉积黏附层102的角落形成孔洞201。在本实施方式中，俯视剖面图(图10A/图10B)可以看到凹孔w的底部四周环绕着孔洞201，孔洞201连续起来可以定义为环状包围在凹孔底部。由于湿法蚀刻是各向同性，因此，孔洞201的横截面的形状为圆形或者椭圆形，或其他近似圆形的形状。所述孔洞的尺寸为1至5微米。进一步的，在其它实施例中，也可以采用化学干法刻蚀工艺形成所述孔洞201。化学干法刻蚀利用等离子体中的化学活性原子团与被刻蚀材料发生化学反应，从而实现刻蚀目的。由于刻蚀的核心还是化学反应(只是不涉及溶液的气体状态)，因此，刻蚀的效果和湿法刻蚀有些相近，具有较好的选择性。
因此，本实施方式相较于现有的硅通孔封装技术，本发明主要改进了半导体金属接触孔的结构工艺，即在金属层下面外缘形成一圈孔洞。金属层与钝化层凹孔之间的孔洞作为金属热膨胀时的缓冲，来控制化学机械工艺中背面通孔显露装置的稳定性，进而也增强了晶圆键合的能力。从而使得封装后半导体结构的性能改善、可靠性增强。同时，相比于在金属层上端形成孔洞，本发明能避免在后期化学机械抛光工艺中颗粒物卡在孔洞的风险。
步骤六，请参阅图7，形成一阻挡层103于所述孔洞201内的表面。
具体地说，通过气相沉积工艺，在刻蚀后所述凹孔w和所述孔洞201内黏附层102的表面沉积一阻挡层103。利用气相沉积工艺具有很好的覆盖率的特征，可以在所述孔洞201内的黏附层102表面形成一层比较均匀的阻挡层103。在其他实施例中，也可以采用其他合适的工艺形成所述阻挡层103。所述阻挡层103的材料为氮化硅等绝缘材料。所述阻挡层103的厚度为80-120纳米，例如为100纳米。通过干法刻蚀工艺去除所述凹孔w侧壁及底部的阻挡层103，保留孔洞内的阻挡层103，从而只形成孔洞201内表面的阻挡层103。干法刻蚀工艺由于具有良好的各相异性蚀刻特点，因此，刻蚀过程中，刻蚀气体只在纵深方向对所述阻挡层103进行刻蚀，而不会钻进孔洞201内，从而保证孔洞内的阻挡层103能被保留下来。在本实施方式中，所述阻挡层103可以防止后续沉积金属层300时，通过所述孔洞201，金属高温扩散至钝化层101内，从而形成寄生电容。同时，也可以防止在键合时，金属热膨胀缓冲至所述孔洞201，进而钻进所述钝化层101内。因此，通过在孔洞201内形成一层阻挡层103，可以提升半导体制造工艺中半导体结构的良品率。
步骤七，请参阅图8为填充金属层300至所述凹孔w内。
具体地说，采用电镀技术在凹孔中填充金属铜。所述金属层300的材料可以为但不限于钨、铜、铝等相关集成电路导电材料。在另一实施例中，采用电镀技术沉积金属层300之前，可以溅镀一层种子层(未示出)于所述黏附层102表面，然后进行电镀工艺。在电镀工艺中，由于孔洞201内没有种子层，所以在所述孔洞201内不会有电镀金属形成。同时，请参阅图9为采用化学机械抛光技术磨平钝化层101上表面多余的金属层300和黏附层102。
本发明的具体实施方式还提供一种半导体结构，请参考图9。
所述半导体器件包括：半导体衬底100，导电结构200，钝化层101，凹孔w，黏附层102，孔洞201，金属层300。
所述半导体衬底100表面具有显露的导电结构200。所述显露的导电结构200穿过所述半导体衬底100的表面；所述显露的导电结构200可以但不限于是钨、铜等相关集成电路导电材料。进一步的，在所述导电结构200的侧壁有氧化硅或氮化硅隔离层，用于防止导电材料铜扩散到半导体衬底中。
所述半导体衬底100可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，半导体衬底100为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是掺杂硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。
所述钝化层101沉积于所述半导体衬底100和所述显露的导电结构200表面。所述钝化层101的材料可以包括但不限于二氧化硅、氮化硅、氮氧化硅等相关集成电路绝缘材料。
所述凹孔w位于所述钝化层101内，所述凹孔w的底部暴露出所述导电结构200的一端。所述凹孔的尺寸为5-30微米，即所述凹孔的深度为5-30微米，例如10微米，15微米，20微米或25微米。所述凹孔的形状可以为圆形，方形或其他不规则形状。本领域技术人员可以理解，在封装工艺中，其中硅通孔工艺需要将半导体衬底、导电结构、通孔相连通，以满足后续其他工艺步骤。
所述黏附层102沉积于所述凹孔w表面。通过溅镀工艺在上述刻蚀后凹孔w的表面沉积黏附层102。所述黏附层102覆盖所述凹孔的部分侧壁，且覆盖所述凹孔的底部及所述钝化层101远离所述凹孔底部的表面。沿着所述凹孔的侧壁至所述凹孔底部的方向，所述黏附层102的厚度逐渐减小，直至暴露出所述凹孔的侧壁。由于溅镀工艺会导致垂直面覆盖率不佳，最不容易覆盖的地方是凹孔的角落。因此，在本实施方式中，通过控制沉积速度，可以使所述凹孔的侧壁沉积有倒三角状的黏附层102，所述凹孔底侧壁靠近底部四周均没有沉积黏附层102。其中，凹孔下侧壁未被黏附层102覆盖的高度为1-5微米，例如2微米或4微米。同时，所述黏附层102的材料包括：钽、氮化钽或其组合。所述黏附层的厚度为35-45纳米，例如为40纳米。
进一步的，可以在黏附层表面沉积种子层(未示出)；所述种子层的材料为铜种子。所述种子层的厚度为80-120纳米，例如为100纳米。
进一步的，形成孔洞201于所述凹孔的底部。所述孔洞201连续排布于所述凹孔底部四周内。采用各向同性刻蚀工艺，通过刻蚀所述暴露的凹孔侧壁，以在所述凹孔底部四周内形成所述孔洞201，所述孔洞201连续排布于所述凹孔底部四周内。具体地说，通过湿法刻蚀，可以使原先凹孔内未被沉积黏附层102的角落形成孔洞201。俯视剖面图(图10A/图10B)可以看到凹孔w的底部四周环绕着孔洞201，孔洞201连续起来可以定义为环状包围在凹孔底部。由于湿法蚀刻是各向同性，因此，孔洞201的横截面的形状为圆形或者椭圆形，或其他近似圆形的形状。所述孔洞的尺寸为1-5微米。
进一步的，所述阻挡层103沉积于所述孔洞201内的表面。通过气相沉积工艺，在所述凹孔w和所述孔洞201表面沉积一阻挡层103，而后利用干法刻蚀工艺去除所述凹孔w侧壁和底部的阻挡层103，保留所述孔洞201内钝化层表面的阻挡层103。所述阻挡层103的材料为氮化硅等绝缘材料。所述阻挡层103的厚度为80-120纳米，例如为100纳米。在本实施方式中，所述阻挡层103可以防止后续沉积金属层300时，通过所述孔洞201，金属高温扩散至钝化层内，从而形成寄生电容。同时，也可以防止在键合时，金属热膨胀缓冲至所述孔洞201，进而钻进所述钝化层101内。因此，通过在孔洞201内形成以层阻挡层103，可以提升半导体制造工艺中半导体结构的良品率。
进一步的，所述金属层300填充于所述凹孔内。采用电镀ECP技术在凹孔中填充金属铜。所述金属层300的材料可以为但不限于钨、铜、铝等相关集成电路导电材料。
因此，本实施方式相较于现有的硅通孔封装技术，本发明主要改进了半导体金属接触孔的结构工艺，即在金属层下面外缘形成一圈孔洞。利用金属层与钝化层凹孔之间的孔洞作为金属热膨胀时的缓冲，来控制化学机械工艺中背面通孔显露装置的稳定性，进而也增强了晶圆键合的能力。从而使得封装后半导体结构的性能改善、可靠性增强。同时，相比于在金属层上端形成孔洞，本发明能避免在后期化学机械抛光工艺中颗粒物卡在孔洞的风险。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (14)

1.一种半导体结构的形成方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底表面具有显露的导电结构；
在所述半导体衬底和所述显露的导电结构的表面形成钝化层；
刻蚀所述钝化层以形成凹孔，所述凹孔的底部暴露出所述导电结构的一端；
在所述凹孔表面形成黏附层；
进行刻蚀，以形成所述凹孔底部内的孔洞。
2.根据权利要求1所述的半导体结构的形成方法，其特征在于，在所述凹孔表面形成黏附层还包括：沿着所述凹孔的侧壁至所述凹孔底部的方向，所述黏附层的厚度逐渐减小，直至暴露出所述凹孔的侧壁。
3.根据权利要求2所述的半导体结构的形成方法，其特征在于，所述暴露出凹孔的侧壁的高度为1-5微米。
4.根据权利要求2所述的半导体结构的形成方法，其特征在于，形成所述孔洞的步骤进一步包括：采用各向同性刻蚀工艺，通过刻蚀所述暴露出凹孔的侧壁形成所述孔洞，所述孔洞连续排布于所述凹孔底部四周内。
5.根据权利要求1所述的半导体结构的形成方法，其特征在于，还包括：所述孔洞的横截面的形状为圆形或者椭圆形；所述孔洞的尺寸为1至5微米。
6.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述凹孔的尺寸为5-30微米。
7.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述黏附层的材料包括：钽、氮化钽或其组合。
8.根据权利要求1所述的半导体结构的形成方法，其特征在于，在所述黏附层表面沉积种子层。
9.根据权利要求1所述的半导体结构的形成方法，其特征在于，在形成所述凹孔底部内的孔洞后，还包括：形成一阻挡层于所述孔洞内的表面。
10.根据权利要求9所述的半导体结构的形成方法，其特征在于，所述阻挡层厚度为80-120纳米。
11.根据权利要求1所述的半导体结构的形成方法，其特征在于，还包括：填充金属层至所述凹孔内。
12.一种半导体结构，其特征在于，包括：
半导体衬底，所述半导体衬底表面具有显露的导电结构；
钝化层，沉积于所述半导体衬底和所述显露的导电结构的表面；
凹孔，位于所述钝化层内，所述凹孔的底部暴露出所述导电结构的一端；
黏附层，沉积于所述凹孔表面；
孔洞，位于所述凹孔底部；
金属层，填充于所述凹孔内。
13.根据权利要求12所述的半导体结构，其特征在于，还包括：阻挡层，沉积于所述孔洞内的表面。
14.根据权利要求12所述的半导体结构，其特征在于，所述孔洞连续排布于所述凹孔底部四周内。
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