CN112086370B - 集成电路元件及其制备方法 - Google Patents

集成电路元件及其制备方法 Download PDF

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CN112086370B
CN112086370B CN202010176914.9A CN202010176914A CN112086370B CN 112086370 B CN112086370 B CN 112086370B CN 202010176914 A CN202010176914 A CN 202010176914A CN 112086370 B CN112086370 B CN 112086370B
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substrate
pad
conductive portion
conductive
expansion
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CN112086370A (zh
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蔡子敬
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种集成电路元件及其制备方法。该集成电路元件具有一第一基底、一第二基底、一第一扩展垫、一第二扩展垫以及一接合结构。该第一基底提供有一第一导电部，该第二基底提供有一第二导电部，该第一扩展垫形成在该第一导电部上以提供一第一扩展接触区，该第二扩展垫形成在该第二导电部上以提供一第二扩展接触区，该接合结构形成在该第一基底与第二基底之间，其中该第一扩展垫接合该第二扩展垫。

Description

集成电路元件及其制备方法
技术领域
本公开主张22019/06/13申请的美国正式申请案第16/440,292号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
本公开涉及一种集成电路元件及其制备方法。特别涉及一种具有接合结构的集成电路元件及其制备方法。
背景技术
集成电路是广泛地使用在电子元件(electronic devices)中。在集成电路产业中，在微小化特征尺寸中的持续缩小是允许多个组件(components)整合在一给定区(givenarea)中。一个最新发展则是三维集成电路(three-dimensional integrated circuits，3DICs)，其是多个半导体晶粒(dies)相互堆叠在其上，且使用封装技术，例如堆叠式封装(package-on-package，PoP)以及系统级封装(system in package，SiP)。一些3DICs是通过在一半导体晶圆级上的多个晶粒置放多个晶粒所准备。3DICs提供改善的集成密度(integration density)以及其他优点，例如更快的速度以及较佳的带宽(bandwidth)。
在寻找减少多个堆叠晶粒之间的内连线(interconnects)的长度的方法同时，因为一拙劣的对准可造成二基底之间的内连线的误置(misplacement)，所以二基底的对准(alignment)变得至关重要。举例来说，假使一基底的一导电部由于所述的拙劣的对准而使适合地与其他基底的其他导电部的耦接失败的话，则将很可能发生一导电缺陷(conductive defect)。然而，在半导体制造期间，继续进行完美对准(perfect alignment)是无效率的，此后其是在制程时间中需要一显著的提升。
上文的“现有技术”说明仅是提供背景技术，并未承认上文的“现有技术”说明本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的一实施例提供一种在一集成电路元件。该集成电路元件包括一第一基底、一第二基底、一第一扩展垫、一第二扩展垫以及一接合结构。在一些实施例中，该第一基底提供有一第一导电部。在一些实施例中，该第二基底提供有一第二导电部。在一些实施例中，该第一扩展垫形成在该第一导电部上，以提供一第一扩展接触区。在一些实施例中，该第二扩展垫形成在该第二导电部上，以提供一第二扩展接触区。在一些实施例中，该接合结构形成在该第一基底与该第二基底之间，其中该第一扩展垫接合该第二扩展垫。
在本公开的一些实施例中，该第一扩展垫大致地对准该第二扩展垫。
在本公开的一些实施例中，该第一导电部与该第二导电部由铜所形成，该第一扩展垫与该第二扩展垫由以下至少其中之一所形成：锗化铜(copper germanide，Cu3Ge)、铜填充(copperfil，Cu3Si)以及铜碳簇(copper-carbon cluster，Cu3C)。
在本公开的一些实施例中，该第一扩展垫与该第二扩展垫分别地围绕该第一导电部与该第二导电部设置。
在本公开的一些实施例中，该第一导电部的一侧壁的一部分直接接触该第一扩展垫，该第二导电部的一侧壁的一部分直接接触该第二扩展垫。
在本公开的一些实施例中，该第一导电部与该第二导电部由铜所形成，该第一扩展垫与该第二扩展垫通过将导电材料镀覆(plating)在该第一导电部与该第二导电部周围所形成。
在本公开的一些实施例中，所述的集成电路元件还包括一第一基底穿孔(firstthrough-substrate via)以及一内连线结构(interconnect structure)，该第一基底穿孔形成在该第一基底中，该内连线结构形成在该第一基底穿孔上，其中该第一基底穿孔位在该内连线结构与该接合结构之间。
在本公开的另一实施例中提供一种集成电路元件的制备方法。该制备方法包括提供一第一基底，该第一基底具有一第一导电部；提供一第二基底，该第二基底具有一第二导电部；执行一第一化学反应以在该第一导电部上形成一第一扩展垫，并提供一第一扩展接触区；执行一第二化学反应以在该第二导电部上形成一第二扩展垫，并提供一第二扩展接触区；以及以一接合结构将该第一基底接合到该第二基底。
在本公开的一些实施例中，所述的集成电路元件的制备方法还包括对准该第一扩展垫与该第二扩展垫。
在本公开的一些实施例中，该第一导电部含有铜。
在本公开的一些实施例中，该第一化学反应具有用锗烷(germane)与铜产生反应以获取锗化铜(copper germanide)、用硅烷(silane)与铜产生反应以获取铜填充(copperfil)，或是用甲烷(methane)与铜产生反应以获取铜碳簇(copper-carboncluster)。
在本公开的一些实施例中，所述的集成电路元件的制备方法还包括在执行该第一化学反应之前，执行一化学机械研磨制程(chemical mechanical polishing process)，以暴露该第一导电部的一侧壁通过该第一基底的至少一部分。
在本公开的一些实施例中，该第一扩展垫接合到该第二扩展垫，以使该第一扩展接触区大致地直接接触该第二扩展接触区。
在本公开的一些实施例中，所述的集成电路元件的制备方法还包括在该第一基底中形成一第一基底穿孔以及在该第一基底穿孔上形成一内连线结构。
在本公开的一些实施例中，该第一基底穿孔位在该内连线结构与该接合结构之间。
在本公开的另一实施例中提供一种集成电路元件的制备方法。该制备方法包括提供一第一基底，该第一基底具有一第一导电部；提供一第二基底，该第二基底具有一第二导电部；执行一第一镀覆制程(first plating process)以在该第一导电部上形成一第一扩展垫，并提供一第一扩展接触区；执行一第二镀覆制程以在该第二导电部上形成一第二扩展垫，并提供一第二扩展接触区；以及以一接合结构将该第一基底接合到该第二基底。
在本公开的一些实施例中，该第一导电部由铜(copper)所制，且该第一扩展垫为镀覆在该铜上的锡(nickel)。
在本公开的一些实施例中，所述的集成电路元件的制备方法还包括对准该第一扩展垫与该第二扩展垫。
在本公开的一些实施例中，该第一扩展垫接合到该第二扩展垫，以使该第一扩展接触区大致地直接接触该第二扩展接触区。
在本公开的一些实施例中，所述的集成电路元件的制备方法还包括在该第一基底中形成一第一基底穿孔以及在该第一基底穿孔上形成一内连线结构，其中该第一基底穿孔位在该内连线结构与该接合结构之间。
由于上述集成电路元件的架构以及其制备方法，二基底的所述导电部均具有各自的扩展垫，以便可增加接触区。因此，可以减轻由拙劣对准所造成的导电性问题(conductivity problems)。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或制程而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离后附的权利要求所界定的本公开的精神和范围。
附图说明
参阅实施方式与权利要求合并考量附图时，可得以更全面了解本公开的公开内容，附图中相同的元件符号是指相同的元件。
图1为依据本公开一种集成电路元件的制备方法的一第一优选实施例的流程示意图。
图2A至图2F为依据本公开该第一优选实施例的一种集成电路元件的制备方法在不同阶段的剖视示意图。
图3为依据本公开一种集成电路元件的制备方法的一第二优选实施例的流程示意图。
图4A至图4E为依据本公开该第二优选实施例的一种集成电路元件的制备方法在不同阶段的剖视示意图。
其中，附图标记说明如下：
20 集成电路元件(3DIC堆叠结构)
40 集成电路元件(3DIC堆叠结构)
100 制备方法
102 步骤
104 步骤
106 步骤
108 步骤
110 步骤
200 第一半导体元件
201 第一化学反应
202 第一半导体基底
203 薄化制程
204 介电层
205 第一镀覆制程
206 隔离材料
207 栅极介电层
208 第一聚合物材料
209 栅极电极
210 第一元件区
211 源极/漏极区
212 第一导电特征
213 隔离结构
214 第一导电部
215 第一扩展垫
215A 第一扩展接触区
216 扩散阻障层
218 接触插塞
220 第一接合结构
222 第二聚合物材料
300 第二半导体元件
300’ 第二半导体元件
301 第二化学反应
302 第二半导体基底
305 第二镀覆制程
306 隔离材料
307 栅极介电层
308 第二聚合物材料(第三聚合物材料)
309 栅极电极
310 第二元件区
311 源极/漏极区
312 导电特征
313 隔离结构
314 第二导电部
315 第二扩展垫
315A 第二扩展接触区
316 扩散阻障层
318 接触插塞
320 第二接合结构
322 第四聚合物材料
350 重分布结构
352 金属垫
354 钝化层
356 导电组件
358 凸块下金属化层
400 混合式接合结构
500 直通硅穿孔(TSV)
502 衬垫
504 扩散阻障层
506 导电材料
600 内连线结构
600’ 内连线结构
610 导电特征
620 隔离材料
700 制备方法
702 步骤
704 步骤
706 步骤
708 步骤
710 步骤
800 直通硅穿孔(TSV)
802 衬垫
804 扩散阻障层
806 导电材料
D1 深度
D2 深度
H1 高度
H2 高度
H3 高度
H4 高度
W1 宽度
W2 距离
W3 宽度
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了详细说明之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由权利要求定义。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所示出的取向外亦囊括元件在使用或操作中的不同取向。所述装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对关系描述语可同样相应地进行解释。
图1为依据本公开一种集成电路元件的制备方法100的一第一优选实施例的流程示意图。在一些实施例中，所述制备方法100是包括许多步骤(102、104、106、108以及110)，且下列的叙述与图示并不表示用来限制所述操作的顺序。
图2A至图2F为依据本公开该第一优选实施例的一种集成集成电路元件20的制备方法在不同阶段的剖视示意图。请参考图2，是显示依据一些实施例的一第一半导体元件200的一部分与一第二半导体元件300的一部分的剖视示意图。在步骤102中，提供在其上具有一第一导电部214的一第一半导体基底202。在一些实施例中，若第一导电部214由易于扩散的如铜的金属所制的话，则需要一扩散阻障层(diffusion barrier layer)216，以避免金属扩散。扩散阻障层216可由以下材料所制：氮化硅(silicon nitride，SiN)、氮氧化硅(silicon oxynitride，SiON)、氮化钛(titanium nitride，TiN)、氮化钽(tantalumnitride，TaN)，或是氮化铝(aluminum nitride，AlN)。在一些实施例中，第一导电部214由铜(copper)所制，且扩散阻障层216由Ti、TiN、Ta、TaN、Ta/TaN、COP或CoW所制。在一些实施例中，扩散阻障层216具有一厚度，在
Figure BDA0002411136440000081
到
Figure BDA0002411136440000082
的范围内。
可如图2A所示，为了接下来的制程第一半导体元件200与第二半导体元件300是相互面对配置。如图所示，第一半导体元件200具有第一元件区(first device region)210，并形成一金属化结构(metallization structure)以个别地连接到第一元件区210。第一元件区210与金属化结构的细节将于后说明。在一些实施例中，金属化结构具有一内连线结构(interconnect structure)，例如接触插塞(contact plugs)218与第一导电特征(firstconductive features)212。所述导电特征212内置(embedded)在一隔离材料(insulatingmaterial)206中。在一些实施例中，隔离材料206由氧化硅所制。在一些实施例中，隔离材料206具有介电材料(dielectric materials)的多个介电层(multiple dielectriclayers)。所述导电特征212连接到所述第一导电部214，以使所述第一元件区210亦电性连接到所述第一导电部214。第一导点部214可由导电材料所制，例如铜(Cu)、铜合金、铝(Al)、铝合金，或是其组合。其他应用的材料可被使用来形成第一导电部214。所示的金属化层仅用于图例说明。金属化结构可具有其他架构(configurations)，并具有一或多个导线(conductive lines)或通孔层(via layers)。
在一些实施例中，第一半导体基底202可依据所属技术领域所熟知的由硅或其他材料所制。举例来说，在一些实施例中，第一半导体基底202可具有其他元素半导体材料(elementary semiconductor materials)，例如锗(germanium)。在一些实施例中，第一半导体基底202由化合物半导体(compound semiconductor)所制，例如碳化硅(siliconcarbide)、砷化镓(gallium arsenic)、砷化铟(indium arsenide)或磷化铟(indiumphosphide)。在一些实施例中，第一半导体基底202由合金半导体(alloy semiconductor)所制，例如硅锗碳化物(silicon germanium)、硅锗碳化物(silicon germanium carbide)、砷化镓磷化物(gallium arsenic phosphide)或磷铟镓化物(gallium indiumphosphide)。在一些实施例中，第一半导体基底202具有一外延层(epitaxial layer)。举例来说，第一半导体基底202具有覆盖在一散装半导体(bulk semiconductor)上的一外延层。
在步骤104中，提供具有一第二导电部314的一第二半导体基底302。在一些实施例中，如图2A所示，第二半导体元件300类似于第一半导体元件200。第二半导体元件300具有第二半导体基底302、多个第二元件区310以及一金属化结构，金属化结构是形成来个别地连接到所述第二元件区310。第二元件区310与金属化结构的细节将于后详述。
在一些实施例中，金属化结构具有一内连线结构，例如接触插塞318与导电特征312。所述导电特征312内置在一隔离材料306中。在一些实施例中，隔离材料306由氧化硅所制。在一些实施例中，隔离材料306具有介电材料的多个介电层。所示的金属化层仅用于图例说明。金属化结构可具有其他架构，并具有一或多个导线或通孔层。在一些实施例中，金属化结构还可具有一扩散阻障层316，其是类似于扩散阻障层216。
第二半导体基底302类似于第一半导体基底202，也因此亦可由依据所述技术领域中所熟知的硅或其他半导体材料所制。在一些实施例中，第二半导体基底302具有一外延层。举例来说，第二半导体基底302具有覆盖在一散装半导体上的一外延层。
请参考图2B，是显示依据一些实施例的第一半导体元件200的一部分与第二半导体元件300的一部分的剖视示意图。在步骤106中，执行一第一化学反应(first chemicalreaction)201以在第一导电部214上形成一第一扩展垫(first expanding pad)215，并提供一第一扩展接触区(first expanded contact area)215A，举例来说，第一扩展接触区215A大于第一导电部214约10％。在一些实施例中，第一导电部214为铜，且第一化学反应201包括铜的锗化(germanidation)。为了达到铜的锗化，是使第一半导体基底202处于一预清洗温度(pre-clean temperature)，优选者，所述预清洗温度等于浸渍温度(soaktemperature)，且所述预清洗温度接续在一下降压力(declining pressure)中执行原位(in-situ)一等离子体辅助预清洗(plasma-assisted pre-clean)之后。锗化的结果即一锗化铜(copper germanide，Cu3Ge)合金，并形成第一扩展垫215。通过施行一原位等离子体辅助清洗(in-situ plasma-assisted clean)，暴露在锗前驱物(germanium precursor)之前，是移除出现在铜膜上的原生氧化铜(native copper oxide，CuO)，借此促进铜与锗烷气体(germane gas)之间的固汽反应(solid vapor reaction)。相较于一非原位(ex-situ)等离子体辅助清洗而言，许多比较研究已显示原位等离子体辅助清洗导致具有一正交晶体(orthorhombic crystalline)的铜的较佳锗化。在一些实施例中，在第一化学反应201之前，可执行一化学机械研磨(chemical mechanical polishing)制程。如图2B所示，第一导电部214的所述侧壁的至少一部分通过第一聚合物材料(first polymer material)208而暴露，以促进接下来的第一化学反应201。在一些实施例中，第一导电部214的所述侧壁的该暴露部分直接接触第一扩展垫215。
依据本公开的一些实施例，使用在第一化学反应201的锗前驱物可为锗烷(germane)，即GeH4，其是提供在现场的一载体气体(carrier gas)以引起一催化的化学气相反应(catalyzed chemical vapor reaction)。优选者，载体气体为氮气(N2)。锗前驱物(GeH4)的流动率(flow rate)可在PECVD(等离子体增强化学气相沉积)腔室中调整到所欲的部分压力，而PECVD腔室是锗化发生处。举例来说，在反应室(reactor)中锗前驱物的所述部分压力可在70到420mTorr。
再者，其是已发现浸渍时间(soak time)、锗前驱物(GeH4)的部分压力以及浸渍温度(亦代表锗化温度)是为相关变数(interrelated variables)，其是必须依据所选的金属膜厚度进行选择。在一些实施例中，对于铜(Cu)、镍(Ni)以及钴(Co)膜其中任何一个的浸渍温度，是维持在205℃到400℃的范围内。
在一些实施例中，在第一化学反应201中的锗化可以用类似制程取代。举例来说，前驱物可为甲烷(methane，CH4)或硅烷(silane，SiH4)，以分别获取铜碳簇(copper-carboncluster)或铜填充(copper fill)。由于使用上述前驱物的化学反应的原理类似，因此为了简洁起见，不再重复相对应制程的详细说明。
在步骤108中，执行一第二化学反应301以在第二导电部314上形成一第二扩展垫315，并提供一第二扩展接触区315A，举例来说，第二扩展接触区315A大于第二导电部314约10％。在一些实施例中，第二导电部314为铜，且第二化学反应301包括如上所述的铜的锗化。在一些实施例中，在第二化学反应301之前，可执行一化学机械研磨制程。如图2B所示，第二导电部314的所述侧壁的至少一部分通过第二聚合物材料308而暴露，以促进接下来的第二化学反应301。在一些实施例中，第二导电部314的所述侧壁的该暴露部分直接接触第二扩展垫315。
请参考图2C，是显示依据一些实施例的第一半导体元件200的一部分与第二半导体元件300的一部分的剖视示意图。在步骤110中，第一半导体元件200的第一半导体基底202是以一混合式接合结构(hybrid bonding structure)400接合到第二半导体元件300的第二半导体基底302，以使第一扩展接触区215A大致地直接接触第二扩展接触区315A。
如图2C所示，一第一接合结构220形成在第一半导体元件200的金属化层上。第一接合结构220具有第一导电部214与第一扩展垫215，第一导电部214内置在第一聚合物材料208中，第一扩展垫215内置在第二聚合物材料222中。举例来说，第一导电部214可为形成在第一半导体元件200的一顶表面上的一接触垫(或一接合垫)。在一些实施例中，第一聚合物材料208为苯并环丁烯(benzocyclobutene，BCB)聚合物、聚酰亚胺(polyimide，PI)或聚苯并恶唑(polybenzoxazole，PBO)。在一些实施例中，第二聚合物材料222为苯并环丁烯(BCB)聚合物所制，并通过旋涂(spin coating)使用在金属化结构。由于苯并环丁烯聚合物为柔性材料，所以相较于其他如二氧化硅的的介电材料，其可容许由在接下来的制程期间所形成的基底穿孔(TSV)所造成的更大的应力(stress)。
第二接合结构320类似于第一接合结构220，并具有第二导电部314以及第二扩展垫315，第二导电部314在第三聚合物材料308中，第二扩展垫315在第四聚合物材料322中。第二导电部314类似于第一导电部214，且第三与第四聚合物材料308与322分别地类似于第一与第二聚合物材料208与222。
在第一半导体元件200接合到第二半导体元件300之前，是对准第一与第二半导体元件200与300，以使在第一导电部214上的第一扩展垫215可接合到在第二导电部314上的第二扩展垫315，且在第一半导体元件200上的第二聚合物材料222可接合到在第二半导体元件300上的第四聚合物材料322。在一些实施例中，可通过使用一光学感测方法(opticalsensing method)来达到第一与第二半导体元件200与300的对准(alignment)。如图所示，由于第一与第二扩展垫215与315，其并不需要完美的对准，但仍可达到很好的接合结果(fine bonding result)。
请参考图2C，执行对准之后，通过混合式接合将第一与第二半导体元件200与300接合在一起，以形成一3DIC堆叠结构20(晶粒堆叠)。通过压力与热的应用将第一与第二半导体元件200与300混合式接合在一起。在一些实施例中，在混合式接合期间，在100℃到200℃温度范围内加热堆叠结构20，以使聚合物材料208、222、308、322变成非局限粘性液体(non-confined viscous liquid)并回焊(reflowed)。通过回焊聚合物材料208、222、308、322，以除去其内的孔隙(voids)。
接下来，在220℃到380℃的一更高温度的范围内进一步加热堆叠结构20，以通过热压接合(thermocompression bonding)使扩展垫215与315内连线(interconnected)，并使聚合物材料208、222、308、322完全地固化(cured)。在一些实施例中，对于混合式接合的压力是在0.7bar到10bar的范围内。混合式接合制程可在一惰性环境(inert environment)执行，例如填满有惰性气体的环境，惰性气体是如氮气(N2)、氩气(Ar)、氦气He)，或其组合。
如图2C所示，混合式接合包含至少二种接合，包括金属对金属(metal-to-metal)接合与非金属对非金属(metal-to-metal)接合。如图2C所示，混合式接合结构400形成在第一与第二半导体元件200与300之间。混合式接合结构400具有通过金属对金属接合的扩展垫215、315以及通过非金属对非金属接合的聚合物材料222、322。如图2C所示，混合式接合结构400具有在扩展垫215与315之间的一金属接合界面，但由于回焊制程，因此在聚合物材料222与322之间可不具有一明显的非金属界面(clear non-metallic interface)。
相较于包含其他介电层的混合式接合，第一与第二半导体元件200与300通过聚合物材料222与322而接合。由于聚合物材料222与322的接合包含聚合物222与322的回焊，因此除去在聚合物材料222与322中的孔隙(voids)，且改善第一与第二半导体元件200与300的接合强度(bonding strength)。
请参考图2D，是显示依据一些实施例的第一半导体元件200的一部分与第二半导体元件300的一部分的剖视示意图。如图所示，每一第一元件区210具有内置在一介电层204中的一栅极结构、一源极/漏极区211以及多个隔离结构213，隔离结构213是例如浅沟槽隔离(shallow trench isolation，STI)结构。栅极结构具有一栅极介电层207、一栅极电极209以及可选择间隙子(optional spacers)(图未示)。如图2D所示的所述第一元件区210仅为举例，且其他结构是可形成在所述元件区210。在一些实施例中，所述第一元件区210可形成不同N型金属氧化物半导体(NMOS)及/或P型金属氧化物半导体(PMOS)元件，例如晶体管或存储器，或其类似物，其是内连接以形成一或多个功能。例如电容器、电阻器、二极管、光电二极管(photo-diodes)、熔丝(fuses)或其类似物的其他元件，是可形成在基底202上。
如图2D所示，直通硅穿孔(through silicon vias，TSVs)500是提供在第一半导体基底202上，且金属化结构形成在直通硅穿孔500上，以个别地将所述直通硅穿孔500连接到所述元件区210。如图所示，所述直通硅穿孔500形成在二相邻元件区210之间，并延伸进入基底202。所述直通硅穿孔500被用来提供电性连接与针对3DICs的散热(heatdissipation)。虽然图2D显示三个直通硅穿孔，但可依据实际应用调整直通硅穿孔的数量。
如图2D所示，依据一些实施例，每一直通硅穿孔500具有一衬垫(liner)502、一扩散阻障层(diffusion barrier layer)504以及一导电材料506。在一些实施例中，衬垫502由一隔离材料所制，例如氧化物或氮化物。可使用等离子体加强化学气相沉积(PECVD)制程或其他应用制程来形成衬垫502。衬垫502可为单一层或多层。在一些实施例中，衬垫502具有一厚度，是在
Figure BDA0002411136440000141
到
Figure BDA0002411136440000142
的范围内。
在一些实施例中，扩散阻障层504由Ta、TaN、Ti、TiN或CoW所制。在一些实施例中，扩散阻障层504由物理气相沉积(PVD)制程所形成。在一些实施例中，导电材料506由铜、铜合金、铝、铝合金，或其组合所制。或者是，可使用其他应用材料。在一些实施例，导电材料506由镀覆(plating)所形成。
由于高深宽比(high aspect ratios)，将材料填充到直通硅穿孔(TSV)的开口(opening)变得有挑战性。孔隙可形成在一直通硅穿孔的开口中。此外，由于衬垫502或是扩散阻障层504的不全面的侧壁覆盖，会发生与导电材料506相关的一些挤出(extrusion)或扩散问题。反之，如图2D所示，所述直通硅穿孔500被设计成具有一深度D1，是小于第一半导体元件200的一高度H1。因此，可解决或大幅地减少孔隙问题以及与导电材料506相关的挤出或扩散问题。此外，所述直通硅穿孔500的一宽度W1是沿着所述直通硅穿孔500的深度D1的减少而缩减。当一距离W2更小时，是进一步改善在所述元件区210中的所述元件的集成密度(integrated density)。
在一些实施例中，第一半导体元件200具有一高度H1，约在1μm到20μm的范围内，高度H1是从第一半导体基底202的一底表面到栅极结构的一顶表面。在一些实施例中，所述直通硅穿孔(TSVs)500具有一宽度W1，约在0.025μm到2μm的范围内。在一些实施例中，TSVs500具有一深度D1，约在0.2μm到10μm的范围内。在一些实施例中，TSVs 500具有一深宽比(D1/W1)，约在2到15的范围内。此外，由于由TSV所产生的应力(stress)，在TSV附近的元件(devices)遭受到严重的性能退化(performance degradation)。一排除区域(keep-outzone，KOZ)被使用来界定可无置放元件的一区域。在一些实施例中，排除区域被界定为一距离W2，其是从TSV500的一侧壁测量到最靠近的栅极结构。由于缩减TSVs 500的深度D1，是达到一较小的宽度W1。因此，减少由TSVs 500所产生的所有应力。在一些实施例中，距离W2在0.01μm到3μm的范围内。在一些实施例中，当TSVs500的宽度W1缩减到2μm至3μm的范围内时，可因此几乎忽略由TSV所产生的应力。
类似地，如图2D所示，第二半导体元件300类似于第一半导体元件200。第二半导体元件300具有一第二半导体基底302以及多个第二元件区310。第二半导体基底302类似于第一半导体基底202。所述第二元件区310类似于所述第一元件区210，并具有一栅极结构、源极/漏极区311以及多个隔离结构313。第二元件区310的栅极结构类似于第一元件区210的栅极结构，并具有一栅极介电层307、一栅极电极309以及多个可选择的间隙子(图未示)。栅极介电层307类似于栅极介电层207，且栅极电极309类似于栅极电极209。此外，在所述第二元件区310中的源极/漏极区311类似于在所述第一元件区210中的源极/漏极区211，且在所述第二元件区310中的所述隔离结构313类似于在所述第一元件区210中的所述隔离结构213。
请参考图2E，是显示依据一些实施例的第一半导体元件200的一部分与第二半导体元件300的一部分的剖视示意图。如图所示，在混合式接合之后，堆叠结构20放在一胶带(tape)(图未示)上，并在第一半导体元件200的一底表面上执行一薄化制程(thinningprocess)203。在薄化制程203之后，暴露TSVs 500。薄化制程203可包括一磨削(grinding)操作以及一研磨(polishing)操作(例如一化学机械研磨(CMP))。薄化制程203之后，执行一湿蚀刻操作，以移除形成在第一半导体元件200的底表面上的所述缺陷(defects)。在一些实施例中，通过薄化制程203移除扩散阻障层504的一底部，以暴露导电材料506。因此，薄化制程203之后，一高度H2小于深度D1。在一些实施例中，TSVs 500具有一深宽比(H2/W2)在2到15的范围内。在一些实施例中，高度H2等于深度D1。薄化制程203之后，第一半导体元件200具有一高度H2，是从第一半导体基底202的底表面到栅极结构的一顶表面，且在0.2μm到10μm的范围内。高度H2小于高度H1。在一些实施例中，高度H2约在高度H1的1％到99％的范围内。
理应注意的是，若是在第一与第二半导体元件200与300接合的前执行薄化制程203的话，则在接下来的制程期间，薄的第一半导体元件200可轻易地断裂(break)。然而，若是第一与第二半导体元件200与300先接合的话，如图2E所示，则如此的接合能使第一半导体元件200薄化。结果，相较于在接合之前直接薄化的第一半导体元件200，此第一半导体元件200可被薄化到一相对较小的高度H2。
请参考图2F，是显示依据一些实施例的第一半导体元件200的一部分与第二半导体元件300的一部分的剖视示意图。如图所示，一内连线结构(interconnect structure)600形成在第一半导体元件200的底表面上。内连线结构600通过TSVs500电性连接在第一半导体基底202上的所述导电特征212。内连线结构600具有形成在一隔离材料620中的多个导电特征610，例如导线(conductive lines)、穿孔(vias)或导电垫(conductive pads)。如图2F所示的所述导电特征的金属配线(metal routing)是仅为一个例子。或者是，可依据实际应用使用所述导电特征的其他金属配线。
内连线结构600形成之后，一或多个重分布层(redistribution layers，RDLs)(图未示)可形成在内连线结构600上。举例来说，重分布层内置在一钝化层(passivationlayer)中。一内连线结构600、所述重分布层以及TSVs500是提供电性连接。此外，TSVs 500具有一相对低的电阻值，且减少电阻电容延迟(RC delay)。此外，可在3DIC堆叠结构20上亦可执行其他制程，且3DIC堆叠结构20可接下来被切割(diced)成多个个别芯片(chips)。
图3为依据本公开一种集成电路元件的制备方法700的一第二优选实施例的流程示意图。在一些实施例中，所述制备方法700是包括许多步骤(702、704、706、708以及710)，且下列的叙述与图示并不表示用来限制所述操作的顺序。步骤702与704大致地等同于上述的步骤102与104。在步骤702中，提供其上具有一第一导电部214的一第一半导体基底202。在步骤704中，提供其上具有一第二导电部314的一第二半导体基底302。
图4A至图4E为依据本公开该第二优选实施例的一种集成电路元件40的制备方法在不同阶段的剖视示意图。请参考图4A，是显示依据一些实施例的第一半导体元件200的一部分与第二半导体元件300的一部分的剖视示意图。在步骤706中，执行一第一镀覆(plating)制程205，以在第一导电部214上形成一第一扩展垫215，并提供一第一扩展接触区215A，举例来说，其是可大于第一导电部214约10％。在一些实施例中，在第一镀覆制程205之前，可执行一化学机械研磨制程。如图4A所示，第一导电部214的所述侧壁的至少一部分，是通过第一半导体基底202而暴露，以帮助接下来的镀覆制程。
在步骤708中，执行一第二镀覆制程305，以在第二导电部314上形成一第二扩展垫315，并提供一第二扩展接触区315A，举例来说，其是可大于第二导电部314约10％。在一些实施例中，在第二化学反应301之前，可执行一化学机械研磨制程。如图4A所示，第二导电部314的所述侧壁的至少一部分，是通过第二半导体基底302而暴露，以帮助接下来的镀覆制程。
请参考图4B，是显示依据一些实施例的第一半导体元件200的一部分与第二半导体元件300’的一部分的剖视示意图。在步骤710中，第一半导体元件200的第一半导体基底202以一混合式接合结构400接合到第二半导体元件300的第二半导体基底302。如图所示，通过接合第一与第二半导体元件200与300’，以形成一3DIC堆叠结构40。如图4B所示，第二半导体元件300’几乎相同于第二半导体元件300，除了TSVs 800形成在第二半导体元件300’中之外。在一些实施例中，TSVs 500具有一直径，是不同于TSVs 800。在一些实施例中，TSVs 800的形成是包括额外的图案化(patterning)与蚀刻制程。在一些实施例中，TSVs500的一数量大于TSVs 800。在一些其他实施例中，TSVs 500的一数量小于TSVs 800。
如图4B所示，每一TSV 800具有类似于衬垫502的一衬垫802、类似于扩散阻障层504的一扩散阻障层804，以及类似于导电材料506的一导电材料806。TSVs 800延伸到第二半导体元件300’的一金属垫312。因为第二半导体元件300’是后来薄化以暴露TSVs 800，所以TSVs 800并未延伸穿过第二半导体元件300’的整个基底302。因此，TSVs 800设计成具有一深度D2，其是小于第二半导体元件300’的一原始高度H3。
在一些实施例中，第二半导体元件300’具有一高度H3，是从第二半导体基底302的一底表面到栅极结构的一顶表面，其是在17μm到100μm的范围内。在一些实施例中，TSVs800具有一宽度W3，是在0.3μm到10μm的范围内。在一些实施例中，TSVs 800具有一深度D2，是在15μm到100μm范围内。在一些实施例中，TSVs 800具有一深宽比(D2/W3)，是在5到15的范围内。在一些实施例中，深度D1相同于深度D2。在一些其他实施例中，深度D1不同于深度D2。
请参考图4C，是显示依据一些实施例的第一半导体元件200的一部分与第二半导体元件300’的一部分的剖视示意图。如图所示，薄化第一半导体元件200至一高度H2，且一内连线结构600’形成在第一半导体元件200的一底表面上。内连线结构600’类似于如图2F中的内连线结构600，为了简洁起见，不再重复内连线结构600’的详细叙述。
请参考图4D，内连线结构600形成之后，堆叠结构40放在一胶带(tape)(图未示)上，并在第二半导体元件300’的一底表面上执行一薄化制程203。在薄化制程203之后，暴露TSVs 800。薄化制程203是如上所述，为了简洁起见，不再重复叙述。薄化制程203之后，第二半导体元件300’具有一高度H4，是从第二半导体基底302的底表面到栅极结构的一顶表面，并在15μm到100μm的范围内。高度H4是小于高度H3。在一些实施例中，高度H4等于或小于深度D2。
请参考图4E，一重分布结构350形成在第二半导体基底302的一底表面上。重分布结构350具有形成在一钝化层354中的一金属垫352。金属垫352电性连接暴露的TSVs 800。金属垫352由具有低电阻率(low resistivity)的导电材料所制，例如铜、铝、铜合金、铝合金，或其他可应用的材料。虽然图4E仅显示一个重分布结构350，但依据需求可形成一个以上的重分布结构。
如图所示，一凸块下金属化(under bump metallization，UBM)层358形成在金属垫352上，且一导电组件(conductive component)356(例如一锡球(solder ball))形成在UBM层358上。UBM层358可包含一粘着层(adhesion layer)及/或一润湿层(wettinglayer)。在一些实施例中，UBM层358由钛(Ti)、氮化钛(TiN)、氮化钽(TaN)、钽(Ta)或其类似物所制。在一些实施例中，UBM层358还包括一铜晶种层(copper seed layer)。在一些实施例中，导电组件356是由具有低电阻率的导电材料所制，例如焊料(solder)或焊料合金。包含在焊料合金中的举例的零组件(elements)是含有锡(Sn)、铅(Pb)、银(Ag)、铜(Cu)、镍(Ni)、铋(Bi)，或是其组合。
在一些实施例中，内连线结构600’通过TSVs 800、重分布结构350以及导电组件356电性连接第二半导体元件300’的后侧(backside)上的其他封装(package)(图未示)。TSVs 500与800个别地执行不同功能。第一半导体元件200通过内连线结构600’与TSVs 500电性连接另一封装结构(图未示)。第二半导体元件300’通过内连线结构600’与TSVs 800电性连接另一封装结构(图未示)。TSVs 500与800提供一快速导电路径，以连接第一半导体元件200、第二半导体元件300及/或其他封装结构，而没有形成复杂的金属配线(metalroutings)。
由于上述集成电路元件的架构及其制备方法，二基底的导电部均具有各自的扩展垫，以便增加接触区。因此，可以减轻由拙劣的对准所造成的导电性(conductivity)问题。
本公开的一实施例提供一种在一集成电路元件。该集成电路元件包括一第一基底、一第二基底、一第一扩展垫、一第二扩展垫以及一接合结构。在一些实施例中，该第一基底提供有一第一导电部。在一些实施例中，该第二基底提供有一第二导电部。在一些实施例中，该第一扩展垫形成在该第一导电部上，以提供一第一扩展接触区。在一些实施例中，该第二扩展垫形成在该第二导电部上，以提供一第二扩展接触区。在一些实施例中，该接合结构形成在该第一基底与该第二基底之间，其中该第一扩展垫接合该第二扩展垫。
在本公开的另一实施例中提供一种集成电路元件的制备方法。该制备方法包括提供一第一基底，该第一基底具有一第一导电部；提供一第二基底，该第二基底具有一第二导电部；执行一第一化学反应以在该第一导电部上形成一第一扩展垫，并提供一第一扩展接触区；执行一第二化学反应以在该第二导电部上形成一第二扩展垫，并提供一第二扩展接触区；以及以一接合结构将该第一基底接合到该第二基底。
在本公开的另一实施例中提供一种集成电路元件的制备方法。该制备方法包括提供一第一基底，该第一基底具有一第一导电部；提供一第二基底，该第二基底具有一第二导电部；执行一第一镀覆制程(first plating process)以在该第一导电部上形成一第一扩展垫，并提供一第一扩展接触区；执行一第二镀覆制程以在该第二导电部上形成一第二扩展垫，并提供一第二扩展接触区；以及以一接合结构将该第一基底接合到该第二基底。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的精神与范围。例如，可用不同的方法实施上述的许多制程，并且以其他制程或其组合替代上述的许多制程。
再者，本公开的范围并不受限于说明书中所述的制程、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的制程、机械、制造、物质组成物、手段、方法、或步骤。据此，这些制程、机械、制造、物质组成物、手段、方法、或步骤是包含于本公开的权利要求内。

Claims (19)

1.一种集成电路元件，包括：
一第一基底，提供有一第一扩散阻障层和由该第一扩散阻障层所包围的一第一导电部；
一第二基底，提供有一第二扩散阻障层和由该第二扩散阻障层所包围的一第二导电部；
一第一扩展垫，形成在该第一导电部上，以提供一第一扩展接触区；
一第二扩展垫，形成在该第二导电部上，以提供一第二扩展接触区；
一接合结构，形成在该第一基底与该第二基底之间，其中该第一扩展垫接合该第二扩展垫，
一第一聚合物材料，包围该第一扩散阻障层，其中该第一导电部的至少一部分暴露通过该第一聚合物材料，并且该第一导电部的该部分直接接触该第一扩展垫；以及
一第二聚合物材料，包围该第二扩散阻障层，其中该第二导电部的至少一部分暴露通过该第二聚合物材料，并且该第二导电部的该部分直接接触该第二扩展垫；
其中该第一扩展垫与该第二扩展垫由以下至少其中之一所形成：锗化铜、铜填充以及铜碳簇。
2.如权利要求1所述的集成电路元件，其中，该第一扩展垫大致地对准该第二扩展垫。
3.如权利要求2所述的集成电路元件，其中，该第一导电部与该第二导电部由铜所形成。
4.如权利要求2所述的集成电路元件，其中，该第一扩展垫与该第二扩展垫分别地围绕该第一导电部与该第二导电部设置。
5.如权利要求4所述的集成电路元件，其中，该第一导电部的一侧壁的一部分直接接触该第一扩展垫，该第二导电部的一侧壁的一部分直接接触该第二扩展垫。
6.如权利要求1所述的集成电路元件，其中，该第一导电部与该第二导电部由铜所形成，该第一扩展垫与该第二扩展垫通过将导电材料镀覆在该第一导电部与该第二导电部周围所形成。
7.如权利要求1所述的集成电路元件，还包括一第一基底穿孔以及一内连线结构，该第一基底穿孔形成在该第一基底中，该内连线结构形成在该第一基底穿孔上，其中该第一基底穿孔位在该内连线结构与该接合结构之间。
8.一种集成电路元件的制备方法，包括：
提供一第一基底，该第一基底具有一第一扩散阻障层和由该第一扩散阻障层所包围的一第一导电部；
提供一第二基底，该第二基底具有一第二扩散阻障层和由该第二扩散阻障层所包围的一第二导电部；
执行一第一化学反应以在该第一导电部上形成一第一扩展垫，并提供一第一扩展接触区；
执行一第二化学反应以在该第二导电部上形成一第二扩展垫，并提供一第二扩展接触区；以及
以一接合结构将该第一基底接合到该第二基底，
其中，该第一化学反应具有用锗烷与铜产生反应以获取锗化铜、用硅烷与铜产生反应以获取铜填充，或是用甲烷与铜产生反应以获取铜碳簇，
其中，该第一扩散阻障层由一第一聚合物材料包围，其中该第一导电部的至少一部分暴露通过该第一聚合物材料，并且该第一导电部的该部分直接接触该第一扩展垫；以及
该第二扩散阻障层由一第二聚合物材料包围，其中该第二导电部的至少一部分暴露通过该第二聚合物材料，并且该第二导电部的该部分直接接触该第二扩展垫。
9.如权利要求8所述的集成电路元件的制备方法，还包括对准该第一扩展垫与该第二扩展垫。
10.如权利要求9所述的集成电路元件的制备方法，其中，该第一导电部含有铜。
11.如权利要求10所述的集成电路元件的制备方法，还包括在执行该第一化学反应之前，执行一化学机械研磨制程，以暴露该第一导电部的一侧壁通过该第一基底的至少一部分。
12.如权利要求9所述的集成电路元件的制备方法，其中，该第一扩展垫接合到该第二扩展垫，以使该第一扩展接触区大致地直接接触该第二扩展接触区。
13.如权利要求8所述的集成电路元件的制备方法，还包括在该第一基底中形成一第一基底穿孔以及在该第一基底穿孔上形成一内连线结构。
14.如权利要求13所述的集成电路元件的制备方法，其中，该第一基底穿孔位在该内连线结构与该接合结构之间。
15.一种集成电路元件的制备方法，包括：
提供一第一基底，该第一基底具有一第一扩散阻障层和由该第一扩散阻障层所包围的一第一导电部；
提供一第二基底，该第二基底具有一第二扩散阻障层和由该第二扩散阻障层所包围的一第二导电部；
执行一第一镀覆制程以在该第一导电部上形成一第一扩展垫，并提供一第一扩展接触区；
执行一第二镀覆制程以在该第二导电部上形成一第二扩展垫，并提供一第二扩展接触区；以及
以一接合结构将该第一基底接合到该第二基底，其中
在进行该第一镀覆制程之前，执行一第一化学机械研磨制程，使该第一导电部的侧壁的至少一部分通过该第一基底而暴露，
在进行该第二镀覆制程之前，执行一第二化学机械研磨制程，使该第二导电部的侧壁的至少一部分通过该第二基底而暴露，并且
该第一扩展垫覆盖该第一导电部的侧壁的至少该部分，该第二扩展垫覆盖该第二导电部的侧壁的至少该部分，
其中，该第一扩散阻障层由一第一聚合物材料包围，其中该第一导电部的至少一部分暴露通过该第一聚合物材料，并且该第一导电部的该部分直接接触该第一扩展垫；以及
该第二扩散阻障层由一第二聚合物材料包围，其中该第二导电部的至少一部分暴露通过该第二聚合物材料，并且该第二导电部的该部分直接接触该第二扩展垫。
16.如权利要求15所述的集成电路元件的制备方法，其中，该第一导电部由铜所制，且该第一扩展垫为镀覆在该铜上的镍。
17.如权利要求16所述的集成电路元件的制备方法，还包括对准该第一扩展垫与该第二扩展垫。
18.如权利要求17所述的集成电路元件的制备方法，其中，该第一扩展垫接合到该第二扩展垫，以使该第一扩展接触区大致地直接接触该第二扩展接触区。
19.如权利要求15所述的集成电路元件的制备方法，还包括在该第一基底中形成一第一基底穿孔以及在该第一基底穿孔上形成一内连线结构，其中该第一基底穿孔位在该内连线结构与该接合结构之间。
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