CN111293100B - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN111293100B
CN111293100B CN201910375561.2A CN201910375561A CN111293100B CN 111293100 B CN111293100 B CN 111293100B CN 201910375561 A CN201910375561 A CN 201910375561A CN 111293100 B CN111293100 B CN 111293100B
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dielectric material
substrate
conductive pad
wafer
height
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CN111293100A (zh
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苏国辉
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种半导体元件及其制造方法。该半导体元件包括：一第一基板、一基板通孔、一第二基板，以及一接合结构。该第一基板包括一第一介电材料，该第一介电材料包括设置在其中的一第一导电垫。该基板通孔形成在该第一基板中。该第二基板包括一第二介电材料，该第二介电材料包括嵌入其中的一第二导电垫，该第一介电材料与该第二介电材料不同，该第二导电垫具有一第一高度，该第二介电材料具有一第二高度，该第一高度小于该第二高度。该接合结构形成在该第一基板和该第二基板之间，其中该接合结构包括接合到该第二导电垫的该第一导电垫和接合到该第二介电材料的该第一介电材料。

Description

半导体元件及其制造方法
相关申请的交叉引用
本公开主张2018/12/07申请的美国临时申请案第62/776,516号及2019/02/22申请的美国正式申请案第16/283,081号的优先权及益处，该美国临时申请案及该美国正式申请案的内容以全文引用的方式并入本文中。
技术领域
本公开提供一种半导体元件及其制造方法，特别涉及利用不同接合技术的一种半导体元件及其制造方法。
背景技术
半导体元件使用于各种电子的应用，例如个人电脑、手机和其他类型的电子装置。半导体工业经过不断减小最小特征尺寸以继续改善各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，使得更多元件可整合到给定的区域中。这些较小的电子元件需要较小的封装，在一些应用中，这些封装使用的面积小于现有技术中封装所需的面积。
三维集成集成电路(3DIC)是半导体封装的最新发展，其中多个多个半导体晶粒彼此堆叠，例如封装上封装(package-on-package，PoP)和系统级封装(system-in-package，SiP)封装技术。一些3DIC是通过将晶粒放置在半导体晶圆上的晶粒的上方来制备。由于堆叠晶粒之间的互连长度减小，这种3DIC提供了改进的集成密度和其他的优点，例如更快的速度和更大的频宽。但是，3DIC仍存在许多的挑战。
上文的“现有技术”说明仅是提供背景技术，并未承认上文的“现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开提供一种半导体元件，包括：一第一基板、一基板通孔、一第二基板，以及一接合结构。该第一基板包括一第一介电材料，该第一介电材料包括设置在其中的一第一导电垫。该基板通孔形成在该第一基板中。该第二基板，包括一第二介电材料，该第二介电材料包括嵌入其中的一第二导电垫，其中该第一介电材料与该第二介电材料不同，该第二导电垫具有一第一高度，该第二介电材料具有一第二高度，该第一高度小于该第二高度。该接合结构形成在该第一基板和该第二基板之间，其中该接合结构包括接合到该第二导电垫的该第一导电垫和接合到该第二介电材料的该第一介电材料。
在一些实施例中，该第一介电材料和该第二介电材料中的一个由一材料在一接合工艺期间膨胀制成，并且该第一介电材料和第二介电材料中的另一个由一材料在接合工艺期间收缩制成。
在一些实施例中，该半导体元件还包括一接触结构，形成在该第一基板的上方，其中该接触结构形成在该基板通孔和该第一介电材料之间。
在一些实施例中，该半导体元件还包括一晶体管及一接触插塞。该晶体管形成在该第一基板的上方。该接触插塞形成在该晶体管的上方，其中该接触结构耦合到该基板通孔和该接触插塞。
在一些实施例中，该半导体元件还包括：一扩散阻挡层以及一接触结构。该扩散阻挡层形成在该第一介电材料内。该接触结构形成在该第一基板的上方，该接触结构形成在该基板通孔和该扩散阻挡层之间。
本公开另提供一种半导体元件，包括：一第一基板、一基板通孔、一第二基板，以及一接合结构。该第一基板包括第一介电材料，该第一介电材料包括设置在其中的第一凹陷图案，该第一介电材料包括一第一导电垫；该基板通孔形成在该第一基板中。该第二基板包括一第二介电材料，该第二介电材料包括一第二导电垫。该接合结构形成在该第一基板和该第二基板之间，其中该接合结构包括接合到该第二导电垫的该第一导电垫和接合到该第二介电材料的该第一介电材料。
在一些实施例中，该第二介电材料包括设置在其中的一第二凹陷图案。
在一些实施例中，该第一凹陷图案包括多个第一凹陷特征，该多个第一凹陷特征彼此电隔离并且与该第一导电垫电隔离。该第二凹陷图案包括多个第二凹陷特征，该多个第二凹陷特征彼此电隔离并且与该第二导电垫电隔离。
在一些实施例中，该第一凹陷结构中的至少一个或该第二凹陷结构中的至少一个包括对应于具有至少三个侧面的圆形或多边形的横截面形状。
在一些实施例中，该第一凹陷图案的一金属表面积相对于该第一凹陷图案的一总表面积的百分比大于50％，并且该第二凹陷图案的一金属表面积相对于第二凹陷图案的总表面积的百分比大于50％。
在一些实施例中，该半导体元件还包括一接触结构，形成在该第一基板的上方，其中该接触结构形成在该基板通孔和该第一介电材料之间。
在一些实施例中，该半导体元件还包括一晶体管及一接触插塞。该晶体管形成在该第一基板的上方。该接触插塞形成在该第一晶体管的上方，该接触结构耦合到该基板通孔和该第一接触插塞。
在一些实施例中，该第一介电材料和该第二介电材料由聚酰亚胺(polyimid)、聚苯并恶唑(polybenzoxazole)或苯并环丁烯(benzocyclobutene)化合物制成。
在一些实施例中，该半导体元件还包括：一扩散阻挡层以及一接触结构。该扩散阻挡层形成在该第一介电材料内。该接触结构形成在该基板通孔和该扩散阻挡层之间。
本公开另提供一种半导体元件的制造方法，包括：提供一第一晶圆和一第二晶圆，其中在该第一晶圆中形成一基板通孔。在该第一晶圆片中形成一第一介电材料。在该第一介电材料中形成一第一导电垫。在该第二晶圆中形成一第二介电材料。在该第二介电材料中形成一第二导电垫。接合该第一晶圆和该第二晶圆。
在一些实施例中，接合该第一晶圆和该第二晶圆还包括：将该第一晶圆的该第一介电材料接合到该第二晶圆的该第二介电材料，并且将设置在该第一介电材料中的该第一导电垫接合到设置在该第二介电材料中的该第二导电垫。
在一些实施例中，该第二介电材料中的该第二导电垫具有一第一高度，该第二介电材料具有第二高度，该第一高度小于该第二高度。
在一些实施例中，该制造方法还包括：在该第一介电材料中形成一第一凹陷图案；以及在该第二介电材料中形成一第二凹陷图案。
在一些实施例中，该第一凹陷图案的一金属表面积相对于该第一凹陷图案的一总表面积的百分比大于50％，并且该第二凹陷图案的一金属表面积相对于第二凹陷图案的总表面积的百分比大于50％。
在一些实施例中，该制造方法还包括：在该第一晶圆中形成一晶体管，其中该晶体管电耦合到该第一晶圆中的一接触结构。
由于接合结构和介电材料的设计，本公开的实施例的半导体元件和制造方法增强了粘附和接合的强度，并且更减少了在制造过程中引起的应力。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离权利要求所界定的本公开的构思和范围。
附图说明
参阅实施方式与权利要求合并考量附图时，可得以更全面了解本公开的公开内容，附图中相同的元件符号是指相同的元件。
图1A至图1C是剖视图，例示本公开一些实施例的半导体元件的形成。
图2和图3是剖视图，例示本公开一些实施例的半导体元件的形成。
图4是流程图，例示本公开一些实施例的半导体元件的制造方法。
附图标记列表
10 第一晶圆
10' 第一晶圆
14 第一基板
20 第二晶圆
20' 晶圆
24 第二晶圆
27 介电层
40 第一凹陷图案
40F 第一凹陷特征
50 接合结构
50a 金属接合界面
60 第二凹陷图案
60F 第二凹陷特征
100 堆叠结构
123 元件区
126 栅极介电层
128 栅极电极
129 栅极结构
130 源极与漏极区
132 隔离结构
134 接触插塞
142 接触结构
144 导电特征
146 绝缘材料
162 接合结构
163 扩散阻挡层
164 第一导电垫
166 介电材料
223 元件区
226 栅极介电层
228 栅极电极
229 栅极结构
230 源极与漏极区
232 隔离结构
234 接触插塞
242 接触结构
244 导电特征
246 绝缘材料
262 接合结构
263 扩散阻挡层
264 第二导电垫
266 第二介电材料
300 基板通孔
310 衬垫
320 扩散阻挡层
330 导电材料
AG 空隙
H1 第一高度
H2 第二高度
S110 步骤
S120 步骤
S130 步骤
S140 步骤
S150 步骤
S160 步骤
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了实施方式之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于实施方式的内容，而是由权利要求定义。
图1A至图1C是例示本公开一些实施例的半导体元件的形成的流程图。图1A描绘了第一晶圆10的一部分和第二晶圆20的一部分的剖视图。第一晶圆10包括第一基板14，其可以由硅或其他半导体材料制成。此外或可替代地，第一基板14可以包括其他半导体材料，例如锗。在一些实施例中，第一基板14可以由合金半导体制成，例如硅锗、碳化硅锗、磷化镓砷或磷化镓铟。在一些实施例中，半导体基板14可以是由诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体制成的。在一些实施例中，例如，第一基板14可以包括外延层，例如覆盖体半导体(bulk semiconductor)的外延层。
参照图1A，在一些实施例中，元件区123在前端(front-end of line，FEOL)工艺中形成在第一基板14中。每个元件区123包括设置在介电层17中的栅极结构129、源极与漏极区130和隔离结构132，例如浅沟槽隔离结构。栅极结构129包括栅极介电层126和栅极电极128，并且还可以包括间隙子(未示出)。元件区123可以形成各种P型金属氧化物半导体(P-type metal-oxide semiconductor，PMOS)和/或N型金属氧化物半导体(N-type metal-oxide semiconductor，NMOS)元件，例如晶体管，它们可以互连以执行各种功能。但是，图1A中描绘的元件区域123仅仅是说明性的，本公开不限于此。可以在基板14的上方形成其他结构和元件，例如二极管、光电二极管、电阻器、电容器、存储存储器和熔丝。
参照图1A，在两个相邻元件区123之间形成基板通孔300，基板通孔300延伸到基板14中。基板通孔300可用于在例如3DIC的半导体元件中提供电连接和散热，例如。尽管在图1A中描绘了三个基板通孔300，但可以根据实际应用调整数量。在一些实施例中，每个基板通孔300包括衬垫310、扩散阻挡层320和导电材料330。衬垫310可以由绝缘材料制成，例如氧化物或氮化物。衬垫310可以使用等电增强化学气相沉积(PECVD)工艺或其他适用的工艺来形成。衬垫310可以是单层或多层。在一些实施例中，衬垫310的厚度在约100埃
Figure GDA0003094207240000071
至约5000埃的范围内。
在一些实施例中，扩散阻挡层320由Ta、TaN、Ti、TiN或CoW制成。扩散阻挡层320可以通过物理气相沉积(PVD)工艺形成。导电材料330由铜(Cu)、铜合金、铝(Al)、铝合金或其组合制成。但是，也可以使用其他适用的材料。在一些实施例中，导电材料330通过电镀形成。与第一晶圆10的尺寸相比，通过最小化基板通孔300的尺寸，可以减小由基板通孔300引起的应力。
参照图1A，在基板通孔300和元件区域123的上方形成接触结构142，以单独地连接到基板通孔300和元件区域123。在一些实施例中，接触结构142包括接触插塞134和导电特征144。接触插塞134嵌入在介电层17中，导电特征144嵌入在绝缘材料146中。在一些实施例中，绝缘材料146由氧化硅制成。在一些实施例中，绝缘材料146包括多个介电材料介电层。所示的接触结构142仅是说明性例示。在其他实施例中，接触结构142可以包括其他配置，并且可以包括一个或多个导电线和通孔层。
如图1A所示，第一基板14包括第一介电材料166，第一介电材料166包括嵌入其中的第一导电垫164。在接触结构142的上方形成接合结构162，其中接合结构162包括第一介电材料166和第一导电垫164。第一导电垫164可以是形成在第一晶圆10一顶表面上的接合垫(或接触垫)导电特征144连接到第一导电垫164。第一导电垫164可以由导电材料制成，例如铜(Cu)、铜合金、铝(Al)、铝合金或其组合。其他适用的材料也可以用于第一导电垫164。
在一些实施例中，如果第一导电垫164由例如铜的金属制成，则在第一介电材料166中添加扩散阻挡层163，如图1A所示。扩散阻挡层163可以由氮化硅(SiN)、氮氧化硅(SiON)、氮化铝(AlN)、氮化钛(TiN)或氮化钽(TaN)制成。在一些实施例中，第一导电垫164由铜制成，扩散阻挡层163由Ti、TiN、Ta、TaN、Ta/TaN、CoP或CoW制成。在一些实施例中，扩散阻挡层163的厚度在约5埃至约1000埃的范围内。
参照图1A，第二晶圆20包括第二基板24和元件区域223。元件区域223类似于元件区域123并且包括栅极结构229，源极与漏极区域230和隔离结构232。栅极结构229是类似于栅极结构129，并且包括栅极介电层226、栅极228和可能的间隙子(未示出)。栅极介电层226类似于栅极介电层126，并与门极228类似于栅极128。此外，元件区域223中的源极与漏极区域230类似于源极与漏极区域130，元件区223中的隔离结构232类似于隔离结构132。
如图1A所示，第二晶圆24包括第二介电材料266，第二介电材料266包括嵌入其中的第二导电垫264。第二晶圆24还包括接触结构242和接合结构262。接合结构262形成在接触结构242的上方，接合结构262包括第二介电材料266和第二导电垫264。第二导电垫264可以是形成在第二晶圆20的一顶表面上的接合垫(或接触垫)。导电特征244连接到第二导电垫264。接触结构242类似于接触结构142并且包括嵌入在介电层27中的接触插塞234和嵌入在绝缘材料246中的导电特征244。接触插塞234类似于接触插塞134，并且介电层27类似于介电层17。导电特征244类似于导电特征144，绝缘材料246类似于绝缘材料146。如果第二导电垫264由金属制成，则也可以添加扩散阻挡层263。
在一些实施例中，第一介电材料166与第二介电材料266不同。第一介电材料166和第二介电材料266中的一个由在接合工艺期间膨胀的材料制成，而另一个第一介电材料166和第二介电材料266的材料由在接合过程中收缩的材料制成。这些材料可以是苯并环丁烯(BCB)聚合物、聚酰亚胺(PI)、聚苯并恶唑(PBO)、他们的组合或其他合适的材料，可以选择这些材料以减少由基板通孔300引起的应力。在一些实施例中，第二导电垫264具有第一高度H1，第二介电材料266具有第二高度H2，如图1A所示。在一些实施例中，形成第一介电材料166和第二介电材料266并通过旋涂施加到接触结构142和242。例如，第二介电材料266可以旋涂以具有第二高度H2，其中第二导电垫264的第一高度H1小于第二介电材料266的第二高度H2。
在将第一晶圆10接合到第二晶圆20之前，将晶圆10和20对准，使得第一晶圆10上的第一导电垫164可以接合到第二晶圆20上的第二导电垫264。第一晶圆10上的第一介电材料166可以接合到第二晶圆20上的第二介电材料266。在一些实施例中，晶圆10和20的对准可以通过使用光学感测的方法来实现，尽管也可以使用其他适用的对准方法。
参照图1B，根据一些实施例，在对准之后，通过混成接合将晶圆10和20接合在一起以形成堆叠结构100，堆叠结构100可以是例如3DIC晶粒堆叠。晶圆10和20通过施加压力和热量而混成在一起。在混成接合期间，堆叠结构100可以被加热到约100℃至约200℃的温度，使得介电材料166和266变成非约束的粘性液体并被回流。因此，由于介电材料166和266中的一个在接合工艺期间膨胀而另一个收缩，并且介电材料166和266被回流，因此图1B中的空隙AG被消除以形成图1C的堆叠结构100。
接下来，可以将堆叠结构100进一步加热到约220℃至约380℃范围内的较高温度，使得导电垫164和264通过热压接合，并且介电材料166和266完全固化。在一些实施例中，混成接合中使用的压力为约0.7巴(bar)至约10巴。混成接合工艺可以在惰性环境中进行，例如填充有惰性气体的环境，包括N2、Ar、He或其组合。
如图1B和1C所示，混成接合涉及至少两种类型的接合，包括金属与金属接合和非金属与非金属接合。参照如图1C，在混成接合工艺之后，在晶圆10和20之间形成接合结构50。混成接合结构50包括通过金属与金属接合的导电垫164和264以及通过非金属与非金属的接合的介电材料166和266。如图1C所示，接合结构50在导电垫164和264之间具有金属接合界面50a，但是由于回流工艺，在介电材料166和266之间可能不具有清晰的非金属界面。
因此，晶圆10和20通过介电材料166和266接合，而不是其他介电层。由于介电材料166和266的接合涉及材料的选择，其中一个在加热过程中膨胀而另一个在加热过程中收缩，并且介电材料166和266被回流，因此消除了介电材料166和266中的空隙AG并且接合晶圆10和20的强度增强。
在一些实施方案中，如图2和图3所示，介电材料166和266中的一个或两个可以包括凹陷图案以促进粘附和平整性，并且减少接合过程中的应力。参照图2，在第一晶圆10'中，第一介电材料166包括设置在其中的第一凹陷图案40。第一凹陷图案40包括多个第一凹陷部件40F，第一凹陷部件40F彼此电隔离并且与第一导电垫164电隔离。在一些实施例中，第二介电材料266可以与第二导电垫264共面。在一些其他实施例中，如图3所示，第二凹陷图案60可以包括在晶圆20'的第二介电材料266中。第二凹陷图案60包括多个第二凹陷特征60F，第二凹陷特征60F彼此电隔离并且与第二导电垫264电隔离。
在一些实施例中，第一凹陷结构40F中的至少一个或第二凹陷结构60F中的至少一个包括对应于具有至少三个侧面的圆形或多边形的横截面形状。第一凹陷图案40的一金属表面积相对于第一凹陷图案40的一总表面积的百分比大于50％，并且第二凹陷图案60的一金属表面积相对于一第二凹陷图案60的总表面面积的百分比大于50％。因此，通过将局部应力重新分布到晶圆的较大部分，在介电材料中形成凹陷图案可以减小接合工艺期间的应力。
在一些实施例中，介电材料166和266可以由苯并环丁烯(BCB)聚合物、聚酰亚胺(PI)、聚苯并恶唑(PBO)、其组合或其他合适的材料制成。凹陷特征40F和60F可以分别由与第一和第二导电垫164和264相同的材料制成，或者由其他合适的材料制成。此外，凹陷图案40和60可以不具有电功能，并且可以不与上面的主动电路电连接。凹陷图案40和60以及凹陷特征40F和60F可以在后端(back-end of line，BEOL)工艺期间形成，例如通过毯式沉积金属层，然后使用例如，Cl2和BCl3(例如，氯化物)作为蚀刻剂执行蚀刻。在一些实施例中，凹陷图案40和60可以不以线性阵列布置，而是可以布置成非线性、曲线、斐波那契(Fibonacci)、几何序列或凹陷特征元素的其他均匀分布。在其他实施例中，凹陷图案40和60不需要以均匀分布布置，而是可以包括凹陷特征元素的随机或不规则分布。
根据本公开的一些实施例，在图4中，例示半导体元件的制造方法。参照图4，制造方法10包括：提供第一晶圆和第二晶圆，其中在第一晶圆中形成基板通孔(步骤S110)。在第一晶圆中形成第一介电材料(步骤S120)。在第一介电材料中形成第一导电垫(步骤S130)。在第二晶圆中形成第二介电材料(步骤S140)。在第二介电材料中形成第二导电垫(步骤S150)。接合第一晶圆和第二晶圆(步骤S160)。在该第一晶圆片中形成一第一介电材料(步骤S120)。在该第一介电材料中形成一第一导电垫(步骤S130)。在该第二晶圆中形成一第二介电材料(步骤S140)。在该第二介电材料中形成一第二导电垫(步骤S150)。接合该第一晶圆和该第二晶圆(步骤S160)。
在一些实施例中，接合第一晶圆和第二晶圆还包括将第一晶圆的第一介电材料接合到第二晶圆的第二介电材料，以及将设置在第一介电材料中的第一导电垫接合到第二导电垫。在一些实施例中，第二介电材料中的第二导电垫具有第一高度，第二介电材料具有第二高度，第一高度小于第二高度。在一些实施例中，制造方法还包括在第一介电材料中形成第一凹陷图案，以及在第二介电材料中形成第二凹陷图案。在一些实施例中，第一凹陷图案的一金属表面积相对于第一凹陷图案的一总表面积的百分比大于50％，第二凹陷图案的一金属表面积相对于第二凹陷图案的一总表面积的百分比大于50％。在一些实施例中，该方法还包括在第一晶圆中形成电体管，其中晶体管电耦合到第一晶圆中的接触结构。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本公开的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，这些工艺、机械、制造、物质组成物、手段、方法、或步骤是包含于本公开的权利要求内。

Claims (17)

1.一种半导体元件，包括：
一第一基板，包括一第一介电材料，该第一介电材料包括嵌入其中的一第一导电垫；
一基板通孔，形成在该第一基板中；
一第二基板，包括一第二介电材料，该第二介电材料包括嵌入其中的一第二导电垫，其中该第一介电材料与该第二介电材料不同，该第二导电垫具有一第一高度，该第二介电材料具有一第二高度，该第一高度小于该第二高度；以及
一接合结构，形成在该第一基板和该第二基板之间，其中该接合结构包括接合到该第二导电垫的该第一导电垫和接合到该第二介电材料的该第一介电材料。
2.如权利要求1所述的半导体元件，其中该第一介电材料和该第二介电材料中的一个由一材料在一接合工艺期间膨胀制成，并且该第一介电材料和第二介电材料中的另一个由一材料在接合工艺期间收缩制成。
3.如权利要求1所述的半导体元件，还包括：
一接触结构，形成在该第一基板的上方，其中该接触结构形成在该基板通孔和该第一介电材料之间。
4.如权利要求3所述的半导体元件，还包括：
一晶体管，形成在该第一基板的上方；以及
一接触插塞，形成在该晶体管的上方，其中该接触结构耦合到该基板通孔和该接触插塞。
5.如权利要求1所述的半导体元件，还包括：
一扩散阻挡层，形成在该第一介电材料内；以及
一接触结构，形成在该第一基板的上方，其中该接触结构形成在该基板通孔和该扩散阻挡层之间。
6.一种半导体元件，包括：
一第一基板，包括第一介电材料，该第一介电材料包括设置在其中的第一凹陷图案，该第一介电材料包括一第一导电垫，其中所述第一凹陷图案包括多个第一凹陷特征，该多个第一凹陷特征彼此电隔离并且与该第一 导电垫电隔离；
一基板通孔，形成在该第一基板中；
一第二基板，包括一第二介电材料，该第二介电材料包括一第二导电垫，其中该第二介电材料包括设置在其中的一第二凹陷图案；该第二凹陷图案包括多个第二凹陷特征，该多个第二凹陷特征彼此电隔离并且与该第二导电垫电隔离；以及
一接合结构，形成在该第一基
板和该第二基板之间，其中该接合结构包括接合到该第二导电垫的该第一导电垫和接合到该第二介电材料的该第一介电材料。
7.如权利要求6所述的半导体元件，其中该第一凹陷特征 中的至少一个或该第二凹陷特征 中的至少一个包括对应于具有至少三个侧面的圆形或多边形的横截面形状。
8.如权利要求6所述的半导体元件，其中该第一凹陷图案的一金属表面积相对于该第一凹陷图案的一总表面积的百分比大于50％，并且该第二凹陷图案的一金属表面积相对于第二凹陷图案的总表面积的百分比大于50％。
9.如权利要求6所述的半导体元件，还包括：
一接触结构，形成在该第一基板的上方，其中该接触结构形成在该基板通孔和该第一介电材料之间。
10.如权利要求9所述的半导体元件，还包括：
一晶体管，形成在该第一基板的上方；以及
一接触插塞，形成在该晶体管的上方，其中该接触结构耦合到该基板通孔和该接触插塞。
11.如权利要求6所述的半导体元件，其中该第一介电材料和该第二介电材料由聚酰亚胺、聚苯并恶唑或苯并环丁烯化合物制成。
12.如权利要求6所述的半导体元件，还包括：
一扩散阻挡层，形成在该第一介电材料内；以及
一接触结构，形成在该第一基板的上方，其中该接触结构形成在该基板通孔和该扩散阻挡层之间。
13.一种半导体元件的制造方法，包括：
提供一第一晶圆和一第二晶圆，其中在该第一晶圆中形成一基板通孔；
在该第一晶圆中形成一第一介电材料；
在该第一介电材料中形成一第一导电垫；
在所述第一介电材料中形成一第一凹陷图案，其中该第一凹陷图案包括多个第一凹陷特征，该多个第一凹陷特征彼此电隔离并且与该第一 导电垫电隔离；在第二介电材料中形成一第二凹陷图案，其中该第二凹陷图案包括多个第二凹陷特征，该多个第二凹陷特征彼此电隔离并且与第二导电垫电隔离； 在该第二晶圆中形成一第二介电材料；
在该第二介电材料中形成一第二导电垫；以及
接合该第一晶圆和该第二晶圆。
14.如权利要求13所述的制造方法，其中接合该第一晶圆和该第二晶圆还包括：
将该第一晶圆的该第一介电材料接合到该第二晶圆的该第二介电材料，并且将设置在该第一介电材料中的该第一导电垫接合到设置在该第二介电材料中的该第二导电垫。
15.如权利要求14所述的制造方法，其中该第二介电材料中的该第二导电垫具有一第一高度，该第二介电材料具有第二高度，该第一高度小于该第二高度。
16.如权利要求13所述的制造方法，其中该第一凹陷图案的一金属表面积相对于该第一凹陷图案的一总表面积的百分比大于50％，并且该第二凹陷图案的一金属表面积相对于第二凹陷图案的总表面积的百分比大于50％。
17.如权利要求13所述的制造方法，还包括：
在该第一晶圆中形成一晶体管，其中该晶体管电耦合到该第一晶圆中的一接触结构。
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