JP5412316B2 - 半導体装置、積層型半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置、積層型半導体装置及び半導体装置の製造方法 Download PDFInfo
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Description
以下、本発明の第1の実施形態に係る半導体装置について、図面を参照しながら説明する。
以下、本発明の第1の実施形態の変形例に係る半導体装置について、図面を参照しながら説明する。
1a 第1の面
1b 第2の面
3 不純物領域
4 ゲート絶縁膜
5 ゲート電極
6 素子分離
7 コンタクト
8a 第1層間絶縁膜
8b 第2層間絶縁膜
8c 第3層間絶縁膜
9a 第1配線
9b 第2配線
10a 第1ビア
10b 第2ビア
11 電極パッド
20 貫通孔
21 絶縁膜
22 バリア膜
23 導電部
24A、24B バンプ
25A、25B アンダーフィル
26 インターポーザ
30 ゲッタリングサイト
100、100A、100B、102 半導体装置
101 積層型半導体装置
Claims (17)
- 素子形成面である第1の面及びその反対側の第2の面を有する半導体基板と、
前記第1の面から前記第2の面まで前記半導体基板を貫通するように形成された貫通孔と、
前記貫通孔の内壁上に形成された絶縁膜と、
前記貫通孔の内壁上に前記絶縁膜を挟んで形成されたバリア膜と、
前記絶縁膜及び前記バリア膜が形成された前記貫通孔が埋まるように形成された導電部とを備え、
前記貫通孔の周辺に位置する部分の前記半導体基板における少なくとも前記第1の面側にゲッタリングサイトが形成されており、
前記バリア膜の膜厚は、前記貫通孔内における前記第2の面側よりも前記第1の面側において薄く形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記貫通孔における前記第1の面側の底部の全面にも前記バリア膜が形成されていることを特徴とする半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記貫通孔の中心から前記半導体基板における活性素子形成領域までの最短距離よりも、前記貫通孔の中心から前記ゲッタリングサイトまでの最短距離の方が短いことを特徴とする半導体装置。 - 請求項1〜3のいずれか1項に記載の半導体装置において、
前記ゲッタリングサイトは前記貫通孔を取り囲むように形成されていることを特徴とする半導体装置。 - 請求項1〜3のいずれか1項に記載の半導体装置において、
前記貫通孔の口径は、前記第2の面から前記第1の面へ向けて小さくなっていることを特徴とする半導体装置。 - 請求項1〜5のいずれか1項に記載の半導体装置において、
前記半導体基板の前記第1の面上に配線が形成されており、
前記導電部と前記配線とが電気的に接続されていることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記導電部と前記配線とは、前記導電部と前記配線との間に介在するコンタクトによって電気的に接続されていることを特徴とする半導体装置。 - 請求項1〜7のいずれか1項に記載の半導体装置において、
前記ゲッタリングサイトは、前記貫通孔が3つ以上二次元的に配列されてなる貫通孔群を取り囲むように形成されていることを特徴とする半導体装置。 - 請求項1〜8のいずれか1項に記載の半導体装置において、
前記貫通孔の周辺に位置する部分の前記半導体基板における前記第1の面側の表面部に絶縁領域が形成されており、
前記ゲッタリングサイトは前記絶縁領域の下側に形成されていることを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記半導体基板における前記第1の面側の表面部に素子分離が形成されており、
前記絶縁領域は、前記素子分離と実質的に同じ深さまで形成されていることを特徴とする半導体装置。 - 複数の半導体装置を積層させた積層型半導体装置であって、
前記複数の半導体装置のうち少なくとも1つは、請求項1〜10のいずれか1項に記載の半導体装置であることを特徴とする積層型半導体装置。 - 貫通孔形成領域の周辺に位置する部分の半導体基板における少なくとも素子形成面側にゲッタリングサイトを形成する工程(a)と、
前記素子形成面からその反対側の面まで前記半導体基板を貫通するように貫通孔を形成する工程(b)と、
前記貫通孔の内壁上に絶縁膜を形成する工程(c)と、
前記貫通孔の内壁上に前記絶縁膜を挟んで、前記貫通孔における前記素子形成面の反対側の面側よりも前記素子形成面側において薄くなるようにバリア膜を形成する工程(d)と、
前記絶縁膜及び前記バリア膜が形成された前記貫通孔が埋まるように導電部を形成する工程(e)とを備えていることを特徴とする半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記工程(d)では、前記貫通孔における前記素子形成面側の底部の全面にも前記バリア膜が残存するように、前記バリア膜を形成することを特徴とする半導体装置の製造方法。 - 素子形成面である第1の面及びその反対側の第2の面を有する半導体基板と、
前記第1の面から前記第2の面まで前記半導体基板を貫通するように形成された貫通孔と、
前記貫通孔の内壁上に形成された絶縁膜と、
前記貫通孔の内壁上に前記絶縁膜を挟んで形成されたバリア膜と、
前記絶縁膜及び前記バリア膜が形成された前記貫通孔が埋まるように形成された導電部とを備え、
前記貫通孔の周辺に位置する部分の前記半導体基板における少なくとも前記第1の面側にゲッタリングサイトが形成されており、
前記ゲッタリングサイトは、前記貫通孔が3つ以上二次元的に配列されてなる貫通孔群を取り囲むように形成されていることを特徴とする半導体装置。 - 素子形成面である第1の面及びその反対側の第2の面を有する半導体基板と、
前記第1の面から前記第2の面まで前記半導体基板を貫通するように形成された貫通孔と、
前記貫通孔の内壁上に形成された絶縁膜と、
前記貫通孔の内壁上に前記絶縁膜を挟んで形成されたバリア膜と、
前記絶縁膜及び前記バリア膜が形成された前記貫通孔が埋まるように形成された導電部とを備え、
前記貫通孔の周辺に位置する部分の前記半導体基板における少なくとも前記第1の面側にゲッタリングサイトが形成されており、
前記貫通孔の周辺に位置する部分の前記半導体基板における前記第1の面側の表面部に絶縁領域が形成されており、
前記ゲッタリングサイトは前記絶縁領域の下側に形成されていることを特徴とする半導体装置。 - 請求項15に記載の半導体装置において、
前記半導体基板における前記第1の面側の表面部に素子分離が形成されており、
前記絶縁領域は、前記素子分離と実質的に同じ深さまで形成されていることを特徴とする半導体装置。 - 複数の半導体装置を積層させた積層型半導体装置であって、
前記複数の半導体装置のうち少なくとも1つは、請求項14〜16のいずれか1項に記載の半導体装置であることを特徴とする積層型半導体装置。
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US8994174B2 (en) * | 2011-09-30 | 2015-03-31 | Intel Corporation | Structure having a planar bonding surface |
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