WO2017113932A1 - 焊垫、包括焊垫的半导体芯片及形成方法 - Google Patents

焊垫、包括焊垫的半导体芯片及形成方法 Download PDF

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Publication number
WO2017113932A1
WO2017113932A1 PCT/CN2016/102136 CN2016102136W WO2017113932A1 WO 2017113932 A1 WO2017113932 A1 WO 2017113932A1 CN 2016102136 W CN2016102136 W CN 2016102136W WO 2017113932 A1 WO2017113932 A1 WO 2017113932A1
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Prior art keywords
layer
metal
opening
barrier layer
forming
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PCT/CN2016/102136
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English (en)
French (fr)
Inventor
王之奇
王鑫琴
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苏州晶方半导体科技股份有限公司
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Priority claimed from CN201521116234.9U external-priority patent/CN205452270U/zh
Priority claimed from CN201511009450.8A external-priority patent/CN105489582B/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Priority to US15/767,122 priority Critical patent/US20190074258A1/en
Priority to JP2018521022A priority patent/JP6548825B2/ja
Priority to KR1020187011137A priority patent/KR102029915B1/ko
Publication of WO2017113932A1 publication Critical patent/WO2017113932A1/zh

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
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    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
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    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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    • H01L2924/161—Cap
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    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Definitions

  • the present invention relates to the field of semiconductor chip technology, and more particularly to the field of structural fabrication of semiconductor chips.
  • Laser drilling technology has a wide range of applications in the semiconductor field, especially in the field of semiconductor chip packaging.
  • FIG. 1 is a schematic diagram of a wafer-level semiconductor chip structure
  • FIG. 2 is a schematic diagram of a package structure of the semiconductor chip.
  • the wafer 100 has a plurality of semiconductor chips 201 arranged in an array, and a plurality of semiconductor chips 201 adjacent to each other are provided with a scribe line region, which will be along the scribe line region after wafer level packaging and testing are completed.
  • the semiconductor chips 201 are separated from each other.
  • Each semiconductor chip 201 has an integrated circuit and a plurality of pads electrically connected to the integrated circuit, the pads being used to establish an electrical connection with an external circuit.
  • the image sensor chip is taken as an example.
  • the first surface I of the semiconductor chip 201 has a protective layer 203 .
  • the solder pad 202 is located in the protective layer 203 .
  • the optical layer is disposed on the protective layer 203 corresponding to the photosensitive region.
  • the protective substrate 200 is provided with a partition wall 205. After the semiconductor chip 201 is aligned with the protective substrate 200, the optical device layer 207 is located in the cavity 206 formed by the partition wall 205.
  • a laser hole 209 penetrating the pad 202 is formed on the pad 202, and a second extension is formed in the laser hole 209 to the semiconductor chip 201.
  • the metal wiring layer 210 on the surface II is then formed on the second surface II to form a solder ball 212 connected to the metal wiring layer 210, and the solder pad 202 is electrically connected to an external circuit through the solder ball 212.
  • the insulating layer 208a and the insulating layer 211 are formed on the semiconductor chip 201 to isolate the metal wiring layer from other circuits.
  • the solder pad usually comprises a multilayer structure of at least two metal layers and a dielectric layer between adjacent metal layers, and the structure and material of the solder pad directly affect the quality and difficulty of laser drilling. Therefore, how to improve the quality of laser drilling of the bonding pad and reduce the difficulty of laser drilling is a technical problem that a person skilled in the art needs to solve.
  • the invention improves the quality of laser drilling of the bonding pad and reduces the difficulty of laser drilling by designing a novel pad structure.
  • a solder pad characterized in that the solder pad comprises at least two metal layers and a dielectric layer between adjacent metal layers; wherein the solder pad has laser drilling In the region, an opening is disposed on the dielectric layer corresponding to the laser perforated region, and a metal plug is disposed in the opening, and two ends of the metal plug are respectively in contact with the adjacent metal layer.
  • the metal plug may include: a bottom portion of the opening in contact with a metal layer in the opening; and a barrier layer formed on a sidewall of the opening; a diffusion barrier layer on the barrier layer; A filler metal on the diffusion barrier layer and filling the opening.
  • the filler metal is made of tungsten
  • the barrier layer is made of titanium
  • the diffusion barrier layer is made of titanium nitride.
  • a region other than the opening in the dielectric layer is further provided with at least one opening to form a conductive plug in the at least one opening, and two ends of the conductive plug are respectively electrically connected to the adjacent metal layer.
  • the conductive plug has the same material and structure as the metal plug.
  • the metal layer comprises a barrier layer bonded tightly to the protective or dielectric layer of the pad, an intermediate metal layer bonded to the barrier layer, and an anti-reflective layer deposited on the intermediate metal layer.
  • the material of the barrier layer is titanium
  • the material of the intermediate metal layer is aluminum-copper alloy
  • the material of the anti-reflection layer is titanium nitride
  • a laser hole is disposed in the laser perforation area, and the laser hole sequentially penetrates the metal layer and the metal plug.
  • a semiconductor chip including the above-described pad is provided.
  • a method of forming a pad for a semiconductor chip comprising: (a) forming a metal layer; (b) forming a dielectric layer on the metal layer; (c) forming a metal plug in the dielectric layer, wherein the metal plug is located in the laser perforated area; (d) forming another metal layer on the dielectric layer.
  • the step of forming a metal plug in the dielectric layer includes: forming an opening on the dielectric layer by an etching process; forming a resistance at a bottom of the opening and a sidewall of the opening by a deposition process a barrier layer; a diffusion barrier layer is formed on the barrier layer by a deposition process; and a filling metal filling the opening is formed on the diffusion barrier layer by a deposition process.
  • the filler metal is made of tungsten
  • the barrier layer is made of titanium
  • the diffusion barrier layer is made of titanium nitride.
  • the method further includes: providing at least one opening in a region other than the opening to form a conductive plug in the at least one opening, the two ends of the conductive plug respectively adjacent to the metal layer Electrical connection.
  • the conductive plug is formed in the same material and method as the metal plug is formed.
  • the step of forming a metal layer comprises: depositing a barrier layer on a protective layer or a dielectric layer of the pad by a deposition process; depositing an intermediate metal layer on the barrier layer by a deposition process; and using a deposition process in the intermediate metal layer An anti-reflection layer is deposited on the surface; the silicon wafer is imprinted by a photoresist, and a metal layer conforming to the shape of the pad is formed by an etching process.
  • the material of the barrier layer is titanium
  • the material of the intermediate metal layer is aluminum-copper alloy
  • the material of the anti-reflection layer is titanium nitride
  • a laser hole that sequentially penetrates the metal layer and the metal plug is formed in the laser perforated area of the pad.
  • steps (b) through (d) are repeated to form a plurality of metal layers and dielectric layers.
  • the invention has the beneficial effects that the quality of the laser drilling of the bonding pad is improved and the difficulty of laser drilling is reduced, the laser acts on the metal material to avoid contact with the dielectric layer, and the thermal deformation of the dielectric layer can be effectively prevented, and the laser hole is prevented. Cracks are formed on the inner wall, and since the sidewalls of the laser holes are all metal, the conductive properties of the pads are improved.
  • FIG. 1 is a schematic structural view of a prior art wafer.
  • FIG. 2 is a schematic diagram of a package structure of a prior art image sensor chip.
  • 3A is a schematic structural view of a semiconductor chip according to a preferred embodiment of the present invention.
  • 3B is a cross-sectional view of a semiconductor chip in accordance with a preferred embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of a pad of a preferred embodiment of the present invention.
  • Figure 5 is a schematic view showing the structure of a metal layer in a preferred embodiment of the present invention.
  • Figure 6 is a schematic view showing the structure of a metal plug disposed in a dielectric layer in accordance with a preferred embodiment of the present invention.
  • the semiconductor chip 301 has an integrated circuit (not shown in FIG. 3A) and a plurality of pads 31 electrically connected to the integrated circuit, and the pad 31 is used to establish an electrical connection with an external circuit.
  • the present invention does not limit the specific structure and function of the integrated circuit.
  • the integrated circuit here is broadly understood, that is, the integrated circuit is a certain number of common electronic components, such as resistors, capacitors, transistors, etc., and the connection between these components.
  • a protective layer 32 is disposed on one surface of the semiconductor chip 301, and the pad 31 is disposed in the protective layer 32.
  • the pad 31 has a laser perforation area 310.
  • the laser hole 320 is disposed in the laser perforation area and the area of the laser perforation area is larger than the area of the laser hole, which is convenient for the simple laser drilling operation.
  • the laser hole is positioned to the laser perforated area, and the laser perforated area is disposed at the center of the pad 31. Thus, in the laser drilling operation, the laser is aligned with the center position of the pad 31 without adding a laser alignment mark. .
  • the shape of the laser perforated area 310 is square.
  • the shape of the laser perforated area 310 is not specifically limited in the present invention, and the shape may also be circular, as long as the laser hole is located in the laser perforated area and the laser is There is a certain spacing between the sidewalls of the apertures and the sidewalls of the laser apertured regions 310.
  • the bonding pad 31 has four metal layers, which are a first metal layer 311, a second metal layer 312, a third metal layer 313, and a fourth metal layer 314, respectively.
  • a first dielectric layer 315 is disposed between the first metal layer 311 and the second metal layer 312, and a second dielectric layer 316, a third metal layer 313 and a fourth metal layer are disposed between the second metal layer 312 and the third metal layer 313.
  • Each dielectric layer is provided with an opening corresponding to the laser perforated area 310, and a metal plug is disposed in the opening, corresponding to the first metal plug 325, the second metal plug 326 and the third metal plug 327 in FIG.
  • the two ends of each metal plug are respectively in contact with the adjacent metal layers, that is, the two ends of the first metal plug 325 are respectively in contact with the first metal layer 311 and the second metal layer 312, and the two ends of the second metal plug 326 are respectively
  • the second metal layer 312 and the third metal layer 313 are in contact with each other, and both ends of the third metal plug 327 are in contact with the third metal layer 313 and the fourth metal layer 314, respectively.
  • a laser hole 320 penetrating the pad 31 is formed in the laser puncturing region 310 of the pad 31.
  • the laser hole 320 sequentially penetrates the fourth metal layer 314 and the third metal plug 327.
  • a region other than the opening in the dielectric layer is further provided with at least one opening to provide a conductive plug 330, and both ends of the conductive plug 330 are electrically connected to the adjacent metal layers, respectively.
  • the production of the metal plug and the conductive plug can be performed simultaneously.
  • Pad 31 is formed in a wafer level process flow.
  • a first metal layer 311 is formed, then a first dielectric layer 315 is formed on the first metal layer 311, and then a first metal plug 325 and at least one conductive plug 330 are formed in the first dielectric layer 315, and then A second metal layer 312 is formed on the first dielectric layer 315, and is repeated, and finally a pad structure as shown in FIG. 4 is formed.
  • the metal layer is a multi-layer structure. Referring to FIG. 5, taking the second metal layer 312 as an example, the process steps of fabricating the second metal layer 312 include:
  • a barrier layer 3121 is deposited on the first dielectric layer 315.
  • the barrier layer 3121 is made of titanium, and the barrier layer 3121 is tightly bonded to the first dielectric layer 315.
  • An intermediate metal layer 3122 is deposited on the barrier layer 3121.
  • the material of the intermediate metal layer 3122 is an aluminum-copper alloy, and the barrier layer 3121 has a good bond with the intermediate metal layer.
  • An anti-reflection layer 3123 is deposited on the aluminum-copper alloy layer 3112.
  • the anti-reflection layer 3123 is made of titanium nitride, which can serve as an anti-reflection layer in the etching process.
  • the silicon wafer is imprinted on the wafer by using a photoresist, and then etched by an etching process to form a second metal layer 312 conforming to the shape of the pad.
  • a barrier layer is deposited on the protective layer 32 of the pad.
  • the process steps of fabricating the second metal plug 326 include:
  • the second dielectric layer 316 is formed on the second metal layer 312.
  • the second dielectric layer 316 is made of silicon oxide or silicon nitride.
  • the second dielectric layer 316 is etched, an opening is formed on the dielectric layer 316, and the second metal layer 312 is exposed at the bottom of the opening.
  • a barrier layer 3162 is deposited on the bottom and side walls of the opening, and the barrier layer 3162 is made of titanium.
  • the filling metal 3164 is made of tungsten, which can fill the opening without voids and has good grinding and polishing properties.
  • the barrier layer 3162 acts as a binder between the filler metal 3164 and the second dielectric layer 316.
  • the diffusion barrier layer 3163 serves to block diffusion of the filler metal 3164.
  • polishing filler metal 3164 is ground to be flush with the surface of the second dielectric layer 316.
  • the manufacturing process of the conductive plug 330 is the same as that of the second metal plug 326, and will not be described herein.
  • the special structural design of the laser perforated area 310 improves the quality of the laser perforation of the bonding pad and reduces the difficulty of laser drilling.
  • the laser acts on the metal substance to avoid contact with the dielectric layer, and the medium can be effectively prevented.
  • the layer is thermally deformed to prevent cracks on the inner wall of the laser hole, and since the side walls of the laser hole are all metal, the conductive property of the pad is improved.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种焊垫、包括该焊垫的半导体芯片以及其形成方法。焊垫（31）包括至少两层金属层以及位于相邻金属层之间的介质层；其中，焊垫上具有激光打孔区域（310），介质层上对应激光打孔区域设置开口，在开口中设置金属塞，金属塞的两端分别与相邻的金属层接触。焊垫的形成方法提高了焊垫的激光打孔的质量且降低了激光打孔的难度，激光作用于金属物质上而避免与介质层接触，能够有效防止介质层热变形。

Description

焊垫、包括焊垫的半导体芯片及形成方法
本申请要求于2015年12月29日提交中国专利局、申请号为201511009450.8、发明名称为“半导体芯片及其形成方法”，以及于2015年12月29日提交中国专利局、申请号为201521116234.9、发明名称为“半导体芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体芯片技术领域，尤其涉及半导体芯片的结构制造领域。
背景技术
激光打孔技术在半导体领域有着广泛的应用，特别是在半导体芯片的封装领域。
请参考图1以及图2，图1为晶圆级半导体芯片结构示意图，图2为半导体芯片的封装结构示意图。请参考图1，晶圆100具有多个阵列排布的半导体芯片201，彼此相邻的多个半导体芯片201之间设置有切割道区域，在完成晶圆级封装和测试之后沿切割道区域将半导体芯片201彼此分离。每一半导体芯片201具有集成电路以及与所述集成电路电连接的多个焊垫，焊垫用于与外部电路建立电连接。
请参考图2，本例以影像传感芯片为例，半导体芯片201的第一表面I上具有保护层203，焊垫202位于保护层203内，保护层203上对应感光区域设置有光学器件层207，保护基板200上设置有间隔墙205，当半导体芯片201与保护基板200对位压合后，光学器件层207位于间隔墙205包围形成的空腔206内。
在图2所示的结构中，为了实现焊垫202与外部电路建立电连接，在焊垫202上形成穿透焊垫202的激光孔209，在激光孔209内形成延伸至半导体芯片201第二表面II上的金属布线层210，然后在第二表面II上形成与金属布线层210连接的锡球212，通过锡球212实现焊垫202与外部电路电连接。当然，为了避免金属布线层210与半导体芯片201中的其他电路互相干扰，在半导体芯片201上形成有绝缘层208a以及绝缘层211将金属布线层与其他电路隔离。
现有技术中焊垫通常包括至少两层金属层以及位于相邻金属层之间的介质层的多层结构，焊垫的结构以及材质直接影响了激光打孔的质量以及难易程度， 因此，如何提高焊垫的激光打孔的质量以及降低激光打孔的难度成为本领域技术人员需要解决的技术问题。
发明内容
本发明通过设计一种新型的焊垫结构，提高了焊垫的激光打孔的质量以及降低了激光打孔的难度。
根据本发明的一方面，提供了一种焊垫，其特征在于，所述焊垫包括至少两层金属层以及位于相邻金属层之间的介质层；其中，所述焊垫上具有激光打孔区域，介质层上对应所述激光打孔区域设置开口，在所述开口中设置金属塞，所述金属塞的两端分别与相邻的金属层接触。
可选地，所述金属塞可包含：在所述开口中与一个金属层接触的开口底部以及所述开口的侧壁上形成的阻挡层；位于所述阻挡层上的扩散阻挡层；位于所述扩散阻挡层上且填充所述开口的填充金属。
可选地，所述填充金属的材质为钨，所述阻挡层的材质为钛，所述扩散阻挡层的材质为氮化钛。
可选地，所述介质层中开口之外的区域还设置有至少一个开口以在所述至少一个开口中形成导电塞，所述导电塞的两端分别与相邻的金属层电连接。
可选地，所述导电塞与所述金属塞具有相同的材质和结构。
可选地，所述金属层包括与焊垫的保护层或者介质层结合紧密的阻挡层、与阻挡层键合的中间金属层以及淀积在中间金属层上的抗反射层。
可选地，所述阻挡层的材质为钛，所述中间金属层的材质为铝铜合金，所述抗反射层的材质为氮化钛。
可选地，所述激光打孔区域内设置有激光孔，所述激光孔依次穿透所述金属层以及所述金属塞。
根据本发明的另一方面，提供了一种包括上述的焊垫的半导体芯片。
根据本发明的另一方面，提供了一种应用于半导体芯片的焊垫的形成方法，其特征在于，所述方法包括：(a)形成金属层；(b)在金属层上形成介质层；(c)在介质层中形成金属塞，其中，所述金属塞位于激光打孔区域；(d)在介质层上形成另一金属层。
可选地，所述在介质层中形成金属塞的步骤包括：采用刻蚀工艺在所述介质层上形成开口；采用沉积工艺在所述开口的底部以及所述开口的侧壁形成阻 挡层；采用沉积工艺在所述阻挡层上形成扩散阻挡层；采用沉积工艺在所述扩散阻挡层上形成填充所述开口的填充金属。
可选地，所述填充金属的材质为钨，所述阻挡层的材质为钛，所述扩散阻挡层的材质为氮化钛。
可选地，所述方法还包括：在所述开口之外的区域还设置有至少一个开口以在所述至少一个开口中形成导电塞，所述导电塞的两端分别与相邻的金属层电连接。
可选地，以与形成所述金属塞相同的材料和方法来形成导电塞。
可选地，所述形成金属层的步骤包括：采用沉积工艺在焊垫的保护层或者介质层上淀积阻挡层；采用沉积工艺在阻挡层淀积中间金属层；采用沉积工艺在中间金属层上淀积抗反射层；利用光刻胶刻印硅片，采用刻蚀工艺形成与焊垫形状一致的金属层。
可选地，所述阻挡层的材质为钛，所述中间金属层的材质为铝铜合金，所述抗反射层的材质为氮化钛。
可选地，在所述焊垫的激光打孔区域形成依次穿透所述金属层和金属塞的激光孔。
可选地，重复步骤(b)至步骤(d)以形成多个金属层和介质层。本发明的有益效果是提高了焊垫的激光打孔的质量且降低了激光打孔的难度，激光作用于金属物质上而避免与介质层接触，能够有效防止介质层热变形，防止激光孔的内壁上产生裂纹，并且由于激光孔侧壁全部是金属，提高了焊垫的导电性能。
附图说明
图1为现有技术晶圆的结构示意图。
图2为现有技术影像传感芯片封装结构示意图。
图3A为本发明优选实施例半导体芯片结构示意图。
图3B为本发明优选实施例半导体芯片的剖视图。
图4为本发明优选实施例焊垫的剖视图。
图5为本发明优选实施例金属层的结构示意图。
图6为本发明优选实施例设置在介质层中金属塞的结构示意图。
具体实施方式
以下将结合附图对本发明的具体实施方式进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法或功能上的变换均包含在本发明的保护范围内。
需要说明的是，提供这些附图的目的是为了有助于理解本发明的实施例，而不应解释为对本发明的不当的限制。为了更清楚起见，图中所示尺寸并未按比例绘制，可能会做放大、缩小或其他改变。
请参考图3A以及图3B，半导体芯片301具有集成电路(图3A中未绘示)以及与所述集成电路电连接的多个焊垫31，焊垫31用于与外部电路建立电连接。本发明不限定集成电路的具体结构与功能，此处集成电路作广义的理解，即所谓的集成电路是把一定数量的常用电子元件，如电阻、电容、晶体管等，以及这些元件之间的连线，通过半导体工艺集成在一起的具有某种功能的电路。在半导体芯片301的其中一个表面设置有保护层32，焊垫31设置于保护层32内。
焊垫31上具有激光打孔区域310，在后续的激光打孔工艺中，激光孔320设置在激光打孔区域且激光打孔区域的面积大于激光孔的面积，为了简便激光打孔操作，方便激光孔定位至激光打孔区域，将激光打孔区域设置于焊垫31的中心位置，如此，在激光打孔操作中只要将激光对准焊垫31的中心位置而不需要增设激光对准标记。
于本实施例中，激光打孔区域310的形状为正方形，本发明不具体限定激光打孔区域310的形状，其形状也可以是圆形的，只要保证激光孔位于激光打孔区域内且激光孔的侧壁与激光打孔区域310的侧壁之间具有一定的间隔。
图4为焊垫31的剖视图，于此实施例中，焊垫31具有四层金属层，分别是第一金属层311、第二金属层312、第三金属层313以及第四金属层314，第一金属层311与第二金属层312之间具有第一介质层315，第二金属层312与第三金属层313之间具有第二介质层316，第三金属层313与第四金属层314之间具有第三介质层317。
每一介质层对应激光打孔区域310设置开口，并在开口中设置金属塞，对应图4中第一金属塞325、第二金属塞326以及第三金属塞327。每一金属塞的两端分别与相邻的金属层接触，即第一金属塞325的两端分别与第一金属层311、第二金属层312接触，第二金属塞326的两端分别与第二金属层312、第三金属层313接触，第三金属塞327的两端分别与第三金属层313、第四金属层314接触。
在后续激光打孔工艺，在焊垫31的激光打孔区域310形成穿透焊垫31的激光孔320，对应图4中，激光孔320依次打穿第四金属层314、第三金属塞327、第三金属层313、第二金属塞326、第二金属层312、第一金属塞325以及第一金属层311。
为了提高金属层之间的电连接稳定性，介质层中开口之外的区域还设置有至少一个开口以设置导电塞330，导电塞330的两端分别与相邻的金属层电连接。
为了提高工艺流程的简洁性以及便利性，金属塞与导电塞的制作可以同步进行。
焊垫31是在晶圆级的工艺流程中形成的。
首先，形成第一金属层311，然后，在第一金属层311上形成第一介质层315，然后，在第一介质层315中形成第一金属塞325以及至少一个导电塞330，然后，在第一介质层315上形成第二金属层312，以此重复，最后形成如图4所示的焊垫结构。
金属层为复层结构，请参考图5，以第二金属层312为例，制作第二金属层312的流程步骤包括：
(1)在第一介质层315上淀积阻挡层3121，阻挡层3121的材质为钛，阻挡层3121与第一介质层315结合紧密。
(2)在阻挡层3121上淀积中间金属层3122，中间金属层3122的材质为铝铜合金，阻挡层3121与中间金属层之间具有良好键合。
(3)在铝铜合金层3112上淀积抗反射层3123，抗反射层3123的材质为氮化钛，其可以充当刻蚀工艺中的抗反射层。
(4)在晶圆上利用光刻胶刻印硅片，然后采用刻蚀工艺进行刻蚀，形成与焊垫形状一致的第二金属层312。
当然对于第一金属层311而言，其是在焊垫的保护层32上淀积阻挡层。
请参考图6，以第二金属塞326为例，制作第二金属塞326的流程步骤包括：
(1)在完成第二金属层312的制作之后，在第二金属层312上形成第二介质层316。第二介质层316的材质为氧化硅，也可以是氮化硅。
(2)刻蚀第二介质层316，在介质层316上形成开口，开口底部暴露第二金属层312。
(3)在开口的底部以及侧壁淀积阻挡层3162，阻挡层3162的材质为钛。
(4)在阻挡层3162上淀积扩散阻挡层3163，其中，所述扩散阻挡层的材 质为氮化钛。
(5)在开口中淀积填充开口的填充金属3164，本实施例中，填充金属3164的材质为钨，能够无空洞地填充开口且具有良好的磨抛特性。阻挡层3162充当填充金属3164与第二介质层316之间的黏合剂。扩散阻挡层3163用于阻挡填充金属3164的扩散。
(6)磨抛填充金属3164使其高度与第二介质层316的表面平齐。
导电塞330的制作工艺与第二金属塞326的制作工艺相同，在此，不再赘述。
基于本发明中激光打孔区域310的特殊结构设计，提高了焊垫的激光打孔的质量且降低了激光打孔的难度，激光作用于金属物质上而避免与介质层接触，能够有效防止介质层热变形，防止激光孔的内壁上产生裂纹，且，由于激光孔侧壁全部是金属，提高了焊垫的导电性能。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (18)

  1. 一种焊垫，其特征在于，所述焊垫包括至少两层金属层以及位于相邻金属层之间的介质层；
    其中，所述焊垫上具有激光打孔区域，介质层上对应所述激光打孔区域设置开口，在所述开口中设置金属塞，所述金属塞的两端分别与相邻的金属层接触。
  2. 根据权利要求1所述的焊垫，其特征在于，所述金属塞包含：
    在所述开口中与一个金属层接触的开口底部以及所述开口的侧壁上形成的阻挡层；
    位于所述阻挡层上的扩散阻挡层；
    位于所述扩散阻挡层上且填充所述开口的填充金属。
  3. 根据权利要求2所述的焊垫，其特征在于，所述填充金属的材质为钨，所述阻挡层的材质为钛，所述扩散阻挡层的材质为氮化钛。
  4. 根据权利要求3所述的焊垫，其特征在于，所述介质层中开口之外的区域还设置有至少一个开口以在所述至少一个开口中形成导电塞，所述导电塞的两端分别与相邻的金属层电连接。
  5. 根据权利要求4所述的焊垫，其特征在于，所述导电塞与所述金属塞具有相同的材质和结构。
  6. 根据权利要求1所述的焊垫，其特征在于，所述金属层包括与焊垫的保护层或者介质层结合紧密的阻挡层、与阻挡层键合的中间金属层以及淀积在中间金属层上的抗反射层。
  7. 根据权利要求6所述的焊垫，其特征在于，所述阻挡层的材质为钛，所述中间金属层的材质为铝铜合金，所述抗反射层的材质为氮化钛。
  8. 根据权利要求1所述的焊垫，其特征在于，所述激光打孔区域内设置有 激光孔，所述激光孔依次穿透所述金属层以及所述金属塞。
  9. 一种包括如权利要求1-8中的任一项所述的焊垫的半导体芯片。
  10. 一种应用于半导体芯片的焊垫的形成方法，其特征在于，所述方法包括：
    (a)形成金属层；
    (b)在金属层上形成介质层；
    (c)在介质层中形成金属塞，其中，所述金属塞位于激光打孔区域；
    (d)在介质层上形成另一金属层。
  11. 根据权利要求10所述的焊垫的形成方法，其特征在于，所述在介质层中形成金属塞的步骤包括：
    采用刻蚀工艺在所述介质层上形成开口；
    采用沉积工艺在所述开口的底部以及所述开口的侧壁形成阻挡层；
    采用沉积工艺在所述阻挡层上形成扩散阻挡层；
    采用沉积工艺在所述扩散阻挡层上形成填充所述开口的填充金属。
  12. 根据权利要求11所述的焊垫的形成方法，所述填充金属的材质为钨，所述阻挡层的材质为钛，所述扩散阻挡层的材质为氮化钛。
  13. 根据权利要求12所述的焊垫的形成方法，其特征在于，所述方法还包括：
    在所述开口之外的区域还设置有至少一个开口以在所述至少一个开口中形成导电塞，所述导电塞的两端分别与相邻的金属层电连接。
  14. 根据权利要求13所述的焊垫，其特征在于，以与形成所述金属塞相同的材料和方法来形成导电塞。
  15. 根据权利要求10所述的焊垫的形成方法，所述形成金属层的步骤包括：
    采用沉积工艺在焊垫的保护层或者介质层上淀积阻挡层；
    采用沉积工艺在阻挡层淀积中间金属层；
    采用沉积工艺在中间金属层上淀积抗反射层；
    利用光刻胶刻印硅片，采用刻蚀工艺形成与焊垫形状一致的金属层。
  16. 根据权利要求15所述的焊垫的形成方法，其特征在于：所述阻挡层的材质为钛，所述中间金属层的材质为铝铜合金，所述抗反射层的材质为氮化钛。
  17. 根据权利要求10所述的方法，其特征在于：
    在所述焊垫的激光打孔区域形成依次穿透所述金属层和金属塞的激光孔。
  18. 根据权利要求10所述的方法，其特征在于：重复步骤(b)至步骤(d)以形成多个金属层和介质层。
PCT/CN2016/102136 2015-12-29 2016-10-14 焊垫、包括焊垫的半导体芯片及形成方法 WO2017113932A1 (zh)

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