TWI588962B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI588962B
TWI588962B TW102130690A TW102130690A TWI588962B TW I588962 B TWI588962 B TW I588962B TW 102130690 A TW102130690 A TW 102130690A TW 102130690 A TW102130690 A TW 102130690A TW I588962 B TWI588962 B TW I588962B
Authority
TW
Taiwan
Prior art keywords
electrodes
region
insulating film
electrode
diameter
Prior art date
Application number
TW102130690A
Other languages
English (en)
Other versions
TW201419483A (zh
Inventor
北尾良平
土屋泰章
Original Assignee
瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 瑞薩電子股份有限公司 filed Critical 瑞薩電子股份有限公司
Publication of TW201419483A publication Critical patent/TW201419483A/zh
Application granted granted Critical
Publication of TWI588962B publication Critical patent/TWI588962B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05176—Ruthenium [Ru] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05657—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/145—Material
    • H01L2224/14505—Bump connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體裝置及其製造方法
本發明係關於一種半導體裝置及其製造技術，例如可適合利用於三維多功能器件之製造中必要之矽穿孔(Through Silicon Via：TSV)技術。
作為用以實現三維多功能器件之重要之技術有TSV技術。TSV技術係形成於厚度方向上垂直地貫通半導體基板之貫通電極之技術。
例如日本專利特開2005-294582號公報(專利文獻1)中，揭示一種包含含有小徑插頭與大徑插頭之貫通電極之半導體裝置。自矽(Si)基板突出之小徑插頭之突出部(下表面)貫入至大徑插頭之上表面，小徑插頭之上表面與第1配線連接。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2005-294582號公報
若於矽(Si)基板上形成自其主面朝與主面為相反側之背面貫通之貫通電極，則由於構成貫通電極之金屬導電體與矽(Si)之熱膨脹係數之不同，而會導致貫通電極周邊之矽(Si)基板上產生應變。因此，於 貫通電極周邊，會產生半導體元件之配置受到限制之區域(排除區域(keep out zone))。又，於貫通電極之正上方，無法配置複數個信號配線，故而於配線佈局上產生制約。此種問題成為推進採用有TSV技術之半導體裝置之高積體化方面之弊病。
其他課題與新穎之特徵可根據本說明書之記述及隨附圖式而明確瞭解。
根據一實施形態，使貫通電極包含形成於半導體基板之主面側之小徑貫通電極、與形成於半導體基板之背面側之大徑貫通電極，且以使俯視時小徑貫通電極之中心位置與大徑貫通電極之中心位置不一致之方式，而於俯視時將小徑貫通電極配置於大徑貫通電極之內側。
根據一實施形態，可實現採用有TSV技術之半導體裝置之高積體化。
ATSV、ATSV1、ATSV2‧‧‧TSV形成區域
B1、B2‧‧‧障壁金屬膜
BM、BM1、BM1c、BM1d、BM2、BM3‧‧‧障壁金屬膜
BP‧‧‧障壁金屬膜
CB‧‧‧銅凸塊
CE‧‧‧連接電極(插頭)
CL‧‧‧接著層
CN‧‧‧連接孔
CP1、CP2‧‧‧鍍銅膜
CS‧‧‧銅片層
GE‧‧‧閘極電極
GH‧‧‧玻璃支持體
GI‧‧‧閘極絕緣膜
I1、I2‧‧‧絕緣膜
IF1、IF1c、IF1d‧‧‧第1絕緣膜
IF2‧‧‧第2絕緣膜
IF3‧‧‧第3絕緣膜
IN‧‧‧氮化矽膜
IO‧‧‧氧化矽膜
IR‧‧‧分離部
IL‧‧‧絕緣膜
ILD、ILD1、ILD2、ILD3‧‧‧層間絕緣膜
KOZ‧‧‧排除區域
M1、M2、M6‧‧‧配線
MC、MCd‧‧‧連接墊
PW‧‧‧p型井
RB‧‧‧背面凸塊
RS‧‧‧密封樹脂
S1‧‧‧主面(表面，第1主面)
S2‧‧‧背面(第2主面)
SB‧‧‧外部端子(焊球)
SC‧‧‧半導體晶片(半導體裝置)
SD‧‧‧n型半導體區域
SIF‧‧‧終止絕緣膜
SL‧‧‧側壁
SW‧‧‧半導體基板
TA‧‧‧配線形成用之槽
TB‧‧‧連接孔
TE、TEa、TEb、TEc‧‧‧貫通電極
TE1、TE1a、TE1b、TE1c、TE1d‧‧‧小徑貫通電極(第1貫通電極)
TE2、TE2a、TE2b‧‧‧大徑貫通電極(第2貫通電極)
TE3‧‧‧連接電極
TRa‧‧‧配線形成用之槽
TRb‧‧‧連接墊形成用之槽
VI‧‧‧通孔(貫通孔、連接孔、開口部)
VI1、VI1c‧‧‧小徑通孔(貫通孔、連接孔、開口部；第1通孔)
VI2‧‧‧大徑通孔(貫通孔、連接孔、開口部；第2通孔)
VO‧‧‧開口部
圖1係實施形態1之包含TSV之半導體裝置之主要部分剖面圖。
圖2係實施形態1之半導體裝置之主要部分後視圖。
圖3係將實施形態1之半導體裝置之製造步驟中之半導體裝置之一部分放大表示之主要部分剖面圖。
圖4係繼圖3後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖5係繼圖4後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖6係繼圖5後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖7係繼圖6後之半導體裝置之製造步驟中之與圖3相同部位之主 要部分剖面圖。
圖8係繼圖7後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖9係繼圖8後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖10係繼圖9後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖11係繼圖10後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖12係繼圖11後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖13係繼圖12後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖14係繼圖13後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖15係繼圖14後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖16係繼圖15後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖17係繼圖16後之半導體裝置之製造步驟中之與圖3相同部位之主要部分剖面圖。
圖18(a)及(b)分別係說明實施形態1之第1變化例之小徑貫通電極及大徑貫通電極之配置之主要部分俯視圖。
圖19係實施形態1之第2變化例之包含TSV之半導體裝置之主要部分剖面圖。
圖20係實施形態1之第3變化例之包含TSV之半導體裝置之主要部 分剖面圖。
圖21係說明俯視實施形態2之TSV形成區域時之小徑貫通電極及大徑貫通電極之配置之主要部分俯視圖。
圖22係對俯視由本發明者等人比較研討之TSV形成區域時之小徑貫通電極及大徑貫通電極之配置進行說明之主要部分俯視圖。
圖23係對由本發明者等人比較研討之貫通電極之製造步驟進行說明之半導體裝置之主要部分剖面圖。
於以下之實施形態中，為方便起見，於必要時，分割為複數個部分或實施形態進行說明，但除特別明示之情形外，其等並非係相互無關者，一者係另一者之一部分或全部之變化例、詳細情形、補充說明等之關係。
又，於以下之實施形態中，於提及要素之數目等(包含個數、數值、量、範圍等)之情形時，除特別明示之情形及原理上明確限定為特定之數目情形等之外，並非限定於上述特定之數目，可為特定之數目以上亦可為其以下。
又，於以下之實施形態中，其構成要素(亦包含要素步驟等)除特別明示之情形及原理上明確認為為必需之情形等之外，當然未必為必需者。
又，於提及「包含A」、「由A構成」、「具有A」、「含有A」時，除特別明示僅為該要素之意旨之情形等之外，當然並不排除此外之要素。同樣地，於以下之實施形態中，於提及構成要素等之形狀、位置關係等時，除特別明示之情形及原理上明確認為並非如此之情形等之外，實質上包含與其形狀等近似或類似者等。此情形對於上述數值及範圍亦為相同。
又，於以下之實施形態中使用之圖式中，即便為俯視圖，為了 容易看清圖式有時亦會附上影線。又，於以下之實施形態時，於提及晶圓時，主要指Si(Silicon)單晶晶圓，但並非僅如此，而是指於其上用以形成SOI(Silicon On Insulator，矽絕緣體)晶圓、積體電路之絕緣膜基板等。其形狀亦並非僅為圓形或大致圓形，亦包含正方形、長方形等。
又，於用以說明以下實施形態之所有圖式中，具有相同功能者原則上標註相同之符號，省略其重複之說明。以下，根據圖式而詳細地說明實施形態。
(由本發明者等人而研討之TSV技術)
為了使本實施形態之採用有TSV技術之半導體裝置更為明確，對經本發明者等人比較研討後之半導體裝置之課題進行說明。
首先，使用圖23簡單地說明經本發明者等人研討後之中通孔(via-middle)方式之貫通電極之製造步驟之一例。圖23係說明貫通電極之製造步驟之半導體裝置之主要部分剖面圖。
例如準備包含單晶矽(Si)之半導體基板(稱為晶圓之平面大致圓形狀之半導體之薄板)SW。雖省略圖示，但於半導體基板SW之主面(表面、第1主面)S1上形成有複數個半導體元件。然後，以覆蓋該等複數個半導體元件之方式，於半導體基板SW之主面S1上形成層間絕緣膜ILD。
其次，藉由將光阻圖案作為遮罩之乾式蝕刻，而於形成有貫通電極之區域(未形成複數個半導體元件之區域)上，依序加工層間絕緣膜ILD及半導體基板SW而形成通孔(貫通孔、連接孔、開口部)VI。其後，於通孔VI之內部，介隔包含氧化矽(SiO2)之絕緣膜I1及包含鉭(Ta)等之障壁金屬膜BM而埋入鍍銅(Cu)膜，形成包含銅(Cu)膜之貫通電極TE。
其次，形成第1層之配線M1、及連接墊MC，該連接墊MC與第1 層之配線M1為同一層，且與貫通電極TE連接。其後，形成第2層之配線M2及進而形成上層之配線之後，與最上層之配線連接而形成銅(Cu)凸塊CB，且與銅(Cu)凸塊CB連接而形成外部端子SB。
其次，對與半導體基板SW之主面S1為相反側之背面(第2主面)S2進行研削、研磨或回蝕。藉此，削薄半導體基板SW之厚度，進而使被絕緣膜I1及障壁金屬膜BM覆蓋之貫通電極TE之底部自半導體基板SW之背面S2突出。繼而，以覆蓋自半導體基板SW之背面S2突出、且被絕緣膜I1及障壁金屬膜BM覆蓋之貫通電極TE之底部之方式，而於半導體基板SW之背面S2上形成絕緣膜I2。
其次，藉由CMP(Chemical Mechanical Polishing，化學機械研磨)法而研磨覆蓋貫通電極TE之底部之絕緣膜I2、絕緣膜I1及障壁金屬膜BM，使貫通電極TE之下表面露出。
<課題1>
若於半導體基板SW上形成自其主面S1朝與主面S1為相反側之背面S2而貫通之貫通電極TE，則由於構成貫通電極TE之銅(Cu)與構成半導體基板SW之矽(Si)之熱膨脹係數之不同，而會導致貫通電極TE周邊之半導體基板SW上產生應變。因此，可配置半導體元件之區域受到限制。例如於半導體基板SW上形成有口徑為5μm之通孔VI之情形時，自該通孔VI之外周起之1μm左右之範圍成為半導體元件之配置受到限制之區域(排除區域)。此半導體元件之配置受到限制之區域(排除區域)隨著通孔VI之口徑變大，即，隨著埋入至通孔VI內部之銅(Cu)之體積增加而變廣。
又，於貫通電極TE之正上方，配置有與貫通電極TE連接之連接墊MC，故而無法配置複數個信號配線。因此，於配線佈局方面產生制約。
為了縮小半導體元件之配置受到限制之區域(排除區域)，或為了 擴大可配置複數個信號配線之區域，可縮小通孔VI之口徑以減小貫通電極TE之體積。然而，於通孔VI之深度為相同之情形時，口徑較小之通孔VI與口徑較大之通孔VI相比，形成於半導體基板SW上之通孔VI之縱橫比(通孔之深度/通孔之口徑)變高。因此，若縮小通孔VI之口徑，則會產生於通孔VI之內部難以埋設鍍銅(Cu)膜之問題。
<課題2>
於加工半導體基板SW之背面S2而使半導體基板SW之厚度變薄時，擔心將覆蓋貫通電極TE之下表面之絕緣膜I1之一部分去除，而使貫通電極TE之下表面露出。若貫通電極TE之下表面露出，則構成貫通電極TE之銅(Cu)會自半導體基板SW之背面S2朝半導體基板SW內擴散。其結果為，由銅(Cu)污染而導致形成於半導體基板SW之主面S1上之半導體元件之動作特性改變。
<課題3>
又，本發明者等人亦對後通孔、背通孔(via-last、via-back)方式(於半導體基板之主面側形成半導體元件及多層配線之後，自半導體基板之背面側而於半導體基板上形成通孔，且於通孔之內部埋設貫通電極之方式)之貫通電極之製造步驟進行了研討。
然而，於半導體基板上形成上述通孔時，存在形成於半導體基板之主面側上之多層配線被蝕刻之危險性。
以上，如所說明般，於採用有TSV技術之半導體裝置中，必須使因配置貫通電極而受到制約之半導體元件之形成區域及配線之配置區域為最小。又，必須避免於貫通電極之製造步驟中產生之銅(Cu)污染等之問題。
再者，根據本發明者等人之研討而明確瞭解，如上述之專利文獻1般，僅憑使貫通電極僅包含小徑插頭與大徑插頭，而尤其難以避免因貫通電極周邊之矽(Si)基板上產生之應變而導致之排除區域之問 題。
(實施形態1)
≪半導體裝置≫
使用圖1及圖2說明本實施形態1之包含TSV之半導體裝置。圖1係半導體裝置之主要部分剖面圖，圖2係半導體裝置之主要部分後視圖。
半導體裝置(半導體晶片)中，將形成有場效電晶體、電阻元件及電容元件等各種半導體元件之區域(以下，稱為元件形成區域(第2區域))、與形成有複數個貫通電極之區域(以下，稱為TSV形成區域(第1區域))設置於互不相同之區域上。圖1中，例示有形成於元件形成區域上之各種半導體元件中之代表場效電晶體之n通道型之MISFET(Metal Insulator Semiconductor Field Effect Transistor，金屬絕緣體半導體場效電晶體)。又，於以下之說明中，將n通道型之MISFET簡略記為nMISFET。
首先，使用圖1對形成於元件形成區域上之nMISFET之構成進行說明。
如圖1所示，於元件形成區域之半導體基板SW之主面(表面、第1主面)S1上，形成有於分離槽之內部埋入有絕緣膜之分離部IR，藉由該分離部IR而規定形成有nMISFET之活性區域。半導體基板SW之厚度例如為50μm左右。於半導體基板SW之主面S1上形成有p型井PW，於形成有該p型井PW之區域上形成有nMISFET。於半導體基板SW之主面S1上介隔nMISFET之閘極絕緣膜GI而形成有閘極電極GE。閘極絕緣膜GI例如包含藉由熱氧化法而形成之氧化矽(SiO2)，閘極電極GE例如包含藉由CVD(Chemical Vapor Deposition，化學氣相沈積)法而形成之多晶矽(Si)。
於nMISFET之閘極電極GE之側面上形成有側壁SL。該側壁SL例 如包含氧化矽(SiO2)或氮化矽(Si3N4)。又，於nMISFET之閘極電極GE之兩側之p型井PW上形成有夾持通道區域而作為源極、汲極發揮功能之n型半導體區域SD。
進而，nMISFET藉由終止絕緣膜SIF及層間絕緣膜ILD1而覆蓋。終止絕緣膜SIF例如包含氮化矽(Si3N4)。又，層間絕緣膜ILD1例如包含氧化矽(SiO2)，且其表面得以平坦化。於終止絕緣膜SIF及層間絕緣膜ILD1上形成有到達閘極電極GE之連接孔(省略圖示)及到達n型半導體區域SD之連接孔CN。連接孔CN為柱狀，其直徑設定為與第1層之配線M1之線寬為相同，或小於第1層之配線M1之線寬，例如為0.06μm左右。於連接孔CN之內部，介隔障壁金屬膜BP而形成有由金屬形成之連接電極(插頭)CE。
於連接電極CE上，與連接電極CE連接並藉由單鑲嵌(Single Damascene)法而形成例如以銅(Cu)膜為主導體之第1層之配線M1。即，第1層之配線M1係藉由在堆積於連接電極CE及層間絕緣膜ILD1上之層間絕緣膜ILD2上形成配線形成用之槽TRa，且於其內部埋入銅(Cu)膜而形成。在配線形成用之槽TRa之內壁與銅(Cu)膜之間形成有障壁金屬膜。第1層之配線M1之線寬例如為0.1μm左右。
進而，於第1層之配線M1上，經由連接構件而與第1層之配線M1連接並藉由雙鑲嵌(Dual Damascene)法而形成例如以銅(Cu)膜為主導體之第2層之配線M2。即，第2層之配線M2係藉由在堆積於第1層之配線M1及層間絕緣膜ILD2上之層間絕緣膜ILD3上形成配線形成用之槽TA，進而於連結配線形成用之槽TA與第1層之配線M1之部分上形成連接孔TB，且於該等之內部埋入銅(Cu)膜而形成。在連接孔TB之內部形成與第2層之配線M2形成為一體之連接構件。在配線形成用之槽TA及連接孔TB各自之內壁與銅(Cu)膜之間形成有障壁金屬膜。再者，第2層之配線M2與第1層之配線M1同樣地，亦可藉由單鑲嵌法而 形成。
進而，於第2層之配線M2上，形成有上層之配線，且以覆蓋最上層之配線(實施形態1中為第6層之配線M6)之方式而形成絕緣膜IL及密封樹脂RS。於該等絕緣膜IL及密封樹脂RS上，形成到達第6層之配線M6之開口部VO，於該開口部VO之內部，與第6層之配線M6連接而形成銅(Cu)凸塊CB，進而與銅(Cu)凸塊CB連接而形成半球狀之外部端子(焊球)SB。
再者，實施形態1中，例示有6層之配線(配線M1~配線M6)，但並不限定於此。亦可為5層以下之配線或7層以上之配線，與最上層之配線連接而形成上述銅(Cu)凸塊CB及外部端子SB。
其次，使用圖1及圖2對形成於TSV形成區域上之TSV之構成進行說明。
如圖1所示，於TSV形成區域之半導體基板SW、終止絕緣膜SIF及層間絕緣膜ILD1上，形成有於厚度方向上貫通該等之通孔(貫通孔、連接孔、開口部)。
該通孔包含：小徑通孔(貫通孔、連接孔、開口部；第1通孔)VI1；及具有口徑大於小徑通孔VI1之口徑(直徑、內徑)之大徑通孔(貫通孔、連接孔、開口部；第2通孔)VI2；於半導體基板SW之主面S1側上配置有小徑通孔VI1，於半導體基板SW之背面(第2主面)S2側配置有大徑通孔VI2。即，小徑通孔VI1係自層間絕緣膜ILD1及終止絕緣膜SIF各自之上表面朝下表面貫通，進而自半導體基板SW之主面S1而形成為特定之深度，大徑通孔VI2係自半導體基板SW之背面S2而形成為特定之深度。
小徑通孔VI1之口徑(第1口徑)例如為2μm左右，其深度例如為10μm左右。大徑通孔VI2之口徑(第2口徑)例如為10μm左右，其深度例如為43μm左右。
又，於小徑通孔VI1之側面上，例如形成有包含氧化矽(SiO2)之第1絕緣膜IF1。進而，於小徑通孔VI1之內部，介隔障壁金屬膜BM1而形成有包含鍍銅(Cu)膜之小徑貫通電極(第1貫通電極)TE1。第1絕緣膜IF1係作為防止來自小徑貫通電極TE1之金屬污染之保護膜而發揮功能，亦發揮使小徑貫通電極TE1與半導體基板SW絕緣分離之功能。第1絕緣膜IF1之厚度例如為0.1μm左右。障壁金屬膜BM1例如係鉭(Ta)膜，其厚度例如為10nm左右。
又，於大徑通孔VI2之側面上，例如形成有包含氧化矽(SiO2)之第2絕緣膜IF2。進而，於大徑通孔VI2之內部，介隔障壁金屬膜BM2而形成有包含鍍銅(Cu)膜之大徑貫通電極(第2貫通電極)TE2。第2絕緣膜IF2係作為防止來自大徑貫通電極TE2之金屬污染之保護膜而發揮功能，亦發揮使大徑貫通電極TE2與半導體基板SW絕緣分離之功能。第2絕緣膜IF2之厚度例如為0.2μm左右。障壁金屬膜BM2例如係鉭(Ta)膜，其厚度例如為25nm左右。
小徑貫通電極TE1之下表面(半導體基板SW之背面S2側之面)係位於較大徑通孔VI2之底面更靠半導體基板SW之背面S2側。即，小徑貫通電極TE1之一部分朝大徑通孔VI2內突出。
將鉭(Ta)膜例示作為障壁金屬膜BM1、BM2，但並不限定於此，例如亦可使用鈦(Ti)膜、鈷(Co)膜、釕(Ru)膜、氮化鈦(TiN)膜或氮化鉭(TaN)膜等。
貫通電極包含小徑貫通電極TE1與大徑貫通電極TE2，小徑貫通電極TE1之下表面(半導體基板SW之背面S2側之面)與大徑貫通電極TE2之上表面(半導體基板SW之主面S1側之面)係經由障壁金屬膜BM1、BM2而電性連接。
然而，與半導體基板SW之主面S1平行之面上之小徑貫通電極TE1之平面面積及直徑(第1徑)分別小於與半導體基板SW之主面S1平 行之面上之大徑貫通電極TE2之平面面積及直徑(第2徑)。而且，於俯視時將小徑貫通電極TE1配置於大徑貫通電極TE2之內側，且於俯視時小徑貫通電極TE1之中心位置(圖1中以單點虛線表示之中心1)與大徑貫通電極TE2之中心位置(圖1中以單點虛線表示之中心2)不一致。即，於俯視時小徑貫通電極TE1之中心位置自大徑貫通電極TE2之中心位置離開。
如上所述，由於構成小徑貫通電極TE1及大徑貫通電極TE2之銅(Cu)與構成半導體基板SW之矽(Si)之熱膨脹係數之不同，而會導致小徑貫通電極TE1及大徑貫通電極TE2周邊之半導體基板SW上產生應變。然而，於半導體基板SW之主面S1側，形成有直徑小於大徑貫通電極TE2、即體積小於大徑貫通電極TE2之小徑貫通電極TE1。藉此，與在半導體基板SW之主面S1側亦形成有大徑貫通電極TE2之情形相比(參照上述之圖23)，於半導體基板SW之主面S1側產生應變之範圍變小，又，貫通電極佔據之區域變小。
由此，實施形態1中，受到半導體基板SW之應變之影響之區域(半導體元件之配置受到限制之區域(排除區域))變小，故而受到半導體基板SW之應變之影響之區域變為越小之區域，則可配置半導體元件之區域可越大。進而，形成有小徑貫通電極TE1之位置可在可與大徑貫通電極TE2連接之範圍內調整，故而可配合半導體元件之配置而設定小徑貫通電極TE1之位置。由此，可實現半導體元件之高積體化，且半導體元件之配置之自由度亦變高。
又，於半導體基板SW之主面S1側貫通電極(小徑貫通電極TE1)佔據之區域變小可使與其連接之連接墊MC之平面面積亦變小，故而可配置第1層之配線M1之區域變大，第1層之配線M1之配置之自由度變高。
將小徑貫通電極TE1之上表面(半導體基板SW之主面S1側之面)與 和第1層之配線M1為同一層之連接墊MC經由障壁金屬膜而連接。連接墊MC係藉由於層間絕緣膜ILD2上形成連接墊形成用之槽TRb，且於其內部埋入銅(Cu)膜而形成。
於實施形態1中，例示有連接墊MC作為貫通電極(小徑貫通電極TE1)之上表面連接之層，但並不限定於此，亦可為包含與第1層之配線M1為同一層之配線(例如形成為條紋狀或格子狀之配線)。
於半導體基板SW之背面S2上，形成有絕緣膜(第3絕緣膜)IF3。該絕緣膜IF3亦係作為防止來自半導體基板SW之背面S2之金屬污染之保護膜而發揮功能。絕緣膜IF3例如係氮化矽(Si3N4)膜、氧化矽(SiO2)膜、或氮化矽(Si3N4)膜與氧化矽(SiO2)膜之積層膜。
進而，於半導體基板SW之背面S2上，露出有大徑貫通電極TE2之下表面(半導體基板SW之背面S2側之面)。與該大徑貫通電極TE2之下表面連接而形成障壁金屬膜BM3，與該障壁金屬膜BM3連接而形成銅(Cu)片層CS及背面凸塊RB。障壁金屬膜BM3例如係鈦(Ti)膜、鉭(Ta)膜、鈷(Co)膜、釕(Ru)膜、氮化鈦(TiN)膜或氮化鉭(TaN)膜等。又，背面凸塊RB包含自銅(Cu)片層CS側將銅(Cu)、鎳(Ni)及Au(金)依序成膜而成之積層膜。
形成有複數個包含小徑貫通電極TE1與大徑貫通電極TE2之貫通電極TE之區域之大小係根據規格而定，以便保持與記憶體等通用品之連接。例如圖2所示，於縱6mm×橫6mm之尺寸之半導體晶片(半導體裝置)SC上，於半導體晶片SC之中央部上，配置有4個TSV形成區域ATSV，其上以40μm間距將貫通電極配置為縱向50個、橫向6個。即，半導體晶片SC之中央部係形成有複數個貫通電極之TSV形成區域ATSV，除此以外之區域成為形成有複數個半導體元件之元件形成區域。再者，圖2中，於半導體晶片SC之中央部上設置有TSV形成區域ATSV，但並不限定於中央部。
又，亦可使形成於TSV形成區域ATSV上之複數個貫通電極並不全部包含於俯視時小徑貫通電極TE1之中心位置與大徑貫通電極TE2之中心位置不重疊之貫通電極。即，可使形成於TSV形成區域ATSV上之複數個貫通電極之全部之貫通電極包含俯視時小徑貫通電極TE1之中心位置與大徑貫通電極TE2之中心位置不重疊之貫通電極。或者，亦可使形成於TSV形成區域ATSV上之複數個貫通電極中之一部分貫通電極包含於俯視時小徑貫通電極TE1之中心位置與大徑貫通電極TE2之中心位置不重疊之貫通電極，且使其他部分之貫通電極包含於俯視時小徑貫通電極TE1之中心位置與大徑貫通電極TE2之中心位置重疊之貫通電極。
≪半導體裝置之製造方法≫
其次，使用圖3~圖17，對本實施形態1之採用有TSV技術之半導體裝置之製造方法按步驟順序進行說明。圖3~圖17係半導體裝置之製造步驟中之半導體裝置之主要部分剖面圖，顯示元件形成區域之一部分及TSV形成區域之一部分。又，於圖3~圖17之元件形成區域上，例示有nMISFET作為半導體元件。又，於半導體裝置上，例如形成有100個以上之貫通電極，但為方便起見，於圖3~圖17中記載有包含小徑貫通電極及大徑貫通電極之1個貫通電極及其周邊部。
<半導體元件之形成步驟>
首先，如圖3所示，準備例如包含單晶矽(Si)之半導體基板(稱為晶圓之平面大致圓形狀之半導體之薄板)SW。半導體基板SW之厚度(第1厚度)例如為700μm左右。其次，於半導體基板SW之主面(表面、第1主面)之元件分離區域上形成包含絕緣膜之分離部IR。繼而，將顯示p型導電性之雜質向形成有nMISFET之區域之半導體基板SW中進行離子注入而形成p型井PW。
其次，於半導體基板SW之主面上形成nMISFET之閘極絕緣膜GI 之後，於閘極絕緣膜GI上形成nMISFET之閘極電極GE。繼而，於閘極電極GE之側面上形成側壁SL之後，將顯示n型導電性之雜質向閘極電極GE之兩側之p型井PW中進行離子注入，相對於閘極電極GE及側壁SL自對準地形成作為nMISFET之源極、汲極而發揮功能之n型半導體區域SD。
其次，於半導體基板SW之主面上依序形成終止絕緣膜SIF及層間絕緣膜ILD1。終止絕緣膜SIF於對層間絕緣膜ILD1進行加工時係成為蝕刻終止層之膜，且使用對層間絕緣膜ILD1具有蝕刻選擇比之材料。終止絕緣膜SIF例如係氮化矽(Si3N4)膜，層間絕緣膜ILD1例如係氧化矽(SiO2)膜。
其次，藉由將光阻圖案作為遮罩之乾式蝕刻，而依序加工層間絕緣膜ILD1及終止絕緣膜SIF，於元件形成區域上形成連接孔CN。連接孔CN係形成於為了使n型半導體區域SD上及閘極電極GE上等之nMISFET動作而必須進行電壓施加之部分上。
其次，於半導體基板SW之主面上，例如藉由濺鍍法而形成障壁金屬膜BP。障壁金屬膜BP例如係鈦(Ti)膜、鉭(Ta)膜、氮化鈦(TiN)膜或氮化鉭(TaN)膜等，其厚度例如為0.1μm左右。繼而，於障壁金屬膜BP上，例如藉由CVD法或濺鍍法而形成鎢(W)膜。繼而，藉由CMP法而去除連接孔CN之內部以外之區域之鎢(W)膜及障壁金屬膜BP，於連接孔CN之內部形成包含鎢(W)膜之連接電極(插頭)CE。
<小徑貫通電極之形成步驟>
其次，如圖4所示，將光阻圖案作為遮罩，依序蝕刻TSV形成區域之層間絕緣膜ILD1、終止絕緣膜SIF及半導體基板SW，於層間絕緣膜ILD1、終止絕緣膜SIF及半導體基板SW上形成小徑通孔(貫通孔、連接孔、開口部；第1通孔)VI1。小徑通孔VI1之口徑(直徑、內徑；第1口徑)例如為2μm左右，其深度例如為10μm左右。
其次，如圖5所示，於包含小徑通孔VI1之底面及側面之半導體基板SW之主面上形成第1絕緣膜IF1。第1絕緣膜IF1例如係藉由電漿CVD法而形成之氧化矽(SiO2)膜，其厚度例如為0.1μm左右。
其次，如圖6所示，於半導體基板SW之主面上(第1絕緣膜IF1上)形成障壁金屬膜BM1之後，於障壁金屬膜BM1上形成銅(Cu)之晶種層(省略圖示)，進而使用電解電鍍法而於晶種層上形成鍍銅(Cu)膜CP1。小徑通孔VI1之口徑較小，例如為2μm左右，但其縱橫比為5左右，故而可於小徑通孔VI1之內部藉由電解電鍍法而埋入鍍銅(Cu)膜CP1。障壁金屬膜BM1例如係鈦(Ti)膜、鉭(Ta)膜、鈷(Co)膜、釕(Ru)膜、氮化鈦(TiN)膜或氮化鉭(TaN)膜等，其厚度例如為10nm左右。
其次，如圖7所示，藉由CMP法而去除小徑通孔VI1之內部以外之區域之鍍銅(Cu)膜CP1、晶種層、障壁金屬膜BM1及第1絕緣膜IF1，於小徑通孔VI1之內部形成包含銅(Cu)膜之小徑貫通電極(第1貫通電極)TE1。
<多層配線及外部端子之形成步驟>
其次，如圖8所示，於半導體基板SW之主面側依序形成第1層之配線M1、連接墊MC、第2層之配線M2，銅(Cu)凸塊CB及外部端子(焊球)SB。
首先，藉由單鑲嵌法而於元件形成區域上形成第1層之配線M1，且於TSV形成區域上形成連接墊MC。
於半導體基板SW之主面上形成層間絕緣膜ILD2。層間絕緣膜ILD2例如係藉由電漿CVD法而形成之氧化矽(SiO2)膜。繼而，將光阻圖案作為遮罩而對層間絕緣膜ILD2進行乾式蝕刻，於元件形成區域之形成有第1層之配線M1之區域上，形成自層間絕緣膜ILD2之上表面朝下表面貫通且到達連接電極CE之配線形成用之槽TRa。同時，於TSV形成區域之形成有連接墊MC之區域上，形成自層間絕緣膜ILD2 之上表面朝下表面貫通且到達小徑貫通電極TE1之連接墊形成用之槽TRb。
繼而，於半導體基板SW之主面上形成障壁金屬膜B1。障壁金屬膜B1例如係鈦(Ti)膜、鉭(Ta)膜、氮化鈦(TiN)膜或氮化鉭(TaN)膜等。繼而，藉由CVD法或濺鍍法而於障壁金屬膜B1上形成銅(Cu)之晶種層(省略圖示)，進而使用電解電鍍法而於晶種層上形成鍍銅(Cu)膜(省略圖示)。藉由該鍍銅(Cu)膜而埋入配線形成用之槽TRa之內部及連接墊形成用之槽TRb之內部。
繼而，藉由CMP法而去除配線形成用之槽TRa之內部及連接墊形成用之槽TRb之內部以外之區域之鍍銅(Cu)膜、晶種層及障壁金屬膜B1。藉此，於配線形成用之槽TRa之內部，形成包含銅(Cu)膜之第1層之配線M1。同時，於連接墊形成用之槽TRb之內部，形成包含銅(Cu)膜之連接墊MC。再者，於實施形態1中，藉由電解電鍍法而形成構成第1層之配線M1及連接墊MC之銅(Cu)膜，但亦可藉由CVD法、濺鍍法或濺鍍回流法等而形成。
其次，藉由雙鑲嵌法而於元件形成區域及TSV形成區域上形成第2層之配線M2。
於半導體基板SW之主面上，例如藉由電漿CVD法而形成層間絕緣膜ILD3。層間絕緣膜ILD3係仿照其下層之層間絕緣膜ILD2、第1層之配線M1及連接墊MC各自之表面形狀而形成，該等之表面為大致平坦，故而層間絕緣膜ILD3之表面亦為大致平坦。繼而，將光阻圖案作為遮罩，對層間絕緣膜ILD3進行乾式蝕刻，於形成有第2層之配線M2之區域上形成配線形成用之槽TA。進而，於連結配線形成用之槽TA與第1層之配線M1之部分上形成到達第1層之配線M1之連接孔TB。同時，於連結配線形成用之槽TA與連接墊MC之部分上形成到達連接墊MC之連接孔TB。
繼而，於半導體基板SW之主面上形成障壁金屬膜B2之後，於障壁金屬膜B2上形成銅(Cu)之晶種層(省略圖示)，進而使用電解電鍍法而於晶種層上形成鍍銅(Cu)膜(省略圖示)。障壁金屬膜B2例如係鈦(Ti)膜、鉭(Ta)膜、氮化鈦(TiN)膜或氮化鉭(TaN)膜等之單層膜、或者將該等膜之若干個積層而成之積層膜。
繼而，藉由CMP法而去除配線形成用之槽TA及連接孔TB之內部以外之區域之鍍銅(Cu)膜、晶種層及障壁金屬膜B2，於配線形成用之槽TA之內部形成包含銅(Cu)膜之第2層之配線M2，且於連接孔TB之內部形成與第2層之配線M2形成為一體之連接構件。
其後，以與上述之第1層之配線M1或第2層之配線M2相同之方式，進而形成上層之配線，但省略此處之說明。
其次，形成銅(Cu)凸塊CB及外部端子(焊球)SB。
於半導體基板SW之主面側上，以覆蓋最上層之配線(例如上述之圖1所示之第6層之配線M6)之方式，形成絕緣膜(省略圖示)及密封樹脂RS。繼而，於絕緣膜及密封樹脂RS上，形成到達最上層之配線之開口部VO之後，使用電解電鍍法，以埋入於該開口部VO之方式而形成銅(Cu)凸塊CB。
繼而，將外部端子(焊球)SB連接於自開口部VO露出之銅(Cu)凸塊CB。外部端子SB例如係藉由以球供給法供給球狀之焊劑之後，實施熱處理而形成。
<大徑貫通電極之形成步驟>
其次，如圖9所示，於半導體基板SW之主面側，經由接著層CL而貼附玻璃支持體GH。
其次，如圖10所示，對半導體基板SW之與主面為相反側之背面(第2主面)進行研削、研磨或回蝕，使半導體基板SW之厚度(第2厚度)例如為50μm以下。此時，小徑貫通電極TE1並未自半導體基板SW之 背面突出。
其次，於半導體基板SW之背面上依序形成絕緣膜(圖1中以符號IF3表示之第3絕緣膜)、例如氮化矽(Si3N4)膜IN及氧化矽(SiO2)膜IO。該成膜必須於接著有玻璃支持體GH之接著層CL之耐熱溫度以下進行，故而氮化矽(Si3N4)膜IN及氧化矽(SiO2)膜IO例如以電漿CVD法或氣體團簇離子束(gas cluster ion beams)法等而形成。
其次，如圖11所示，將光阻圖案作為遮罩，自半導體基板SW之背面側依序蝕刻TSV形成區域之氧化矽(SiO2)膜IO、氮化矽(Si3N4)膜IN及半導體基板SW，於半導體基板SW上形成大徑通孔(貫通孔、連接孔、開口部；第2通孔)VI2。大徑通孔VI2之口徑(直徑、內徑；第2口徑)例如為10μm左右，其深度例如為43μm左右。
此時，被第1絕緣膜IF1及障壁金屬膜BM1覆蓋之小徑貫通電極TE1之一部分自大徑通孔VI2之底面之一部分突出。即，小徑貫通電極TE1之下表面位於較大徑通孔VI2之底面更靠半導體基板SW之背面側。又，於俯視時小徑通孔VI1之中心位置與大徑通孔VI2之中心位置不一致。即，於俯視時小徑通孔VI1之中心位置自大徑通孔VI2之中心位置離開。
其次，如圖12所示，以覆蓋大徑通孔VI2之底面及側面、以及自大徑通孔VI2之底面露出之小徑貫通電極TE1之一部分(被第1絕緣膜IF1及障壁金屬膜BM1覆蓋)之方式，於半導體基板SW之背面上形成第2絕緣膜IF2。第2絕緣膜IF2例如係電漿TEOS(Tetra Ethyl Ortho Silicate，正矽酸乙酯)膜，其厚度例如為0.2μm左右。
其次，如圖13所示，去除覆蓋小徑貫通電極TE1之下表面之第1絕緣膜IF1及第2絕緣膜IF2，使覆蓋小徑貫通電極TE1之下表面之障壁金屬膜BM1露出。
其次，如圖14所示，以覆蓋大徑通孔VI2之底面及側面、以及自 大徑通孔VI2之底面露出之小徑貫通電極TE1之一部分(被障壁金屬膜BM1覆蓋)之方式，於半導體基板SW之背面上形成障壁金屬膜BM2。繼而，於障壁金屬膜BM2上形成銅(Cu)之晶種層(省略圖示)，進而使用電解電鍍法而於晶種層上形成鍍銅(Cu)膜CP2。障壁金屬膜BM2例如係鈦(Ti)膜、鉭(Ta)膜、鈷(Co)膜、釕(Ru)膜、鎳(Ni)膜、氮化鈦(TiN)膜或氮化鉭(TaN)膜等之單層膜或者該等之積層膜。此處，記載使用有障壁金屬膜BM2之情形之實施形態1，但亦可代替障壁金屬膜BM2而使用具有防止銅(Cu)朝半導體基板SW之擴散之性能之絕緣膜，例如氮化矽(Si3N4)膜等。
其次，如圖15所示，藉由CMP法而去除大徑通孔VI2之內部以外之區域之鍍銅(Cu)膜CP2、晶種層及障壁金屬膜BM2，於大徑通孔VI2之內部形成包含銅(Cu)膜之大徑貫通電極TE2。此時，於半導體基板SW之背面上形成有氮化矽(Si3N4)膜IN，故而並未使半導體基板SW之背面露出。由此，可防止構成大徑貫通電極TE2之銅(Cu)朝半導體基板SW內之擴散，從而可抑制由銅(Cu)污染而導致之半導體元件之動作特性之改變。
其次，如圖16所示，與大徑貫通電極TE2之下表面連接而形成障壁金屬膜BM3、銅(Cu)片層CS及背面凸塊RB。障壁金屬膜BM3例如係鈦(Ti)膜、鉭(Ta)膜、鈷(Co)膜、釕(Ru)膜、氮化鈦(TiN)膜或氮化鉭(TaN)膜等。又，背面凸塊RB包含自銅(Cu)片層CS側將銅(Cu)、鎳(Ni)及Au(金)依序成膜而成之積層膜。
其次，如圖17所示，去除玻璃支持體GH及接著層CL。其後，將形成有半導體元件、貫通電極TE等之半導體基板SW沿切割線切割，將半導體裝置一個個地分割開。藉由以上之步驟而大致完成半導體裝置。
如此，根據實施形態1，使貫通電極包含小徑貫通電極TE1與大 徑貫通電極TE2，且於半導體基板SW之主面側配置小徑貫通電極TE1，藉此可取得以下之效果。
受到半導體基板SW之應變之影響之區域(半導體元件之配置受到制約之區域(排除區域))變小，故而受到半導體基板SW之應變之影響之區域變為越小之區域，則可配置半導體元件之區域變得越大。進而，形成有小徑貫通電極TE1之位置可在可與大徑貫通電極TE2連接之範圍內調整，故而可配合半導體元件之配置而設定小徑貫通電極TE1之位置。由此，可實現半導體元件之高積體化，且半導體元件之配置之自由度亦變高。
又，半導體基板SW之主面側之貫通電極(小徑貫通電極TE1)佔據之區域變小會使與其連接之連接墊MC之平面面積亦變小，故而可配置第1層之配線M1之區域變大，第1層之配線M1之配置之自由度亦變高。
又，於形成大徑貫通電極TE2時，半導體基板SW之背面始終藉由絕緣膜(氮化矽(Si3N4)膜IN等)而覆蓋，故而不會使半導體基板SW之背面露出。由此，不會使構成大徑貫通電極TE2之銅(Cu)自半導體基板SW之背面朝半導體基板SW內擴散，從而可防止由銅(Cu)污染而導致之半導體元件之動作特性之改變。
又，埋設大徑貫通電極TE2之大徑通孔VI2係自半導體基板SW之背面朝主面而形成，但大徑通孔VI2之底面並未到達半導體基板SW之主面，故而不存在對形成於半導體基板SW之主面側之多層配線進行蝕刻之危險性。
≪第1變化例≫
使用圖18說明實施形態1之第1變化例之貫通電極。圖18(a)及(b)分別係說明小徑貫通電極及大徑貫通電極之配置之主要部分俯視圖。
上述之圖1所示之半導體裝置中，1個貫通電極包含1個小徑貫通 電極TE1與1個大徑貫通電極TE2，但並不限定於此。1個貫通電極亦可包含1個大徑貫通電極與複數個小徑貫通電極。
圖18(a)中，例示包含2個小徑貫通電極TE1a與1個大徑貫通電極TE2a之1個貫通電極TEa。於俯視時小徑貫通電極TE1a之直徑小於大徑貫通電極TE2a之直徑，且小徑貫通電極TE1a位於大徑貫通電極TE2a之內側。又，小徑貫通電極TE1a之中心位置與大徑貫通電極TE2a之中心位置不一致。即，於俯視時小徑貫通電極TE1a之中心位置自大徑貫通電極TE2a之中心位置離開。
圖18(b)中，例示包含3個小徑貫通電極TE1b與1個大徑貫通電極TE2b之1個貫通電極TEb。於俯視時小徑貫通電極TE1b之直徑小於大徑貫通電極TE2b之直徑，且小徑貫通電極TE1b位於大徑貫通電極TE2b之內側。又，小徑貫通電極TE1b之中心位置與大徑貫通電極TE2b之中心位置不一致。即，於俯視時小徑貫通電極TE1b之中心位置自大徑貫通電極TE2b之中心位置離開。
如此，藉由形成複數個小徑貫通電極TE1a、TE1b，而較形成1個小徑貫通電極之情形，可降低貫通電極TEa、TEb之電阻。
≪第2變化例≫
使用圖19說明實施形態1之第2變化例之貫通電極。圖19係貫通電極之主要部分剖面圖。
於上述之圖1所示之半導體裝置中，使貫通電極包含：層間絕緣膜ILD1；埋設至形成於終止絕緣膜SIF及半導體基板SW上之小徑通孔VI1中之小徑貫通電極TE1；及埋設至形成於半導體基板SW上之大徑通孔VI2中之大徑貫通電極TE2；但並不限定於此。
例如圖19所示，亦可使貫通電極包含：埋設至形成於半導體基板SW上之小徑通孔VI1c中之小徑貫通電極TE1c；及埋設至形成於半導體基板SW上之大徑通孔VI2中之大徑貫通電極TE2。於該情形時， 藉由埋設至形成於層間絕緣膜ILD1及終止絕緣膜SIF上之連接孔CN中之連接電極TE3，而將連接墊MC與小徑貫通電極TE1c電性連接。
連接電極TE3係形成於層間絕緣膜ILD1及終止絕緣膜SIF上，且於俯視時具有第3徑，其一端經由障壁金屬膜而與連接墊MC連接，其另一端經由障壁金屬膜BP而與小徑貫通電極TE1c連接。小徑貫通電極TE1c係自半導體基板SW之主面側而形成於半導體基板SW上，且於俯視時具有第1徑，其一端經由障壁金屬膜BP而與連接電極TE3連接，其另一端經由障壁金屬膜BM1c、BM2而與大徑貫通電極TE2連接。又，大徑貫通電極TE2係自半導體基板SW之背面側而形成於半導體基板SW上，且於俯視時具有第2徑，其一端經由障壁金屬膜BM1c、BM2而與小徑貫通電極TE1c連接。此處，第1徑小於第2徑，第3徑小於第1徑。
可將小徑貫通電極TE1c及連接電極TE3例如以如下方式而形成。
首先，於半導體基板SW之主面側形成複數個半導體元件。
其次，對半導體基板SW進行蝕刻，於半導體基板SW上形成小徑通孔(貫通孔、連接孔、開口部；第1通孔)VI1c。繼而，於包含小徑通孔VI1c之底面及側面之半導體基板SW之主面上形成第1絕緣膜IF1c之後，於半導體基板SW之主面上(第1絕緣膜IF1c上)形成障壁金屬膜BM1c、銅(Cu)之晶種層及鍍銅(Cu)膜。繼而，去除小徑通孔VI1c之內部以外之區域之鍍銅(Cu)膜、晶種層、障壁金屬膜BM1c及第1絕緣膜IF1c，於小徑通孔VI1c之內部形成包含銅(Cu)膜之小徑貫通電極TE1c。
其次，於半導體基板SW之主面上依序形成終止絕緣膜SIF及層間絕緣膜ILD1。繼而，依序蝕刻層間絕緣膜ILD1及終止絕緣膜SIF，於元件形成區域及TSV形成區域上形成連接孔CN。繼而，於半導體基板SW之主面上形成障壁金屬膜BP及鎢(W)膜。
其次，藉由CMP法而去除連接孔CN之內部以外之區域之鎢(W)膜及障壁金屬膜BP，於元件形成區域上於連接孔CN之內部形成包含鎢(W)膜之連接電極CE，且於TSV形成區域上形成連接電極TE3。即，連接電極TE3係與將形成於元件形成區域上之nMISFET之閘極電極GE等與第1層之配線M1加以電性連接之連接電極CE同時形成。
如此，亦可於層間絕緣膜ILD1及終止絕緣膜SIF上不形成小徑貫通電極TE1c，而形成具有較小徑貫通電極TE1c之第2徑小之第3徑之連接電極TE3，且使用該連接電極TE3將連接墊MC與小徑貫通電極TE1c加以電性連接。藉此，與層間絕緣膜ILD1、終止絕緣膜SIF及半導體基板SW上形成小徑貫通電極TE1之情形(參照上述之圖1)相比，貫通電極於層間絕緣膜ILD1及終止絕緣膜SIF上佔據之區域變小。尤其連接電極TE3自身佔據之區域變小可使與連接電極TE3連接之連接墊MC之平面面積亦變小，故而可配置第1層之配線M1之區域變大，第1層之配線M1之配置之自由度變高。
≪第3變化例≫
使用圖20說明實施形態1之第3變化例之貫通電極。圖20係貫通電極之主要部分剖面圖。
上述之圖1所示之半導體裝置中，使小徑貫通電極TE1、大徑貫通電極TE2及連接墊MC包含互不相同之金屬導電體，將小徑貫通電極TE1之一端經由障壁金屬膜而與連接墊MC連接，且將與上述一端為相反側之另一端經由障壁金屬膜BM1、BM2而與大徑貫通電極TE2連接，但並不限定於此。
例如圖20所示，亦可將小徑貫通電極TE1d與連接墊MCd藉由同一金屬導電體而形成為一體。藉此，小徑貫通電極TE1d可與形成於元件形成區域上之第1層之配線M1同時形成。
可將小徑貫通電極TE1d及連接墊MCd例如以如下之方式而形 成。
首先，於半導體基板SW之主面側形成複數個半導體元件。繼而，於半導體基板SW之主面上依序形成終止絕緣膜SIF及層間絕緣膜ILD1之後，依序蝕刻終止絕緣膜SIF及層間絕緣膜ILD1，於元件形成區域上形成連接孔CN，且於連接孔CN之內部形成連接電極CE。
其次，於半導體基板SW之主面上形成層間絕緣膜ILD2之後，於元件形成區域之層間絕緣膜ILD2上形成配線形成用之槽TRa，且於TSV形成區域之層間絕緣膜ILD2形成連接墊形成用之槽TRb。進而，自連接墊形成用之槽TRb之底面之一部分依序蝕刻層間絕緣膜ILD1、終止絕緣膜SIF及半導體基板SW，形成小徑通孔VI1。
其次，於包含小徑通孔VI1、配線形成用之槽TRa及連接墊形成用之槽TRb各自之底面及側面之半導體基板SW之主面上形成第1絕緣膜IF1d之後，去除配線形成用之槽TRa之底面之第1絕緣膜IF1d。
其次，於半導體基板SW之主面上(第1絕緣膜IF1d上)形成障壁金屬膜BM1d、銅(Cu)之晶種層及鍍銅(Cu)膜。繼而，去除小徑通孔VI1、配線形成用之槽TRa及連接墊形成用之槽TRb各自之內部以外之區域之鍍銅(Cu)膜、晶種層、障壁金屬膜BM1d及第1絕緣膜IF1d。藉此，在配線形成用之槽TRa之內部形成包含銅(Cu)膜之第1層之配線M1之同時，將埋設至小徑通孔VI1之內部之包含銅(Cu)膜之小徑貫通電極TE1d、與埋設至連接墊形成用之槽TRb之內部之包含銅(Cu)膜之連接墊MCd形成為一體。
如此，與分別執行藉由與第1層之配線M1及連接墊MCd同時形成小徑貫通電極TE1d而將金屬導電體埋設至小徑通孔VI1中之步驟、與將金屬導電體埋設至配線形成用之槽TRa及連接墊形成用之槽TRb中之步驟的製造方法相比，可減少製造步驟數。
(實施形態2)
使用圖21及圖22說明本實施形態2之包含TSV之半導體裝置。圖21係說明俯視實施形態2之TSV形成區域時之小徑貫通電極及大徑貫通電極之配置的主要部分俯視圖。圖22係說明俯視由本發明者等人比較研討之TSV形成區域時之小徑貫通電極及大徑貫通電極之配置的主要部分俯視圖。
實際上，如使用上述實施形態1之圖2所說明般，在配置於半導體晶片SC之中央部上之TSV形成區域上，形成有數百個(例如50個×6個)貫通電極。然而，圖21及圖22中，為方便起見，記載有12個(4個×3個)貫通電極。
如圖21所示，於實施形態2之TSV形成區域ATSV1上，配置有複數個包含1個小徑貫通電極(影線所示之區域)TE1與1個大徑貫通電極TE2之貫通電極。而且，大徑貫通電極TE2彼此等間隔(例如40μm間距)地排列配置，於俯視時小徑貫通電極TE1之直徑小於大徑貫通電極TE2之直徑，且於俯視時小徑貫通電極TE1位於大徑貫通電極TE2之內側。
然而，TSV形成區域ATSV1上位於最外側之貫通電極中，於俯視時小徑貫通電極TE1之中心位置與大徑貫通電極TE2之中心位置不一致，小徑貫通電極TE1之中心位置自大徑貫通電極TE2之中心位置朝與TSV形成區域ATSV1之外周相反方向而移動。再者，上述以外之貫通電極中，於俯視時小徑貫通電極TE1之中心位置與大徑貫通電極TE2之中心位置一致。
於圖21中以虛線表示半導體元件之配置受到限制之區域(排除區域)KOZ。將TSV形成區域ATSV1上位於最外側之貫通電極之小徑貫通電極TE1配置於自TSV形成區域ATSV1之外周離開之方向上，故而半導體元件之配置受到限制之區域(排除區域)KOZ亦朝TSV形成區域ATSV1之內側移動。
作為比較例，圖22中表示將於俯視時小徑貫通電極TE1之中心位置與大徑貫通電極TE2之中心位置一致之貫通電極配置於整個區域上之TSV形成區域ATSV2。TSV形成區域ATSV2之大徑貫通電極TE2之配置與圖21所示之TSV形成區域ATSV1之大徑貫通電極TE2之配置為相同，但於TSV形成區域ATSV2上，半導體元件之配置受到限制之區域(排除區域)KOZ與大徑貫通電極TE2以同心圓狀擴展。因此，TSV形成區域ATSV2成為亦包含與大徑貫通電極TE2以同心圓狀擴展之半導體元件之配置受到限制之區域(排除區域)KOZ之區域。
圖21中，以單點虛線表示圖22所示之TSV形成區域ATSV2。可知實施形態2之TSV形成區域ATSV1之平面面積小於TSV形成區域ATSV2之平面面積。
如此，實施形態2中，藉由將位於TSV形成區域ATSV1之最外側之貫通電極之小徑貫通電極TE1配置於自TSV形成區域ATSV1之外周離開之方向上，而可使半導體元件之配置受到限制之區域(排除區域)KOZ朝TSV形成區域ATSV1之內側移動。藉此，TSV形成區域ATSV1之平面面積變小，且可使該平面面積減少之區域成為元件形成區域，故而可實現半導體元件之高積體化、或半導體晶片之小型化。
以上，根據實施形態具體地說明瞭由本發明者完成之發明，但本發明並不限定於上述實施形態，當然於不脫離其要旨之範圍內可進行種種變更。
BM1、BM2、BM3‧‧‧障壁金屬膜
BP‧‧‧障壁金屬膜
CB‧‧‧銅凸塊
CE‧‧‧連接電極(插頭)
CN‧‧‧連接孔
CS‧‧‧銅片層
GE‧‧‧閘極電極
GI‧‧‧閘極絕緣膜
IF1‧‧‧第1絕緣膜
IF2‧‧‧第2絕緣膜
IF3‧‧‧第3絕緣膜
IR‧‧‧分離部
IL‧‧‧絕緣膜
ILD1、ILD2、ILD3‧‧‧層間絕緣膜
M1、M2、M6‧‧‧配線
MC‧‧‧連接墊
PW‧‧‧p型井
RB‧‧‧背面凸塊
RS‧‧‧密封樹脂
S1‧‧‧主面(表面，第1主面)
S2‧‧‧背面(第2主面)
SB‧‧‧外部端子(焊球)
SD‧‧‧n型半導體區域
SIF‧‧‧終止絕緣膜
SL‧‧‧側壁
SW‧‧‧半導體基板
TA‧‧‧配線形成用之槽
TB‧‧‧連接孔
TE1‧‧‧小徑貫通電極(第1貫通電極)
TE2‧‧‧大徑貫通電極(第2貫通電極)
TRa‧‧‧配線形成用之槽
TRb‧‧‧連接墊形成用之槽
VI1‧‧‧小徑通孔(貫通孔、連接孔、開口部；第1通孔)
VI2‧‧‧大徑通孔(貫通孔、連接孔、開口部；第2通孔)
VO‧‧‧開口部

Claims (18)

  1. 一種半導體裝置，其係包含：第1區域，其中形成有自半導體基板之第1主面朝與上述第1主面為相反側之第2主面貫通之複數個貫通電極；及第2區域，其中於上述半導體基板之上述第1主面上形成有複數個半導體元件；上述複數個貫通電極之各個貫通電極包含：複數個第1貫通電極，其形成於上述半導體基板之上述第1主面側，且具有第1徑；及複數個第2貫通電極，其形成於上述半導體基板之上述第2主面側，且具有大於上述第1徑之第2徑；且於俯視時上述複數個第1貫通電極之各個係位於上述複數個第2貫通電極之各個之內側，且於俯視時上述複數個第1貫通電極之各個之中心位置係自上述複數個第2貫通電極之各個之中心位置離開；於俯視時，於上述第1區域中之上述複數個第2貫通電極係分別以相同間距配置；於俯視時，位於靠近上述第1區域之外周之上述複數個第1貫通電極之各個之上述中心位置係朝向上述第1區域之中心而配置。
  2. 如請求項1之半導體裝置，其中上述複數個貫通電極之全部或一部分之貫通電極包含1個上述第2貫通電極、及複數個上述第1貫通電極。
  3. 如請求項1之半導體裝置，其進而包含：層間絕緣膜，其以覆蓋上述複數個半導體元件之方式而形成 於上述半導體基板之上述第1主面上；及連接墊或配線，其形成於上述第1區域之上述層間絕緣膜上；且上述複數個第1貫通電極包含自上述層間絕緣膜之上表面朝下表面貫通之部分；上述複數個第1貫通電極之一端係與上述連接墊或上述配線連接；上述複數個第1貫通電極之與上述一端為相反側之另一端係與上述複數個第2貫通電極連接。
  4. 如請求項1之半導體裝置，其進而包含：層間絕緣膜，其以覆蓋上述複數個半導體元件之方式而形成於上述半導體基板之上述第1主面上；及連接電極，其自上表面朝下表面貫通上述第1區域之上述層間絕緣膜；且上述複數個第1貫通電極之一端係與上述連接電極連接；上述複數個第1貫通電極之與上述一端為相反側之另一端係與上述複數個第2貫通電極連接。
  5. 如請求項1之半導體裝置，其進而包含：層間絕緣膜，其以覆蓋上述複數個半導體元件之方式而形成於上述半導體基板之上述第1主面上；連接墊或第1配線，其形成於上述第1區域之上述層間絕緣膜上；及第2配線，其形成於上述第2區域之上述層間絕緣膜上；且上述複數個第1貫通電極包含上述層間絕緣膜之自上表面朝下表面貫通之部分；上述複數個第1貫通電極與上述連接墊或上述第1配線係藉由 同一金屬導電體而形成為一體。
  6. 如請求項5之半導體裝置，其中上述複數個第1貫通電極及上述連接墊、或上述複數個第1貫通電極及上述第1配線係藉由上述金屬導電體而形成於上述第1區域上，上述第2配線係藉由上述金屬導電體而形成於上述第2區域上。
  7. 如請求項1之半導體裝置，其中在上述半導體基板與上述複數個第1貫通電極之間，自上述半導體基板側形成有第1絕緣膜及第1障壁金屬膜；在上述半導體基板與上述複數個第2貫通電極之間，自上述半導體基板側形成有與上述第1絕緣膜不同之第2絕緣膜及與上述第1障壁金屬膜不同之第2障壁金屬膜。
  8. 如請求項1之半導體裝置，其中在上述複數個第1貫通電極與上述複數個第2貫通電極之間，形成有障壁金屬膜。
  9. 如請求項1之半導體裝置，其中於俯視時，位於靠近上述第1區域之外周之上述複數個第1貫通電極之各個之上述中心位置係自對應之上述複數個第2貫通電極之各個之中心位置偏移，該對應之上述複數個第2貫通電極之各個係圍繞位於靠近上述第1區域之外周之上述複數個第1貫通電極之各個。
  10. 如請求項1之半導體裝置，其中於俯視時，位於靠近上述第1區域之外周之上述複數個第1貫通電極中之1個之上述中心位置係自對應之上述複數個第2貫通電極中之1個之中心位置偏移，該對應之上述複數個第2貫通電極之1個係圍繞位於靠近上述第1區域之外周之上述複數個第1貫 通電極之1個。
  11. 如請求項1之半導體裝置，其中相對於對應之上述複數個第2貫通電極之各個之中心位置，位於靠近上述第1區域之外周之上述複數個第1貫通電極中之各個之上述中心位置係朝向上述第1區域之上述中心移動，該對應之上述複數個第2貫通電極之各個係圍繞位於靠近上述第1區域之外周之上述複數個第1貫通電極之各個。
  12. 如請求項1之半導體裝置，其中相對於對應之上述複數個第2貫通電極之各個之中心位置，位於靠近上述第1區域之外周之上述複數個第1貫通電極中之各個之上述中心位置係於與第1區域之外周相反方向而朝向上述第1區域之上述中心移動，該對應之上述複數個第2貫通電極之各個係圍繞位於靠近上述第1區域之外周之上述複數個第1貫通電極之各個。
  13. 如請求項1之半導體裝置，其中於俯視時，位於相鄰於上述第1區域之上述中心且自上述第1區域之外周離開之上述複數個第1貫通電極中之1個之中心位置係與對應之上述複數個第2貫通電極之1個之中心位置重疊，該對應之上述複數個第2貫通電極之1個係圍繞相鄰於上述第1區域之上述中心且自上述第1區域之外周離開之上述複數個第1貫通電極中之1個。
  14. 如請求項1之半導體裝置，其中於俯視時，位於相鄰於上述第1區域之上述中心且自上述第1區域之外周離開之上述複數個第1貫通電極中之各個之中心位置係與對應之上述複數個第2貫通電極之1個之中心位置重疊，該對應之上述複數個第2貫通電極之1個係圍繞相鄰於上述第1區域 之上述中心且自上述第1區域之外周離開之上述複數個第1貫通電極中之各個。
  15. 一種半導體裝置之製造方法，其包含以下之步驟：於該半導體裝置之第1區域中，(a)於具有第1厚度之半導體基板之第1主面上，形成具有第1口徑之第1通孔；(b)於上述第1通孔之底面及側面形成第1絕緣膜之後，於上述第1通孔之內部介隔第1障壁金屬膜而形成複數個第1貫通電極；(c)於上述步驟(b)之後，對上述半導體基板自與上述第1主面為相反側之第2主面進行加工，使上述半導體基板之上述第1厚度成為較上述第1厚度薄之第2厚度；(d)於上述步驟(c)之後，於上述半導體基板之上述第2主面上形成第3絕緣膜；(e)於上述步驟(d)之後，依序加工上述第3絕緣膜及上述半導體基板，於上述半導體基板之上述第2主面上，形成具有較上述第1口徑大之第2口徑之第2通孔，且使被上述第1絕緣膜及上述第1障壁金屬膜覆蓋之上述複數個第1貫通電極之一部分自上述第2通孔之底面突出；(f)於上述步驟(e)之後，於上述第2通孔之底面及側面上形成第2絕緣膜之後，去除覆蓋自上述第2通孔之底面突出之上述複數個第1貫通電極之一部分之上述第2絕緣膜及上述第1絕緣膜，使覆蓋上述複數個第1貫通電極之上述第1障壁金屬膜自上述第2通孔之底面露出；及(g)於上述步驟(f)之後，於上述第2通孔之內部介隔第2障壁金屬膜而形成複數個第2貫通電極；此處，於俯視時上述複數個第1貫通電極之各個係位於上述複 數個第2貫通電極之各個之內側，且於俯視時上述複數個第1貫通電極之各個之中心位置係自上述複數個第2貫通電極之各個之中心位置離開；於俯視時，於上述第1區域中之上述複數個第2貫通電極係分別以相同間距配置；於俯視時，位於靠近上述第1區域之外周之上述複數個第1貫通電極之各個之上述中心位置係朝向上述第1區域之中心而配置。
  16. 如請求項15之半導體裝置之製造方法，其中於上述步驟(a)之前，進而包含以下步驟：(h)於上述半導體基板之上述第1主面上，形成層間絕緣膜；且上述步驟(a)中，於上述層間絕緣膜及上述半導體基板之上述第1主面上，形成具有上述第1口徑之上述第1通孔。
  17. 如請求項15之半導體裝置之製造方法，其中上述第1絕緣膜及上述第2絕緣膜係氧化矽膜，上述第3絕緣膜係自上述半導體基板之上述第2主面側依序形成氮化矽膜及氧化矽膜而成之積層膜。
  18. 如請求項15之半導體裝置之製造方法，其中上述第3絕緣膜係藉由電漿CVD法或氣體團簇離子束法而形成。
TW102130690A 2012-08-29 2013-08-27 半導體裝置及其製造方法 TWI588962B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012189177A JP5955706B2 (ja) 2012-08-29 2012-08-29 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
TW201419483A TW201419483A (zh) 2014-05-16
TWI588962B true TWI588962B (zh) 2017-06-21

Family

ID=50186369

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102130690A TWI588962B (zh) 2012-08-29 2013-08-27 半導體裝置及其製造方法

Country Status (5)

Country Link
US (2) US9275935B2 (zh)
JP (1) JP5955706B2 (zh)
KR (1) KR20140029178A (zh)
CN (1) CN103681616B (zh)
TW (1) TWI588962B (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8970242B2 (en) * 2008-09-30 2015-03-03 Rohm Co, Ltd. Method for manufacturing probe card, probe card, method for manufacturing semiconductor device, and method for forming probe
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
JP6146144B2 (ja) * 2013-06-03 2017-06-14 富士通株式会社 半導体装置およびその製造方法。
US20150021773A1 (en) * 2013-07-22 2015-01-22 Conversant Intellectual Property Management Inc. Through Semiconductor via Structure with Reduced Stress Proximity Effect
JP6363868B2 (ja) * 2014-05-12 2018-07-25 国立大学法人東北大学 半導体装置およびその製造方法
US9312140B2 (en) 2014-05-19 2016-04-12 International Business Machines Corporation Semiconductor structures having low resistance paths throughout a wafer
KR20160009425A (ko) * 2014-07-16 2016-01-26 에스케이하이닉스 주식회사 관통전극을 갖는 반도체소자 및 그 제조방법
JP6479579B2 (ja) 2015-05-29 2019-03-06 東芝メモリ株式会社 半導体装置
US9620488B2 (en) * 2015-08-19 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional integrated circuit structure and bonded structure
KR102497205B1 (ko) 2016-03-03 2023-02-09 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
KR102019352B1 (ko) 2016-06-20 2019-09-09 삼성전자주식회사 팬-아웃 반도체 패키지
US10692799B2 (en) * 2018-06-01 2020-06-23 Innolux Corporation Semiconductor electronic device
US11114433B2 (en) * 2018-07-15 2021-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure and method of fabricating the same
CN111261606B (zh) 2019-02-18 2020-11-17 长江存储科技有限责任公司 贯穿硅触点结构及其形成方法
JP7278184B2 (ja) 2019-09-13 2023-05-19 キオクシア株式会社 半導体装置の製造方法
KR20210120399A (ko) 2020-03-26 2021-10-07 삼성전자주식회사 관통 실리콘 비아를 포함하는 집적 회로 반도체 소자
US11495559B2 (en) * 2020-04-27 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits
JP7462269B2 (ja) 2020-05-19 2024-04-05 パナソニックＩｐマネジメント株式会社 半導体装置及び半導体装置の製造方法
CN114512469A (zh) * 2020-11-16 2022-05-17 长鑫存储技术有限公司 半导体结构及其制作方法
CN115621192A (zh) * 2021-07-13 2023-01-17 长鑫存储技术有限公司 一种半导体结构及其形成方法
US20230015307A1 (en) * 2021-07-19 2023-01-19 Changxin Memory Technologies, Inc. Semiconductor structure fabrication method, semiconductor structure and memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050233581A1 (en) * 2004-03-31 2005-10-20 Nec Electronics Corporation Method for manufacturing semiconductor device
US20120056330A1 (en) * 2010-09-07 2012-03-08 Samsung Electronics Co., Ltd. Semiconductor device
US20120164788A1 (en) * 2010-12-24 2012-06-28 Elpida Memory, Inc. Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005235860A (ja) * 2004-02-17 2005-09-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4439976B2 (ja) * 2004-03-31 2010-03-24 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
US20070032059A1 (en) * 2005-08-02 2007-02-08 Harry Hedler Method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure
JP4812512B2 (ja) * 2006-05-19 2011-11-09 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
US7488630B2 (en) * 2007-03-06 2009-02-10 International Business Machines Corporation Method for preparing 2-dimensional semiconductor devices for integration in a third dimension
US20080284041A1 (en) * 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
JP5605978B2 (ja) * 2008-02-26 2014-10-15 ピーエスフォー ルクスコ エスエイアールエル 積層メモリ
KR20100045857A (ko) * 2008-10-24 2010-05-04 삼성전자주식회사 반도체 칩, 스택 모듈, 메모리 카드 및 반도체 칩의 제조 방법
US20130119543A1 (en) * 2011-11-16 2013-05-16 Globalfoundries Singapore Pte. Ltd. Through silicon via for stacked wafer connections

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050233581A1 (en) * 2004-03-31 2005-10-20 Nec Electronics Corporation Method for manufacturing semiconductor device
US20120056330A1 (en) * 2010-09-07 2012-03-08 Samsung Electronics Co., Ltd. Semiconductor device
US20120164788A1 (en) * 2010-12-24 2012-06-28 Elpida Memory, Inc. Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Also Published As

Publication number Publication date
KR20140029178A (ko) 2014-03-10
US20140061940A1 (en) 2014-03-06
TW201419483A (zh) 2014-05-16
JP5955706B2 (ja) 2016-07-20
US9275935B2 (en) 2016-03-01
JP2014049500A (ja) 2014-03-17
US9779992B2 (en) 2017-10-03
US20160148841A1 (en) 2016-05-26
CN103681616A (zh) 2014-03-26
CN103681616B (zh) 2018-06-26

Similar Documents

Publication Publication Date Title
TWI588962B (zh) 半導體裝置及其製造方法
TWI718523B (zh) 用於堆疊積體電路的矽直通穿孔設計
TWI502700B (zh) 半導體基板、混成接合結構及混成接合基板的形成方法
US7906363B2 (en) Method of fabricating semiconductor device having three-dimensional stacked structure
TWI512896B (zh) 半導體晶粒及在基板穿孔上形成內連線結構的方法
US9425138B2 (en) Semiconductor device having through-electrode
US8970007B2 (en) Semiconductor device and process for producing semiconductor device
US7812457B2 (en) Semiconductor device and semiconductor wafer and a method for manufacturing the same
US20110298097A1 (en) Semiconductor device and method for manufacturing the same
US20140273453A1 (en) Semiconductor device and method for manufacturing semiconductor device
JP5998459B2 (ja) 半導体装置およびその製造方法、電子部品
TW201622107A (zh) 半導體裝置及其製造方法
US9337182B2 (en) Method to integrate different function devices fabricated by different process technologies
TWI812168B (zh) 三維元件結構及其形成方法
KR20120067525A (ko) 반도체 소자 및 이의 제조 방법
US8907459B2 (en) Three-dimensional semiconductor integrated circuit device and method of fabricating the same
TWI758122B (zh) 半導體結構及其形成方法
JP5960549B2 (ja) 半導体装置の製造方法
JP2009283503A (ja) 半導体装置及びその製造方法
TW202111765A (zh) 半導體裝置
JP6173531B2 (ja) 半導体装置及びその製造方法
TWI705527B (zh) 形成積體電路結構之方法、積體電路裝置、和積體電路結構
JP5751131B2 (ja) 半導体装置及びその製造方法
US20230163087A1 (en) Semiconductor package
TW201639162A (zh) 半導體裝置及其製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees