CN103681616B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN103681616B CN103681616B CN201310384818.3A CN201310384818A CN103681616B CN 103681616 B CN103681616 B CN 103681616B CN 201310384818 A CN201310384818 A CN 201310384818A CN 103681616 B CN103681616 B CN 103681616B
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Classifications
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Abstract
本发明涉及一种半导体器件及其制造方法。提供了实现高度集成采用TSV技术的半导体器件的技术。贯通电极由具有第一直径并且形成在半导体晶片的主表面上的小直径贯通电极和具有比上述第一直径大的第二直径并且形成在半导体晶片的背表面侧上的大直径贯通电极构成,并且在平面图中,小直径贯通电极布置在大直径贯通电极的内部,使得在平面图中,小直径贯通电极的中心位置和大直径贯通电极的中心位置彼此不重合。
Description
相关申请的交叉参考
于2012年8月29日提交的日本专利申请2012-189177的公开,包括说明书、附图和摘要,作为参考以其全部在此并入。
技术领域
本发明涉及一种半导体器件及其制造技术,以及,例如,可以适用于制造三维多功能器件所要求的TSV(Through Silicon Vias:贯通硅通孔)技术。
背景技术
已知作为用来实现三维多功能器件的重要技术的TSV技术。该TSV技术是用来形成垂直于厚度方向贯穿半导体衬底的贯通电极(through electrode)的技术。
例如,日本专利特开No.2005-294582(专利文献1)公开了一种半导体器件,包括由小直径插塞和大直径插塞构成的贯通电极。从硅(Si)衬底突出的小直径插塞的突出部分(下表面)贯穿到大直径插塞的顶表面中,并且小直径插塞的顶表面与第一布线耦合。
发明内容
当在硅(Si)衬底中形成从硅(Si)衬底的主表面贯穿到主表面的相反侧上的背表面的贯通电极时,由于构成贯通电极的金属导体和硅(Si)的热膨胀系数的差异,而在贯通电极周围的硅(Si)衬底中产生了变形。因此,在贯通电极的周围产生了限制半导体元件布置的区域(排除区域(keep out zone))。另外,由于多个信号布线不能布置在贯通电极的正上方,所以在布线布局时会产生约束。这种问题在促进采用TSV技术的半导体器件的高度集成时具有不利影响。
通过本说明书的描述和附图,其它问题和新特征将变得更清楚。
根据一个实施例,贯通电极由形成在半导体衬底的主表面一侧上的小直径贯通电极和形成在半导体衬底的背表面一侧上的大直径贯通电极构成,并且在平面图中,小直径贯通电极布置在大直径贯通电极的内部,使得在平面图中,小直径贯通电极的中心位置和大直径贯通电极的中心位置彼此不重合。
根据一个实施例,可以实现采用TSV技术的半导体器件的高度集成。
附图说明
图1是根据第一实施例的包括TSV的半导体器件的主要部分截面图;
图2是根据第一实施例的半导体器件的主要部分背表面视图;
图3是示出根据第一实施例的半导体器件的制造步骤期间的半导体器件的一部分的放大主要部分截面图;
图4是在图3之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图5是在图4之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图6是在图5之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图7是在图6之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图8是在图7之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图9是在图8之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图10是在图9之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图11是在图10之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图12是在图11之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图13是在图12之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图14是在图13之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图15是在图14之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图16是在图15之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图17是在图16之后的半导体器件的制造步骤期间,与图3中相同的部分的主要部分截面图;
图18A和18B分别是示出根据第一实施例的第一修改的小直径贯通电极和大直径贯通电极的布置的主要部分平面图;
图19是根据第一实施例的第二修改的包括TSV的半导体器件的主要部分截面图;
图20是根据第一实施例的第三修改的包括TSV的半导体器件的主要部分截面图;
图21是示出当从平面观察根据第二实施例的TSV形成区时的小直径贯通电极和大直径贯通电极的布置的主要部分平面图;
图22是示出当从平面观察由本发明人比较并研究的TSV形成区时的小直径贯通电极和大直径贯通电极的布置的主要部分平面图;和
图23是示出由本发明人比较并研究的贯通电极的制造步骤的半导体器件的主要部分截面图。
具体实施方式
为了方便,如果有必要的话,将分成多个部分或实施例来说明下面的实施例。除了特别清楚示出的情形之外,它们不是互相无关的,并且一个具有诸如另一个的一些或全部的修改、细节和补充说明的关系。
在下面的实施例中,当涉及要素的数量等(包括数量、数值、量、范围等)时,除了特别清楚规定以及理论上清楚限制于特定数量的情形之外,它们可以不限制于特定数量,而是可以比特定数量大或小。
此外,在下面的实施例中,不必说要素(包括要素步骤等)不是必不可少的,除了特别清楚规定的和被认为是根据理论观点等很明显必不可少的情形之外。
此外,当使用术语“由A构成”、“由A组成”、“具有A”和“包括A”时,不必说不排除除了A之外的要素,除了特别清楚规定A是唯一要素等的情形之外。同样,在下面的实施例中,当涉及要素等的形状、位置关系等时,应包括类似物或与上述形状基本相同的情况,除了特别清楚规定的和被认为是根据理论观点很明显不正确的情形之外。该声明也适用于上述的数值和范围。
此外,在用于以下实施例的图中,为了使附图更容易看得清楚,即使是平面图,也可以附上影线。此外,在下面的实施例中,当使用术语“晶片”时,主要指Si(硅)单晶晶片,但不限于此,并且指的是用于形成SOI(Silicon On Insulator:绝缘体上硅)晶片的绝缘膜衬底和其上面的集成电路等。而且晶片的形状不限于圆形或基本圆形,而是还包括正方形、矩形等。
在用于说明以下实施例的所有图中,原则上,同一符号被赋予具有相同功能的元件,并且省略了它们的重复说明。在下文,将基于附图详细地说明实施例。
(由本发明人研究的TSV技术)
由于根据本实施例的采用TSV技术的半导体器件被认为是更清楚的,所以将说明本发明人已经比较并研究的半导体器件中的问题。
首先,利用图23,将通过本发明人研究的通孔中间方案简要说明贯通电极的制造步骤的一个实例。图23是示出贯通电极的制造步骤的半导体器件的主要部分截面图。
例如,制备由单晶硅(Si)构成的半导体晶片(平表面为基本圆形的半导体薄板被称为晶片)SW。虽然省略了图示,但在半导体晶片SW的主表面(表面或第一主表面)S1上形成了多个半导体元件。然后在半导体晶片SW的主表面S1上面形成层间绝缘膜ILD,以覆盖这些半导体元件。
接下来,通过使用抗蚀剂图案作为掩膜的干法蚀刻,顺序处理层间绝缘膜ILD和半导体晶片SW,以在形成贯通电极的区域(没有形成半导体元件的区域)中形成通孔(贯通孔(through hole)、连接孔或开口)VI。之后,经由由氧化硅(SiO2)构成的绝缘膜I1和由钽(Ta)等构成的阻挡金属膜BM,在通孔VI内部掩埋铜(Cu)镀膜,并且形成由铜(Cu)膜构成的贯通电极TE。
随后,形成第一层布线M1和耦合垫MC,该耦合垫MC位于与第一层布线M1相同的层中并且耦合至贯通电极TE。之后,在形成第二层布线M2和更上层布线之后,形成铜(Cu)凸块CB以耦合至顶层布线,并且形成外部端子SB以耦合至铜(Cu)凸块CB。
接下来,研磨、抛光或回蚀刻在半导体晶片SW的主表面S1的相反侧上的背表面(第二主表面)S2。其结果是,使半导体晶片SW的厚度变薄,并且进一步地,使得覆盖有绝缘膜I1和阻挡金属膜BM的贯通电极TE的底部从半导体晶片SW的背表面S2突出。随后,在半导体晶片SW的背表面S2上形成绝缘膜I2以覆盖从半导体晶片SW的背表面S2突出的且覆盖有绝缘膜I1和阻挡金属膜BM的贯通电极TE的底部。
随后,通过CMP(化学机械抛光)方法抛光覆盖贯通电极TE底部的绝缘膜I2、绝缘膜I1和阻挡金属膜BM,以暴露贯通电极TE的下表面。
<问题1>
当在半导体晶片SW中形成从半导体晶片SW的主表面S1贯穿到在主表面S1的相反侧上的背表面S2的贯通电极TE时,由于构成贯通电极TE的铜(Cu)和构成半导体晶片SW的硅的热膨胀系数之间的差异,导致在贯通电极TE的周围的半导体晶片SW中产生了变形。因此,限制了可以布置半导体元件的区域。例如,当在半导体晶片SW中形成具有5μm直径的通孔VI时,离通孔VI的外圆周大约1μm的范围对应于限制半导体元件布置的区域(排除区域)。随着通孔VI的直径变大,限制半导体元件布置的区域(排除区域)变宽,即,更增加了掩埋在通孔VI内部的铜(Cu)的体积。
另外,由于耦合至贯通电极TE的耦合垫MC布置在贯通电极的正上方,所以不能布置多个信号布线。因此,在布线布局中产生了约束。
为了使限制半导体元件布置的区域(排除区域)变窄,或使可以布置多个信号布线的区域延伸,可以减小通孔VI的直径以减小贯通电极TE的体积。然而,在具有同一深度的通孔VI的情况下,具有小直径的通孔VI的纵横比(通孔深度/通孔直径)与具有大直径的通孔VI的纵横比相比更高,该通孔VI形成在半导体晶片SW中。因此,当减小通孔VI的直径时,会产生铜(Cu)镀膜难以掩埋在通孔VI内部的这种问题。
<问题2>
当处理半导体晶片SW的背表面S2并且使半导体晶片SW的厚度变薄时,担心覆盖贯通电极TE的下表面的绝缘膜I1的部分被移除,并且暴露出贯通电极TE的下表面。当暴露出贯通电极TE的下表面时,构成贯通电极TE的铜(Cu)会从半导体晶片SW的背表面S2扩散进半导体晶片SW中。其结果是,由于铜(Cu)污染,改变了形成在半导体晶片SW的主表面S1上的半导体元件的操作特性。
<问题3>
另外,本发明人还研究了通过后通孔(via-last)和背通孔(via-back)方案(该方案中,在半导体衬底的主表面一侧上形成半导体元件和多层布线之后,从半导体衬底的背表面一侧在半导体衬底中形成通孔,并且在该通孔内部掩埋贯通电极)制造贯通电极的步骤。
然而,存在如下风险:当在半导体晶片中形成上述通孔时,会蚀刻形成在半导体衬底的主表面一侧上的多层布线。
如前文所述,在采用TSV技术的半导体器件中,必须使半导体元件的形成区域和由贯通电极的布置约束的布线的布置区域最小化。另外,必须避免如下问题,诸如在贯通电极的制造步骤中产生的铜(Cu)污染。
注意,从本发明人的研究显而易见,具体地,如在上面提到的专利文献1中,通过仅由小直径插塞和大直径插塞构成贯通电极,难以避免由于在贯通电极周围的硅(Si)衬底中产生的变形而引起的排除区域的问题。
(第一实施例)
<<半导体器件>>
将利用图1和2描述根据本第一实施例的包括TSV的半导体器件。图1是半导体器件的主要部分截面图,图2是半导体器件的主要部分背表面图。
在半导体器件(半导体芯片)中,在彼此不同的区域中提供其中形成了诸如场效应晶体管、电阻元件和电容元件的各种半导体元件的区域(下文称为元件形成区(第二区域))和其中形成了多个贯通电极的区域(下文称为TSV形成区(第一区域))。在图1中,示例了n沟道型MISFET(金属绝缘体半导体场效应晶体管),其代表在元件形成区中形成的各种半导体元件当中的场效应晶体管。另外,在以下说明中,n沟道型MISFET缩写为nMISFET。
首先,将利用图1说明形成在元件形成区中的nMISFET的构造。
如图1所示,在元件形成区的半导体晶片SW的主表面(表面或第一主表面)S1中形成隔离部分IR,该隔离部分IR是在其内部掩埋了绝缘膜的隔离沟槽,并且由隔离部分IR限定形成nMISFET的有源区。半导体晶片SW的厚度例如为大约50μm。在半导体晶片SW的主表面S1中形成p型阱PW,并且在已经形成了p型阱PW的区域中形成nMISFET。经由nMISFET的栅绝缘膜GI在半导体晶片SW的主表面S1上形成栅电极GE。栅绝缘膜GI例如由通过热氧化方法形成的氧化硅(SiO2)构成,并且栅电极GE例如由通过CVD(化学汽相沉积)方法形成的多晶硅(Si)构成。
在nMISFET的栅电极GE的侧表面上形成侧壁SL。该侧壁SL例如由氧化硅(SiO2)或氮化硅(Si3N4)构成。另外,形成用作源极和漏极的n型半导体区SD,其在nMISFET的栅电极GE的两侧上的p型阱PW中夹有沟道区。
此外,nMISFET覆盖有停止绝缘膜SIF和层间绝缘膜ILD1。停止绝缘膜SIF例如由氮化硅(Si3N4)构成。另外,层间绝缘膜ILD1例如由氧化硅(SiO2)构成,并且使其表面平整化。在停止绝缘膜SIF和层间绝缘膜ILD1中形成到达栅电极GE的连接孔(省略了图示)和到达n型半导体区SD的连接孔CN。连接孔CN是柱状的,其直径被设定为等于或小于第一层布线M1的线宽,且例如为大约0.06μm。经由阻挡金属膜BP,在连接孔CN内部形成由金属构成的耦合电极(插塞)CE。
在耦合电极CE上,通过单镶嵌方法形成其中例如铜(Cu)膜用作主要导体的第一层布线M1,并将其耦合至耦合电极CE。也就是,通过在沉积在耦合电极CE和层间绝缘膜ILD1上的层间绝缘膜ILD2中形成布线形成沟槽TRa,并且在布线形成沟槽TRa内部掩埋铜(Cu)膜,来形成第一层布线M1。在布线形成沟槽TRa的内壁和铜(Cu)膜之间形成阻挡金属膜。第一层布线M1的线宽例如为大约0.1μm。
此外,在第一层布线M1上,通过双镶嵌方法将第二层布线M2形成为经由耦合部件耦合至第一层布线M1,在第二层布线M2的每个中,例如,铜(Cu)膜用作主要导体。也就是说,通过在沉积在第一层布线M1和层间绝缘膜ILD2上的层间绝缘膜ILD3中形成布线形成沟槽TA,进一步在联接布线形成沟槽TA和第一层布线M1的部分中形成连接孔TB,并且在布线形成沟槽TA和连接孔TB内部掩埋铜(Cu)膜,来形成第二层布线M2。与第二层布线M2整体形成的耦合部件形成在连接孔TB内部。阻挡金属膜形成在布线形成沟槽TA和连接孔TB的每个的内壁和铜(Cu)膜之间。要注意,第二层布线M2可以通过与第一层布线M1类似的单镶嵌方法形成。
此外,在第二层布线M2上,形成上层布线,并且形成绝缘膜IL和密封树脂RS使得覆盖顶层布线(第一实施例中的第六层布线M6)。在绝缘膜IL和密封树脂RS中形成到达第六层布线M6的开口VO,将铜(Cu)凸块CB形成为耦合至开口VO内部的第六层布线M6,并且进一步将半球状的外部端子(焊球)SB形成为耦合至铜(Cu)凸块CB。
要注意,虽然在第一实施例中示例了六层中的布线(布线M1至M6),但本发明不限于此。本发明可以采用不超过五层的布线或不小于七层的布线,并且将上述的铜(Cu)凸块CB和外部端子SB形成为耦合至顶层布线。
接下来,将利用图1和2说明形成在TSV形成区中的TSV的构造。
如图1所示,在TSV形成区中的半导体晶片SW、停止绝缘膜SIF和层间绝缘膜ILD1中,形成了在厚度方向上贯穿它们的通孔(贯通孔、连接孔或开口)。
该通孔是由小直径通孔(第一通孔;贯通孔;连接孔;或开口)VI1和具有比小直径通孔VI1的直径大的直径(直径或内径)的大直径通孔(第二通孔;贯通孔;连接孔;或开口)VI2构成的,小直径通孔VI1布置在半导体晶片SW的主表面S1一侧上,并且大直径通孔VI2布置在半导体晶片SW的背表面(第二主表面)S2一侧上。也就是说,小直径通孔VI1从层间绝缘膜ILD1和停止绝缘膜SIF的每个的上表面贯穿到下表面,进一步形成为具有离半导体晶片SW的主表面S1的预定深度,并且大直径通孔VI2形成为具有离半导体晶片SW的背表面的预定深度。
小直径通孔VI1的直径(第一直径)例如为大约2μm,并且其深度例如为大约10μm。大直径通孔VI2的直径(第二直径)例如为大约10μm,并且其深度例如为大约43μm。
另外,在小直径通孔VI1的侧表面上形成例如由氧化硅(SiO2)构成的第一绝缘膜IF1。此外,经由阻挡金属膜BM1,在小直径通孔VI1内部形成由铜(Cu)镀膜构成的小直径贯通电极(第一贯通电极)TE1。第一绝缘膜IF1用作防止来自小直径贯通电极TE1的金属污染的保护膜,并且还实现使小直径贯通电极TE1与半导体晶片SW绝缘并分离的作用。第一绝缘膜IF1的厚度例如为大约0.1μm。阻挡金属膜BM1例如为钽(Ta)膜,并且其厚度例如为大约10nm。
另外,在大直径通孔VI2的侧表面上形成例如由氧化硅(SiO2)构成的第二绝缘膜IF2。此外,经由阻挡金属膜BM2,在大直径通孔VI2内部形成由铜(Cu)镀膜构成的大直径贯通电极(第二贯通电极)TE2。第二绝缘膜IF2用作防止来自大直径贯通电极TE2的金属污染的保护膜,并且还实现使大直径贯通电极TE2与半导体晶片SW绝缘并分离的作用。第二绝缘膜IF2的厚度例如为大约0.2μm。阻挡金属膜BM2例如为钽(Ta)膜,并且其厚度例如为大约25nm。
小直径贯通电极TE1的下表面(半导体晶片SW的背表面S2一侧上的表面)位于比大直径通孔VI2的底表面更靠近半导体晶片SW的背表面S2一侧。也就是说,小直径贯通电极TE1的一部分突出到大直径通孔VI2的内部。
虽然已经示例了钽(Ta)膜作为阻挡金属膜BM1和BM2,但本发明不限于此,并且,例如,还可以使用钛(Ti)膜、钴(Co)膜、钌(Ru)膜、氮化钛(TiN)膜或氮化钽(TaN)膜。
贯通电极是由小直径贯通电极TE1和大直径贯通电极TE2构成的,并且小直径贯通电极TE1的下表面(半导体晶片SW的背表面S2一侧上的表面)和大直径贯通电极TE2的上表面(半导体晶片SW的主表面S1一侧上的表面)经由阻挡金属膜BM1和BM2彼此电耦合。
然而,在与半导体晶片SW的主表面S1平行的面中的小直径贯通电极TE1的平面面积和直径(第一直径)分别比在与半导体晶片SW的主表面S1平行的面中的大直径贯通电极TE2的平面面积和直径(第二直径)小。另外,在平面图中,小直径贯通电极TE1布置在大直径贯通电极TE2的内部,并且在平面图中,小直径贯通电极TE1的中心位置(由图1中的长虚点线指示的中心1)和大直径贯通电极TE2的中心位置(由图1中的长虚点线指示的中心2)彼此不重合。也就是说,在平面图中,小直径贯通电极TE1的中心位置离开大直径贯通电极TE2的中心位置。
如上所述,由于构成小直径贯通电极TE1和大直径贯通电极TE2的铜(Cu)和构成半导体晶片SW的硅(Si)之间的热膨胀系数的差异,在小直径贯通电极TE1和大直径贯通电极TE2周围的半导体晶片SW中产生变形。然而,在半导体晶片SW的主表面S1一侧上形成具有比大直径贯通电极TE2的直径小的直径的小直径贯通电极TE1,即,具有更小体积的小直径贯通电极TE1。其结果是,与在半导体晶片SW的主表面S1一侧上也形成大直径贯通电极TE2的情形(指的是上面提到的图23)相比,在半导体晶片SW的主表面S2一侧上,产生变形的范围变小,并且贯通电极占据的区域变小。
因此,在第一实施例中,受到变形影响的半导体晶片SW的区域(限制半导体元件布置的区域(排除区域))变小,并且因此可以布置半导体元件的区域可以增加与减小的受到变形影响的半导体晶片SW的区域对应的量。此外,由于形成小直径贯通电极TE1的位置可以在能够耦合至大直径贯通电极TE2的范围内调节,所以小直径贯通电极TE1的位置可以根据半导体元件的布置来设定。因此,可以实现半导体元件的高度集成,并且半导体元件的布置的自由度也会变高。
另外,当贯通电极(小直径贯通电极TE1)在半导体晶片SW的主表面S1一侧上占据的区域变小时,使得耦合至贯通电极的耦合垫MC的平面面积也变小,因此可以布置第一层布线M1的区域变大,并且布置第一层布线M1的自由度变高。
小直径贯通电极TE1的上表面(半导体晶片SW的主表面S1一侧上的表面)经由阻挡金属膜耦合至与第一层布线M1相同层中的耦合垫MC。通过在层间绝缘膜ILD2中形成耦合垫形成沟槽TRb,并且在耦合垫形成沟槽TRb内部掩埋铜(Cu)膜,来形成耦合垫MC。
在第一实施例中,虽然示例了耦合垫MC作为贯通电极(小直径贯通电极TE1)的上表面耦合到的层,但本发明不限于此,并且该层可以是形成在与第一层布线M1相同层中的布线(例如,形成条形或格形的布线)。
在半导体晶片SW的背表面S2形成绝缘膜(第三绝缘膜)IF3。该绝缘膜IF3还用作防止半导体晶片SW的背表面S2被金属污染的保护膜。例如,绝缘膜IF3是氮化硅(Si3N4)膜、氧化硅(SiO2)膜、或氮化硅(Si3N4)膜和氧化硅(SiO2)膜的堆叠膜。
此外,在半导体晶片SW的背表面S2处暴露出大直径贯通电极TE2的下表面(半导体晶片SW的背表面S2一侧上的表面)。将阻挡金属膜BM3形成为耦合至大直径贯通电极TE2的下表面,并且将铜(Cu)片层CS和背表面凸块RB形成为耦合至阻挡金属膜BM3。例如,阻挡金属膜BM3是钛(Ti)膜、钽(Ta)膜、钴(Co)膜、钌(Ru)膜、氮化钛(TiN)膜或氮化钽(TaN)膜。另外,背表面凸块RB由已经从铜(Cu)片层CS一侧将铜(Cu)、镍(Ni)和Au(金)顺序形成为膜的堆叠膜构成。
通过标准限定了形成多个由小直径贯通电极TE1和大直径贯通电极TE2构成的贯通电极TE的区域的尺寸,以保持与诸如存储器的通用产品的连接。例如,如图2所示,在高度和宽度为6乘6mm尺寸的半导体芯片(半导体器件)SC中,布置四个TSV形成区ATSV,其中在半导体芯片SC的中心中,以40μm的节距(pitch)在高度上布置五十个贯通电极和宽度上布置六个贯通电极。也就是说,半导体芯片SC的中心是形成了多个贯通电极的TSV形成区ATSV,并且其它区域对应于形成了多个半导体元件的元件形成区。要注意,虽然在图2中的半导体芯片SC的中心提供了TSV形成区ATSV,但提供TSV形成区ATSV的位置不限于中心。
另外,形成在TSV形成区ATSV中的多个贯通电极不是全部都不需要由小直径贯通电极TE1的中心位置和大直径贯通电极TE2的中心位置在平面图中彼此不重合的贯通电极构成。也就是说,形成在TSV形成区ATSV中的所有贯通电极都可以通过小直径贯通电极TE1的中心位置和大直径贯通电极TE2的中心位置在平面图中彼此不重合的贯通电极构成。可选地,形成在TSV形成区ATSV中的一部分贯通电极可以由小直径贯通电极TE1的中心位置和大直径贯通电极TE2的中心位置在平面图中彼此不重合的贯通电极构成,其它贯通电极可以由小直径贯通电极TE1的中心位置和大直径贯通电极TE2的中心位置在平面图中彼此重合的贯通电极构成。
<<半导体器件的制造方法>>
接下来,将利用图3至17按照步骤顺序说明根据本第一实施例的采用TSV技术的半导体器件的制造方法。图3至17是在该半导体器件的制造步骤期间半导体器件的主要部分截面图,并且分别示出了一部分元件形成区和一部分TSV形成区。另外,举例说明了nMISFET,作为图3至17的元件形成区中的半导体元件。另外,例如,虽然在该半导体器件中形成了不少于一百个贯通电极,但是为了方便,在图3至17中将描述由一小直径贯通电极和一大直径贯通电极组成的一个贯通电极和它的外围。
<半导体元件的形成步骤>
首先,如图3所示,例如,制备由单晶硅(Si)构成的半导体晶片(平表面基本是圆形的半导体薄板被称为晶片)SW。例如,半导体晶片SW的厚度(第一厚度)为大约700μm。接下来,在半导体晶片SW的主表面(表面或第一主表面)的元件隔离区中形成由绝缘膜构成的隔离部分IR。随后,在形成了nMISFET的区域中,向半导体晶片SW中离子注入示出p型导电性的杂质,以形成p型阱PW。
接下来,在半导体晶片SW的主表面上形成nMISFET的栅绝缘膜GI之后,在栅绝缘膜GI上形成nMISFET的栅电极GE。随后,在栅电极GE的侧表面上形成侧壁SL之后,在栅电极GE两侧上的p型阱PW中离子注入示出n型导电性的杂质,并且关于栅电极GE和侧壁SL,以自对准方式,形成用作nMISFET的源极和漏极的n型半导体区SD。
随后,在半导体晶片SW的主表面上顺序形成停止绝缘膜SIF和层间绝缘膜ILD1。停止绝缘膜SIF是当处理层间绝缘膜ILD1时用作蚀刻停止的膜,并因此使用相对层间绝缘膜ILD1具有蚀刻选择性的材料。停止绝缘膜SIF例如是氮化硅(Si3N4)膜,并且层间绝缘膜ILD1例如是氧化硅(SiO2)膜。
接下来,通过使用抗蚀剂图案作为掩膜的干法蚀刻,顺序处理层间绝缘膜ILD1和停止绝缘膜SIF,以在元件形成区中形成连接孔CN。连接孔CN形成在需要电压施加以操作n型半导体区SD上的nMISFET和栅电极GE等的部分中。
随后,例如,通过溅射方法,在半导体晶片SW的主表面上形成阻挡金属膜BP。该阻挡金属膜BP例如是钛(Ti)膜、钽(Ta)膜、氮化钛(TiN)膜或氮化钽(TaN)膜,并且其厚度例如为大约0.1μm。随后,例如,通过CVD方法或溅射方法,在阻挡金属膜BP上形成钨(W)膜。随后,通过CMP方法移除除了连接孔CN内之外的区域中的钨(W)膜和阻挡金属膜BP,并且在连接孔CN内形成由钨(W)膜构成的耦合电极(插塞)CE。
<小直径贯通电极的形成步骤>
接下来,如图4所示,通过利用抗蚀剂图案作为掩膜,顺序蚀刻TSV形成区中的层间绝缘膜ILD1、停止绝缘膜SIF和半导体晶片SW,以在层间绝缘膜ILD1、停止绝缘膜SIF和半导体晶片SW中形成小直径通孔(第一通孔:贯通孔;连接孔;或开口)VI1。小直径通孔VI1的直径(第一直径:直径;或内径)例如为大约2μm,并且其深度例如为大约10μm。
随后,如图5所示,在包括小直径通孔VI1的底表面和侧表面的半导体晶片SW的主表面上形成第一绝缘膜IF1。第一绝缘膜IF1例如是通过等离子体CVD方法形成的氧化硅(SiO2)膜,并且其厚度例如为大约0.1μm。
接下来,在半导体晶片SW的主表面上(在第一绝缘膜IF1上)形成阻挡金属膜BM1之后,在阻挡金属膜BM1上形成铜(Cu)籽晶层(省略了图示),并且利用电镀方法在该籽晶层上进一步形成铜(Cu)镀膜CP1。由于小直径通孔VI1的直径相对小,例如为大约2μm,但是其纵横比大约为5,所以铜(Cu)镀层CP1可以通过电镀方法掩埋在小直径通孔VI1内部。阻挡金属膜BM1例如是钛(Ti)膜、钽(Ta)膜、钴(Co)膜、钌(Ru)膜、氮化钛(TiN)膜或氮化钽(TaN)膜,并且其厚度例如为大约10nm。
接下来,如图7所示,通过CMP方法,移除除了小直径通孔VI1内部之外的区域中的铜(Cu)镀膜CP1、籽晶层、阻挡金属膜BM1和第一绝缘膜IF1,以在小直径通孔VI1内部形成由铜(Cu)膜构成的小直径贯通电极(第一贯通电极)TE1。
<多层布线和外部端子的形成步骤>
接下来,如图8所示,在半导体晶片SW的主表面一侧上顺序形成第一层布线M1、耦合垫MC、第二层布线M2、铜(Cu)凸块CB和外部端子(焊球)SB。
首先,通过单镶嵌方法在元件形成区中形成第一层布线M1,并在TSV形成区中形成耦合垫MC。
在半导体晶片SW的主表面上形成层间绝缘膜ILD2。例如,该层间绝缘膜ILD2是通过等离子体CVD方法形成的氧化硅(SiO2)膜。随后,在形成了第一层布线M1的元件形成区的区域中,利用该抗蚀剂图案作为掩膜,干法蚀刻层间绝缘膜ILD2,以形成布线形成沟槽TRa,其从层间绝缘膜ILD2的上表面贯穿到下表面,并且到达耦合电极CE。同时,在形成了耦合垫MC的TSV形成区的区域中形成耦合垫形成沟槽TRb,其从层间绝缘膜ILD2的上表面贯穿到下表面,并到达小直径贯通电极TE1。
随后,在半导体晶片SW的主表面上形成阻挡金属膜B1。例如,阻挡金属膜B1是钛(Ti)膜、钽(Ta)膜、氮化钛(TiN)膜或氮化钽(TaN)膜。随后,通过CVD方法或溅射方法,在阻挡金属膜B1上形成铜(Cu)籽晶层(省略了图示),并且利用电镀方法在该籽晶层上进一步形成铜(Cu)镀膜(省略了图示)。布线形成沟槽TRa和耦合垫形成沟槽TRb的内部被铜(Cu)镀膜掩埋。
随后,通过CMP方法,移除除了布线形成沟槽TRa和耦合垫形成沟槽TRb内部之外的区域中的阻挡金属膜B1。该结果是,在布线形成沟槽TRa内部形成了由铜(Cu)膜构成的第一层布线M1。同时,在耦合垫形成沟槽TRb内部形成了由铜(Cu)膜构成的耦合垫MC。要注意,虽然在第一实施例中用电镀方法形成了构成第一层布线M1和耦合垫MC的铜(Cu)膜,但是其也可以通过CVD方法、溅射方法、溅射回流方法等形成。
接下来,通过双镶嵌方法在元件形成区和TSV形成区中形成第二层布线M2。
例如,通过等离子体CVD方法,在半导体晶片SW的主表面上形成层间绝缘膜ILD3。在位于层间绝缘膜ILD3的下层中的、其表面基本平坦的层间绝缘膜ILD2、第一层布线M1和耦合垫MC的各个表面成形之后形成层间绝缘膜ILD3,由此层间绝缘膜ILD3的表面也基本是平坦的。随后,利用抗蚀剂图案作为掩膜,干法蚀刻层间绝缘膜ILD3,以在形成了第二层布线M2的区域中形成布线形成沟槽TA。此外,在联接布线形成沟槽TA和第一层布线M1的部分中,形成到达第一层布线M1的连接孔TB。同时,在联接布线形成沟槽TA和耦合垫MC的部分中,形成到达耦合垫MC的连接孔。
随后,在半导体晶片SW的主表面上形成阻挡金属膜B2之后,在阻挡金属膜B2上形成铜(Cu)籽晶层(省略了图示),并且利用电镀方法,在该籽晶层上进一步形成铜(Cu)镀膜(省略了图示)。该阻挡金属膜B2是单层膜,诸如钛(Ti)膜、钽(Ta)膜、氮化钛(TiN)膜或氮化钽(TaN)膜,或者是堆叠了这些膜的一些的堆叠膜。
随后,通过CMP方法,移除除了布线形成沟槽TA和连接孔TB内部之外的区域中的铜(Cu)镀膜、籽晶层和阻挡金属膜B2,在布线形成沟槽TA内部形成由铜(Cu)膜构成的第二层布线M2,并且在连接孔TB的内部形成与第二层布线M2整体形成的耦合部件。
之后,虽然与上述的第一层布线M1或第二布线M2类似地进一步形成上层布线,但省略这里的说明。
接下来,形成铜(Cu)凸块CB和外部端子(焊球)SB。
在半导体晶片SW的主表面一侧上形成绝缘膜(省略了图示)和密封树脂RS,以覆盖顶层布线(例如,在上述的图1中示出的第六层布线M6)。随后,在绝缘膜和密封树脂RS中形成到达顶层布线的开口VO之后,形成铜(Cu)凸块CB以利用电镀方法掩埋该开口VO。
随后,使外部端子(焊球)SB耦合至从开口VO暴露出的铜(Cu)凸块CB。例如,外部端子SB是在通过球供应方法提供球状焊接剂之后通过应用热处理形成的。
<大直径贯通电极的形成步骤>
接下来,如图9所示,经由接合层CL在半导体晶片SW的主表面一侧上接合玻璃支撑体GH。
接下来,如图10所示,研磨、抛光或回蚀刻在半导体晶片SW的主表面的相反侧上的背表面(第二主表面),以使半导体晶片SW的厚度(第二厚度),例如,为不大于50μm。此时,小直径贯通电极TE1没有从半导体晶片SW的背表面突出。
接下来,在半导体晶片SW的背表面上顺序形成绝缘膜(由图1中的符号IF3指示的第三绝缘膜),例如,氮化硅(Si3N4)膜IN和氧化硅(SiO2)膜IO。由于该膜形成需要在不大于使玻璃支撑体GH粘附的接合层CL的耐热温度的温度下执行,所以,例如,通过等离子体CVD方法或气体簇型离子束方法形成氮化硅(Si3N4)膜IN和氧化硅(SiO2)膜IO。
接下来,如图11所示,通过利用抗蚀剂图案作为掩膜从半导体晶片SW的背表面一侧顺序蚀刻氧化硅(SiO2)膜IO、氮化硅(Si3N4)膜IN和TSV形成区中的半导体晶片SW,以在半导体晶片SW中形成大直径通孔(第二通孔;贯通孔;连接孔;或开口)VI2。大直径通孔VI2的直径(第二直径:直径;或内径)例如为大约10μm,并且其深度例如为大约43μm。
此时,覆盖有第一绝缘膜IF1和阻挡金属膜BM1的小直径贯通电极TE1的一部分从大直径通孔VI2的底表面的一部分突出。也就是说,小直径贯通电极TE1的下表面位于比大直径通孔VI2的底表面更靠近半导体晶片SW的背表面一侧。另外,在平面图中,小直径通孔VI1的中心位置和大直径通孔VI2的中心位置彼此不重合。也就是说,在平面图中,小直径通孔VI1的中心位置离开大直径通孔VI2的中心位置。
接下来,如图12所示,在半导体晶片SW的背表面上形成第二绝缘膜IF2,以覆盖大直径通孔VI2的底表面和侧表面,并且小直径贯通电极TE1的该部分(其覆盖有第一绝缘膜IF1和阻挡金属膜BM1)从大直径通孔VI2的底表面暴露出。第二绝缘膜IF2例如是等离子体TEOS(原硅酸四乙酯)膜,并且其厚度例如为大约0.2μm。
接下来,如图13所示,移除覆盖小直径贯通电极TE1的下表面的第一绝缘膜IF1和第二绝缘膜IF2,以暴露出覆盖小直径贯通电极TE1的下表面的阻挡金属膜BM1。
接下来,如图14所示,在半导体晶片SW的背表面上形成阻挡金属膜BM2,以覆盖大直径通孔VI2的底表面和侧表面,并且小直径贯通电极TE1的该部分(其覆盖有阻挡金属膜BM1)从大直径通孔VI2的底表面暴露出。随后,在阻挡金属膜BM2上形成铜(Cu)籽晶层(省略了图示),并且利用电镀方法在籽晶层上进一步形成了铜(Cu)镀膜CP2。阻挡金属膜BM2是单层膜,诸如钛(Ti)膜、钽(Ta)膜、钴(Co)膜、钌(Ru)膜、镍(Ni)膜、氮化钛(TiN)膜或氮化钽(TaN)膜,或者它们的堆叠膜。虽然这里描述了利用阻挡金属膜BM2的情形的第一实施例,但可以使用具有防止铜(Cu)扩散到半导体晶片SW的性能的绝缘膜,例如氮化硅(Si3N4)膜,来代替阻挡金属膜BM2。
接下来,如图15所示,通过CMP方法移除除了大直径通孔VI2内部之外的区域中的铜(Cu)镀膜CP2、籽晶层和阻挡金属膜BP,以形成由大直径通孔VI2内部的铜(Cu)膜构成的大直径贯通电极TE2。在这种情况下,由于已经在半导体晶片SW的背表面上形成了氮化硅(Si3N4)膜IN,所以没有暴露出半导体晶片SW的背表面。因此,可以防止构成大直径贯通电极TE2的铜(Cu)扩散到半导体晶片SW中,并且可以抑制由于铜(Cu)污染引起的半导体元件的操作特性的改变。
接下来,如图16所示,形成阻挡金属膜BM3、铜(Cu)片层CS和背表面凸块RB,耦合至大直径贯通电极TE2的下表面。阻挡金属膜BM3例如是钛(Ti)膜、钽(Ta)膜、钴(Co)膜、钌(Ru)膜、氮化钛(TiN)膜或氮化钽(TaN)膜。另外,背表面凸块RB由已经从铜(Cu)片层CS一侧将铜(Cu)、镍(Ni)和Au(金)顺序形成为膜的堆叠膜构成。
接下来,如图17所示,移除玻璃支撑体GH和接合层CL。之后,沿着切割线切割其中已经形成了半导体元件、贯通电极TE等的半导体晶片SW,以分别分成半导体器件。通过上述步骤,基本完成了半导体器件。
如上所述,根据第一实施例,贯通电极由小直径贯通电极TE1和大直径贯通电极TE2构成,小直径贯通电极TE1布置在半导体晶片SW的主表面一侧上,由此可以获得以下效果。
由于受到变形影响的半导体晶片SW的区域(限制半导体元件布置的区域(排除区域))变小,所以可以布置半导体元件的区域变大了与减小的受到变形影响的半导体晶片SW的区域对应的量。此外,由于形成小直径贯通电极TE1的位置可以在能够耦合至大直径贯通电极TE2的范围内调节,所以小直径贯通电极TE1的位置可以根据半导体元件的布置设置。因此,可以实现半导体元件的高度集成,并且布置半导体元件的自由度还会变高。
另外,当贯通电极(小直径贯通电极TE1)占据的半导体晶片SW的主表面S1一侧上的区域变小时,耦合至贯通电极的耦合垫MC的平面面积也会变小,因此可以布置第一层布线M1的区域变大,并且布置第一层布线M1的自由度也会变高。
另外,由于形成大直径贯通电极TE2时,半导体晶片SW的背表面一直覆盖有绝缘膜(氮化硅(Si3N4)IN膜等),所以半导体晶片SW的背表面没有被暴露。因此,构成大直径贯通电极TE2的铜(Cu)不会从半导体晶片SW的背表面扩散进半导体晶片SW中,因此可以防止由于铜(Cu)污染引起的半导体元件的操作特性的改变。
另外,虽然从半导体晶片SW的背表面向主表面形成其中掩埋了大直径贯通电极TE2的大直径通孔VI2,但由于大直径通孔VI2的底表面没有到达半导体晶片SW的主表面,所以不存在蚀刻形成在半导体晶片SW的主表面一侧上的多层布线的风险。
<<第一修改>>
将利用图18A和18B说明根据第一实施例的第一修改的贯通电极。图18A和18B分别是示出小直径贯通电极和大直径贯通电极的布置的主要部分平面图。
虽然在上述的图1中示出的半导体器件中,一个贯通电极由一个小直径贯通电极TE1和一个大直径贯通电极TE2构成,但本发明不限于此。一个贯通电极可以由一个大直径贯通电极和多个小直径贯通电极构成。
在图18A中,示例了由两个小直径贯通电极TE1a和一个大直径贯通电极TE2a构成的一个贯通电极TEa。在平面图中,小直径贯通电极TE1a的直径比大直径贯通电极TE2a的直径小,并且小直径贯通电极TE1a位于大直径贯通电极TE2a的内部。另外,小直径贯通电极TE1a的中心位置和大直径贯通电极TE2a的中心位置彼此不重合。也就是说,在平面图中小直径贯通电极TE1a的中心位置离开大直径贯通电极TE2a的中心位置。
在图18B中,示例了由三个小直径贯通电极TE1b和一个大直径贯通电极TE2b构成的一个贯通电极TEb。在平面图中,小直径贯通电极TE1b的直径比大直径贯通电极TE2b的直径小,并且小直径贯通电极TE1b位于大直径贯通电极TE2b的内部。另外,小直径贯通电极TE1b的中心位置和大直径贯通电极TE2b的中心位置彼此不重合。也就是说,在平面图中,小直径贯通电极TE1b的中心位置离开大直径贯通电极TE2b的中心位置。
如上所述,形成了多个小直径贯通电极TE1a和TE1b,并且由此相比形成一个小直径贯通电极的情况,贯通电极TE1a和TE1b的电阻可以减小更多。
<<第二修改>>
将利用图19说明根据第一实施例的第二修改的贯通电极。图19是贯通电极的主要部分截面图。
虽然在上述的图1中示出的半导体器件中,贯通电极由掩埋在形成于层间绝缘膜ILD1、停止绝缘膜SIF和半导体晶片SW中的小直径通孔VI1中的小直径贯通电极TE1和掩埋在形成于半导体晶片SW中的大直径通孔VI2中的大直径贯通电极TE2构成,但本发明不限于此。
例如,如图19所示,贯通电极可以由掩埋在形成于半导体晶片SW中的小直径通孔VI1c中的小直径贯通电极TE1c和掩埋在形成于半导体晶片SW中的大直径通孔VI2中的大直径贯通电极TE2构成。在这种情况下,通过掩埋在形成于层间绝缘膜ILD1和停止绝缘膜SIF中的连接孔CN中的耦合电极TE3将耦合垫MC和小直径贯通电极TE1c电耦合。
耦合电极TE3形成在层间绝缘膜ILD1和停止绝缘膜SIF中,并且在平面图中具有第三直径,耦合电极TE3的一端经由阻挡金属膜耦合至耦合垫MC,其另一端经由阻挡金属膜BP耦合至小直径贯通电极TE1c。小直径贯通电极TE1c从半导体晶片SW的主表面一侧形成在半导体晶片SW中,并且在平面图中具有第一直径,小直径贯通电极TE1c的一端经由阻挡金属膜BP耦合至耦合电极TE3,其另一端经由阻挡金属膜BM1c和阻挡及金属膜BM2耦合至大直径贯通电极TE2。另外,大直径贯通电极TE2从半导体晶片SW的背表面一侧形成在半导体晶片SW中,并且在平面图中具有第二直径,大直径贯通电极TE2的一端经由阻挡金属膜BM1c和BM2耦合至小直径贯通电极TE1c。这里,第一直径比第二直径小,并且第三直径比第一直径小。
例如,可以如下形成小直径贯通电极TE1c和耦合电极TE3。
首先,在半导体晶片SW的主表面一侧上形成多个半导体元件。
接下来,蚀刻半导体晶片SW,并且在半导体晶片SW中形成小直径通孔(第一通孔;贯通孔;连接孔;或开口)。随后,在包括小直径通孔VI1c的底表面和侧表面的半导体晶片SW的主表面上形成第一绝缘膜IF1c之后,在半导体晶片SW的主表面上(第一绝缘膜IF1c上)形成阻挡金属膜BM1c、铜(Cu)籽晶层和铜(Cu)镀膜。随后,移除除了小直径通孔VI1c内部之外的区域中的铜(Cu)镀膜、籽晶层、阻挡金属膜BM1c和第一绝缘膜IF1c,以形成由小直径通孔VI1c内部的铜(Cu)膜构成的小直径贯通电极TE1c。
接下来,在半导体晶片SW的主表面上顺序形成停止绝缘膜SIF和层间绝缘膜ILD1。随后,顺序蚀刻层间绝缘膜ILD1和停止绝缘膜SIF以在元件形成区和TSV形成区中形成连接孔CN。随后,在半导体晶片SW的主表面上形成阻挡金属膜BP和钨(W)膜。
接下来,通过CMP方法移除除了连接孔CN内部之外的区域中的钨(W)膜和阻挡金属膜BP,在元件形成区中的连接孔CN内部形成由钨(W)膜构成的耦合电极CE,并且在TSV形成区中形成耦合电极TE3。也就是说,耦合电极TE3与电耦合nMISFET的栅电极GE等的耦合电极CE和形成在元件形成区中的第一层布线M1同时形成。
如上所述,形成具有比小直径贯通电极TE1c的第二直径小的第三直径的耦合电极TE3,而没有在层间绝缘膜ILD1和停止绝缘膜SIF中形成小直径贯通电极TE1c,并且耦合垫MC和小直径贯通电极TE1c可以利用该耦合电极TE3电耦合。该结果是,占据层间绝缘膜ILD1和停止绝缘膜SIF的贯通电极的区域变得比在层间绝缘膜ILD1、停止绝缘膜SIF和半导体晶片SW中形成小直径贯通电极TE1的情形(参考上述的图1)小。特别地,当耦合电极TE3自身占据的区域变小时,也可以使耦合至耦合电极TE3的耦合垫MC的平面面积小,从而可以布置第一层布线M1的区域变大,并且布置第一层布线M1的自由度变高。
<<第三修改>>
将利用图20说明根据第一实施例的第三修改的贯通电极。图20是贯通电极的主要部分截面图。
虽然在上述图1中示出的半导体器件中,小直径贯通电极TE1、大直径贯通电极TE2和耦合垫MC由互相不同的金属导体构成,小直径贯通电极TE1的一端经由阻挡金属膜耦合至耦合垫MC,并且上述一端的相反侧上的另一端经由阻挡金属膜BM1和BM2耦合至大直径贯通电极TE2,本发明不限于此。
例如,如图20所示,可以利用同一金属导体一体形成小直径贯通电极TE1d和耦合垫MCd。该结果是,小直径贯通电极TE1d可以与形成在元件形成区中的第一层布线M1同时形成。
例如,小直径贯通电极TE1d和耦合垫MCd可以如下形成。
首先,在半导体晶片SW的主表面一侧上形成多个半导体元件。随后,在半导体晶片SW的主表面上顺序形成停止绝缘膜SIF和层间绝缘膜ILD1之后,顺序蚀刻停止绝缘膜SIF和层间绝缘膜ILD1,在元件形成区中形成连接孔CN,并且在连接孔CN内部形成耦合电极CE。
接下来,在半导体晶片SW的主表面上形成层间绝缘膜ILD2之后,在元件形成区的层间绝缘膜ILD2中形成布线形成沟槽TRa,并且在TSV形成区的层间绝缘膜ILD2中形成耦合垫形成沟槽TRb。此外,从耦合垫形成沟槽TRb的底表面的一部分顺序蚀刻层间绝缘膜ILD1、停止绝缘膜SIF和半导体晶片SW,以形成小直径通孔VI1。
接下来,在包括小直径通孔VI1、布线形成沟槽TRa和耦合垫形成沟槽TRb的各个底表面和侧表面的半导体晶片SW的主表面上形成第一绝缘膜IF1d之后,移除布线形成沟槽TRa的底表面的第一绝缘膜IF1d。
接下来,在半导体晶片SW的主表面上(在第一绝缘膜IF1d上)形成阻挡金属膜BM1d、铜(Cu)籽晶层和铜(Cu)镀膜。随后,移除除了小直径通孔VI1、布线形成沟槽TRa和耦合垫形成沟槽TRa各自内部之外的区域中的铜(Cu)镀膜、籽晶层、阻挡金属膜BM1d和第一绝缘膜IF1d。该结果是,与在布线形成沟槽TRa内部形成由铜(Cu)膜构成的第一层布线M1同时,一体形成由掩埋在小直径通孔VI1内部的铜(Cu)膜构成的小直径贯通电极TE1d和由掩埋在耦合垫形成沟槽TRb内部的铜(Cu)膜构成的耦合垫MCd。
如上所述,小直径贯通电极TE1d与第一层布线M1和耦合垫MCd同时形成,由此,与在分别执行在小直径通孔VI1中掩埋金属导体的步骤和在布线形成沟槽TRa和耦合垫形成沟槽TRb中掩埋金属导体的步骤的制造方法中相比,可以大大减少制造步骤的数量。
(第二实施例)
将利用图21和22说明根据本第二实施例的包括TSV的半导体器件。图21是示出在从平面观察根据第二实施例的TSV形成区时的小直径贯通电极和大直径贯通电极的布置的主要部分平面图。图22是示出在从平面观察由本发明人比较并研究的TSV形成区时的小直径贯通电极和大直径贯通电极的布置的主要平面图。
实际上,如利用上述第一实施例的图2所述的,在布置于半导体芯片SC中心的TSV形成区中形成几百个贯通电极(例如,五十乘六)。然而,为了方便,在图21和22中描述了十二个贯通电极(四乘三)。
如图21所示,根据第二实施例在TSV形成区ATSV1中布置了多个分别由一个小直径贯通电极(由阴影表示的区域)TE1和一个大直径贯通电极TE2构成的贯通电极。另外,大直径贯通电极TE2彼此以等间隔(例如,40μm节距)布置成线,在平面图中,小直径贯通电极TE1的直径比大直径贯通电极TE2的直径小,并且在平面图中,小直径贯通电极TE1位于大直径贯通电极TE2内部。
然而,在位于TSV形成区ATSV1中的最外侧上的贯通电极中,在平面图中,小直径贯通电极TE1的中心位置和大直径贯通电极TE2的中心位置彼此不重合,并且小直径贯通电极TE1的中心位置已经在与TSV形成区ATSV1的外围相反的方向上从大直径贯通电极TE2的中心位置移动。要注意,在除了上述之外的贯通电极中,在平面图中,小直径贯通电极TE1的中心位置和大直径贯通电极TE2的中心位置彼此重合。
由图21中的点线指示了限制半导体元件布置的区域(排除区域)KOZ。由于位于TSV形成区ATSV1中的最外侧上的贯通电极的小直径贯通电极TE1布置在离开TSV形成区ATSV1的外围的方向上,所以限制半导体元件布置的区域(排除区域)KOZ也移动到TSV形成区ATSV1内部。
作为比较例,在图22中示出了TSV形成区ATSV2,其中在平面图中小直径贯通电极TE1的中心位置和大直径贯通电极TE2的中心位置彼此重合的贯通电极已经被布置在整个区域中。虽然TSV形成区ATSV2中的大直径贯通电极TE2的布置与图21中示出的TSV形成区ATSV1中的大直径贯通电极TE2相同,但在TSV形成区ATSV2中,限制半导体元件布置的区域(排除区域)KOZ与大直径贯通电极TE2同心地展开。因此,TSV形成区ATSV2指的是还包括与大直径贯通电极TE2同心地展开并且限制了半导体元件布置的区域(排除区域)KOZ的区域。
图22中示出的TSV形成区ATSV2由图21中的长虚点线指示。其指出,根据第二实施例的TSV形成区ATSV1的平面面积比TSV形成区ATSV2的平面面积小。
如上所述,在第二实施例中,位于TSV形成区ATSV1的最外侧上的贯通电极的小直径贯通电极TE1布置在离开TSV形成区ATSV1的外围的方向上,由此限制半导体元件布置的区域(排除区域)KOZ可以移动到TSV形成区ATSV1内部。该结果是,由于TSV形成区ATSV1的平面面积变小,并且与减小的平面面积对应的区域可以用作元件形成区,所以能够实现半导体元件的高度集成或半导体芯片的尺寸减小。
在上文中,虽然已基于实施例具体说明了本发明人做出的发明,但本发明不限于上述的实施例,并且不必说可以在不脱离本发明的精神的前提下做出各种改变。
Claims (8)
1.一种半导体器件,包括:
第一区域,在所述第一区域已经形成有从半导体衬底的第一主表面贯穿到在所述第一主表面的相反侧上的第二主表面的多个贯通电极;以及
第二区域,在所述第二区域,在所述半导体衬底的所述第一主表面上已经形成有多个半导体元件,
其中所述多个贯通电极中的每个由以下构成:
第一贯通电极,所述第一贯通电极具有第一直径,并且形成在所述半导体衬底的所述第一主表面侧上;以及
第二贯通电极,所述第二贯通电极具有比所述第一直径大的第二直径,并且形成在所述半导体衬底的所述第二主表面侧上,
其中在所述多个贯通电极中的每个中,在平面图中,所述第一贯通电极位于所述第二贯通电极的内部,并且在平面图中,所述第一贯通电极的中心位置离开所述第二贯通电极的中心位置,
其中在平面图中,在所述第一区域中的所述多个贯通电极分别以相同的节距布置,并且
其中在平面图中,位于所述第一区域的最外侧的、所述多个贯通电极当中的最外侧贯通电极的所述第一贯通电极的所述中心位置被布置在离开所述第一区域的外围的方向上。
2.根据权利要求1所述的半导体器件,
其中所述贯通电极的全部或一部分由一个所述第二贯通电极和多个所述第一贯通电极构成。
3.根据权利要求1所述的半导体器件,进一步包括:
层间绝缘膜,所述层间绝缘膜形成在所述半导体衬底的所述第一主表面上,以便覆盖所述半导体元件;以及
耦合垫或布线,所述耦合垫或所述布线形成在所述第一区域的所述层间绝缘膜上,
其中所述第一贯通电极具有从所述层间绝缘膜的顶表面贯穿到下表面的部分,
其中所述第一贯通电极的一端耦合到所述耦合垫或所述布线,并且
其中在所述第一贯通电极的所述一端的相反侧上的另一端耦合到所述第二贯通电极。
4.根据权利要求1所述的半导体器件,进一步包括:
层间绝缘膜,所述层间绝缘膜形成在所述半导体衬底的所述第一主表面上,以便覆盖所述半导体元件;以及
耦合电极,所述耦合电极从顶表面到下表面贯穿所述第一区域的所述层间绝缘膜,
其中所述第一贯通电极的一端耦合到所述耦合电极,并且
其中在所述第一贯通电极的所述一端的相反侧上的另一端耦合到所述第二贯通电极。
5.根据权利要求1所述的半导体器件,进一步包括:
层间绝缘膜,所述层间绝缘膜形成在所述半导体衬底的所述第一主表面上,以便覆盖所述半导体元件;
耦合垫或第一布线,所述耦合垫或所述第一布线形成在所述第一区域的所述层间绝缘膜上;以及
第二布线,所述第二布线形成在所述第二区域的所述层间绝缘膜上,
其中所述第一贯通电极具有从所述层间绝缘膜的顶表面贯穿到下表面的部分,并且
其中由相同的金属导体整体地形成所述第一贯通电极与所述耦合垫或所述第一布线。
6.根据权利要求5所述的半导体器件,
其中在所述第一区域中由所述金属导体形成所述第一贯通电极和所述耦合垫,或者所述第一贯通电极和所述第一布线,并且在所述第二区域中由所述金属导体形成所述第二布线。
7.根据权利要求1所述的半导体器件,
其中在所述半导体衬底和所述第一贯通电极之间,从所述半导体衬底侧,形成有第一绝缘膜和第一阻挡金属膜,并且
其中在所述半导体衬底和所述第二贯通电极之间,从所述半导体衬底侧,形成有与所述第一绝缘膜不同的第二绝缘膜和与所述第一阻挡金属膜不同的第二阻挡金属膜。
8.根据权利要求1所述的半导体器件,
其中在所述第一贯通电极和所述第二贯通电极之间形成有阻挡金属膜。
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KR102019352B1 (ko) | 2016-06-20 | 2019-09-09 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
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KR102554692B1 (ko) | 2019-02-18 | 2023-07-12 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 집적 구조체 및 형성 방법 |
JP7278184B2 (ja) | 2019-09-13 | 2023-05-19 | キオクシア株式会社 | 半導体装置の製造方法 |
KR20210120399A (ko) | 2020-03-26 | 2021-10-07 | 삼성전자주식회사 | 관통 실리콘 비아를 포함하는 집적 회로 반도체 소자 |
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