JP4327644B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4327644B2 JP4327644B2 JP2004108442A JP2004108442A JP4327644B2 JP 4327644 B2 JP4327644 B2 JP 4327644B2 JP 2004108442 A JP2004108442 A JP 2004108442A JP 2004108442 A JP2004108442 A JP 2004108442A JP 4327644 B2 JP4327644 B2 JP 4327644B2
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- plug
- semiconductor device
- forming
- film
- hole
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Description
図1は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。図1の半導体装置100は、シリコン基板101、エッチングストッパ膜109、最下層絶縁膜111、第一配線層絶縁膜113の積層構造を有し、シリコン基板101、エッチングストッパ膜109、および最下層絶縁膜111を貫通する貫通電極135が設けられている。
まず、半導体装置100においては、貫通電極135が小径プラグ119および大径プラグ131の二つのプラグからなる。小径プラグ119の端部の突出部141は、大径プラグ131に内包されている。
第一の実施形態に記載の半導体装置100を以下のようにして作製することもできる。以下、図2(a)〜図2(d)を参照しつつ、第一の実施形態と異なる点を中心に説明する。
第一の実施形態に記載の半導体装置100を以下のようにして作製することもできる。以下、以下、図2(a)〜図2(d)を参照しつつ、第一または第二の実施形態と異なる点を中心に説明する。
101 シリコン基板
102 半導体装置
103 素子分離膜
104 半導体装置
105 拡散層
107 ゲート電極
109 エッチングストッパ膜
112 配線用絶縁膜
113 第一配線層絶縁膜
114 プラグ用絶縁膜
115 粘着剤層
117 支持体
119 小径プラグ
121 第一配線
122 接続プラグ
123 接続プラグ
125 パッド
127 バンプ
129 電着絶縁膜
131 大径プラグ
133 めっき膜
135 貫通電極
137 SiN膜
139 開口部
141 突出部
153 配線
154 配線
161 絶縁層
163 絶縁層
165 配線
167 接続プラグ
169 配線
171 接続プラグ
Claims (9)
- 半導体基板の素子形成面の側に第一の孔を形成する工程と、
前記第一の孔の内壁に、絶縁材料からなるバリア膜を形成する工程と、
前記第一の孔の内部を埋め込むように第一の金属膜を埋設する工程と、
前記第一の孔の外部に形成された前記第一の金属膜を除去し、前記第一の孔の内部に第一のプラグを形成する工程と、
裏面の側から前記半導体基板を選択的に除去して第二の孔を形成し、前記第二の孔の内部に前記第一のプラグの一部を露出させる工程と、
前記第二の孔の内面の前記第一のプラグを除く領域に選択的に絶縁材料を付着させる工程と、
絶縁材料を付着させる前記工程の後、露出した前記バリア膜の少なくとも一部を除去し、前記第一の金属膜を露出させる工程と、
前記第二の孔の内部を埋めるように選択的に第二の金属膜を成長させて、前記第一のプラグの一部を内包する第二のプラグを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、第二のプラグを形成する前記工程は、露出した前記第一の金属膜を起点として前記第二の孔の内部を埋めるように前記第二の金属膜を成長させる工程を含むことを特徴とする半導体装置の製造方法。
- 請求項1または2に記載の半導体装置の製造方法において、前記絶縁材料は電着材料であることを特徴とする半導体装置の製造方法。
- 請求項3に記載の半導体装置の製造方法において、前記電着材料は電着ポリイミドであることを特徴とする半導体装置の製造方法。
- 請求項1乃至4いずれかに記載の半導体装置の製造方法において、前記第二の孔は前記第一の孔よりも断面積が大きいことを特徴とする半導体装置の製造方法。
- 請求項1乃至5いずれかに記載の半導体装置の製造方法において、第二のプラグを形成する前記工程の前に、前記第二の孔の前記内面に金属のシード層を形成する工程を含み、
第二のプラグを形成する前記工程は、前記シード層を起点として前記第二の金属膜を成長させる工程を含むことを特徴とする半導体装置の製造方法。 - 請求項1乃至6いずれかに記載の半導体装置の製造方法において、第二の孔を形成する前記工程の後、絶縁材料を付着させる前記工程の前に、前記第二の孔の前記内面の前記第一のプラグを除く前記領域に選択的に金属のシード層を形成する工程を含み、
絶縁材料を付着させる前記工程は、前記シード層に前記絶縁材料を付着させる工程を含むことを特徴とする半導体装置の製造方法。 - 請求項1乃至7いずれかに記載の半導体装置の製造方法において、第一の孔を形成する前記工程は、前記半導体基板の前記素子形成面の側に絶縁膜を形成した後、前記第一の孔を形成する領域の前記絶縁膜を選択的に除去する工程を含むことを特徴とする半導体装置の製造方法。
- 請求項8に記載の半導体装置の製造方法において、
第一のプラグを形成する前記工程の後に、前記半導体基板の前記絶縁膜上に配線層を形成する工程を含み、
配線層を形成する前記工程は、前記第一のプラグに接続する配線を形成する工程を含むことを特徴とする半導体装置の製造方法。
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