CN108630647B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN108630647B
CN108630647B CN201710650835.5A CN201710650835A CN108630647B CN 108630647 B CN108630647 B CN 108630647B CN 201710650835 A CN201710650835 A CN 201710650835A CN 108630647 B CN108630647 B CN 108630647B
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contact hole
semiconductor substrate
spacer film
film
semiconductor
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CN108630647A (zh
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久米一平
中村一彦
野田有辉
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明的实施方式提供一种能够减小贯通电极与半导体元件之间的接触电阻的半导体装置及其制造方法。本实施方式的半导体装置具备半导体衬底，所述半导体衬底具有第1面及第2面，所述第1面具有半导体元件，所述第2面位于该第1面的相反侧。第1绝缘膜设置在半导体衬底的第1面上。导电体设置在第1绝缘膜上。金属电极设置在第1面与第2面之间，贯通半导体衬底并与导电体接触。第2绝缘膜设置在金属电极与半导体衬底之间。第1绝缘膜与第2绝缘膜的边界面位于较半导体衬底的第1面更靠导电体侧，且随着向金属电极的中心部靠近而以向导电体接近的方式倾斜。

Description

半导体装置及其制造方法
[相关申请案]
本申请案享有以日本专利申请案2017-53588号(申请日：2017年3月17日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
半导体存储器等半导体芯片有自高功能化或高集成化等观点考虑进行积层的情况。为了将所积层的多个半导体芯片间的元件电连接，而使用被称为TSV(Through-SiliconVia，硅穿孔)的贯通电极。TSV贯通衬底而将该衬底的元件与其他衬底的元件电连接。为了不对元件的特性造成影响，期望TSV的寄生电阻及寄生容量较小。
然而，TSV本身由金属形成，虽然为低电阻，但形成在衬底上的TSV用的接触孔的纵横比较高。因此，存在接触孔底部上的TSV与配线的接触面积变小，TSV与配线的接触电阻变高的问题。
发明内容
本发明的实施方式提供一种能够减小贯通电极与半导体元件之间的接触电阻的半导体装置及其制造方法。
本实施方式的半导体装置具备半导体衬底，所述半导体衬底具有第1面及第2面，所述第1面具有半导体元件，所述第2面位于该第1面的相反侧。第1绝缘膜设置在半导体衬底的第1面上。导电体设置在第1绝缘膜上。金属电极设置在第1面与第2面之间，贯通半导体衬底并与导电体接触。第2绝缘膜设置在金属电极与半导体衬底之间。第1绝缘膜与第2绝缘膜的边界面位于较半导体衬底的第1面更靠导电体侧，且随着向金属电极的中心部靠近以向导电体接近的方式倾斜。
附图说明
图1是表示第1实施方式的半导体芯片的构成例的截面图。
图2是更详细地表示较配线构造更靠第2面侧的构造的截面图。
图3是表示边界面未倾斜的构造的截面图。
图4是表示第1实施方式的半导体芯片的制造方法的一例的截面图。
图5是继图4之后表示半导体芯片的制造方法的截面图。
图6是继图5之后表示半导体芯片的制造方法的截面图。
图7是继图6之后表示半导体芯片的制造方法的截面图。
图8是表示第2实施方式的半导体芯片的构成例的截面图。
图9是表示第2实施方式的半导体芯片的制造方法的一例的截面图。
图10是继图9之后表示半导体芯片的制造方法的一例的截面图。
图11是继图10之后表示半导体芯片的制造方法的一例的截面图。
具体实施方式
以下，参照图式对本发明之实施方式进行说明。本实施方式并不限定本发明。在以下实施方式中，半导体衬底的上下方向表示以设置有半导体元件的面或其相反侧的面为上表面时的相对方向，有与依据重力加速度的上下方向不同的情况。
(第1实施方式)
图1是表示第1实施方式的半导体芯片的构成例的截面图。半导体芯片1可为具有例如NAND(与非)型EEPROM(Electrically Erasable and Programmable Read-OnlyMemory，电可擦除可编程只读存储器)等的半导体芯片。在图1中表示半导体芯片1的TSV及其周边部。
半导体芯片1具备半导体衬底10、STI(Shallow Trench Isolation，浅沟槽隔离)20、焊垫(凸块)30、TSV40、间隔膜50及凸块60。
半导体衬底10例如为硅衬底，薄膜化为例如约30μm以下。半导体衬底10具有第1面F1及位于第1面F1的相反侧的第2面F2。半导体衬底10的第1面F1具有形成半导体元件的主动区域、及将主动区域间电分离的STI(Shallow Trench Isolation)20。在主动区域形成有存储单元阵列、晶体管、电阻元件、电容元件等半导体元件(未图示)。在STI20使用例如氧化硅膜等绝缘膜。在STI20上未设置半导体元件，但设置有将半导体元件与TSV40电连接的焊垫30及配线构造35。以下，也将焊垫30与配线构造35统称为导电体30、35。在半导体衬底10的第2面F2上未设置半导体元件及配线，但设置有与TSV40电连接的凸块60等。
作为第1绝缘膜的STI20设置在半导体衬底10的第1面F1上。如上所述，在STI20使用例如氧化硅膜等绝缘膜。
导电体30、35设置在STI20上，与设置在半导体衬底10的第1面F1上的半导体元件(例如晶体管)电连接。焊垫30使用例如钨或钛等低电阻金属。在配线构造35使用例如多晶硅、所述低电阻金属等。
作为金属电极的TSV40及障壁金属BM设置在半导体衬底10的第1面F1与第2面F2之间，贯通半导体衬底10。进而，TSV40及障壁金属BM贯通STI20而与导电体30、35电连接。由此，TSV40及障壁金属BM将与位于第1面F1侧的导电体30、35的电性连接延长至第2面F2侧为止。TSV40使用例如镍等低电阻金属。障壁金属BM设置在间隔膜50的侧面。障壁金属BM使用例如Ti、Ta、Ru或其积层膜。以下，也将TSV40及障壁金属BM统称为金属电极40、BM。再者，只要能够将TSV40良好地埋入于接触孔CH内，则并不一定必需设置障壁金属BM。
作为第2绝缘膜的间隔膜50设置在金属电极40、BM与半导体衬底10之间，将金属电极40、BM与半导体衬底10电分离。此外，间隔膜50也设置在半导体衬底10的第2面F2上。间隔膜50使用例如氧化硅膜等绝缘膜。
凸块60在半导体衬底10的第2面F2侧设置在TSV40上。凸块60使用例如锡、铜等金属。
图2是更详细地表示较配线构造35更靠第2面F2侧的构造的截面图。在图2中，为了容易理解，示意性地强调表示TSV40或障壁金属BM与导电体30、35的连接部分。
此处，STI20及间隔膜50的边界面Fb1较半导体衬底10的第1面F1更靠导电体30、35侧，且随着靠近TSV40的中心部以接近导电体30、35的方式倾斜。也就是说，边界面Fb1较半导体衬底10的第1面F1更靠近导电体30、35，且朝向TSV40的中心部，向远离半导体衬底10的方向倾斜。进而换言之，边界面Fb1位于半导体衬底10与TSV40之间，朝向设置有TSV40的接触孔CH的中心部(TSV40的中心部)而逐渐向导电体30、35靠近。因此，在具有接触孔CH的区域，STI20的厚度随着向TSV40的中心部靠近而变薄。
此外，伴随边界面Fb1的倾斜，TSV40或障壁金属BM与间隔膜50或STI20之间的边界面Fb2也沿边界面Fb1倾斜。例如，边界面Fb2在半导体衬底10的第1面F1的附近(TSV40的上部)具有略倒锥形，或者成为与第1面F1大致垂直的面。边界面Fb2在半导体衬底10的第2面F2的附近的边界面Fb1的正上方，向TSV40的中心部靠近，随着向TSV40的中心部靠近，以向导电体30、35接近的方式倾斜。进而，边界面Fb2向与第1面F1垂直的方向靠近并到达至导电体30、35为止。
如此，根据本实施方式，半导体衬底10与金属电极40、BM之间的间隔膜50的内侧面几乎无与第1面F1大致平行的面，而在与第1面F1大致垂直的方向上延伸或者平滑地倾斜。
图3是表示边界面Fb1未倾斜的构造的截面图。假设在像图3那样边界面Fbl未倾斜，而与半导体衬底10的第1面F1或第2面F2大致平行(例如，与第2面F2为大致同一平面)的情况下，边界面Fb2也与半导体衬底10的第1面F1或第2面F2大致平行。在此情况下，间隔膜50正下方的STI20的厚度与半导体衬底10之下的STI20的厚度大致相同。因此，接触孔CH的底面积变小，TSV40及障壁金属BM与导电体30、35之间的接触电阻变高。此外，在边界面Fbl未倾斜而与第2面F2为大致同一平面时，像图3那样，间隔膜50的内侧面具有级差ST。当在间隔膜50的内侧面有级差ST时，设置在间隔膜50的内侧面的障壁金属的覆盖变差，难以填充TSV40的金属材料。
相对于此，根据本实施方式，像图2那样，半导体衬底10与金属电极40、BM之间的间隔膜50的内侧面几乎无与第1面F1大致平行的面，而在与第1面F1大致垂直的方向上延伸或者平滑地倾斜。由此，在接触孔CH下方的区域，STI20的厚度随着向金属电极40、BM的中心部靠近而变薄。在此情况下，间隔膜50与STI20的膜厚的和随着向接触孔CH的中心部靠近而变薄。由此，当对接触孔CH的底部进行蚀刻时，接触孔CH变得容易贯通间隔膜50及STI20。因此，即便是短时间的过蚀刻，形成在间隔膜50及STI20上的接触孔CH的直径也会变大。由此，接触孔CH的底面积相对变大，金属电极40、BM与导电体30、35之间的接触电阻变低。此外，在对接触孔CH的底部进行蚀刻时，可缩短过蚀刻的时间，因此，能够抑制接触孔CH穿透配线构造35。
进而，半导体衬底10与金属电极40、BM之间的间隔膜50的内侧面在与第1面F1大致垂直的方向上延伸或者平滑地倾斜。由此，在间隔膜50的内侧面无级差ST，障壁金属BM的覆盖变得良好。因此，也容易填充TSV40的金属材料。
其次，对本实施方式的半导体芯片1的制造方法进行说明。
图4～图7是表示第1实施方式的半导体芯片的制造方法的一例的截面图。为了容易理解TSV40或障壁金属BM与导电体30、35的连接部分的形成方法，图5～图7与图2相同地表示示意性的截面图。
以下，主要说明在半导体芯片1上形成TSV40的方法。
首先，在半导体衬底10的第1面F1上形成STI20而决定主动区域。半导体衬底10例如为硅衬底。STI20例如为氧化硅膜。其次，在主动区域形成半导体元件(未图示)。半导体元件可为例如存储单元阵列、晶体管、电阻元件、电容元件等。在形成半导体元件时，在STI20上形成例如配线构造35。半导体元件及配线构造35由绝缘膜37、38被覆。其次，焊垫30以与配线构造35连接的方式形成。因此，在STI20上形成导电体30、35。
其次，使用光刻技术及RIE(Reactive Ion Etching，反应性离子蚀刻)法，从位于与第1面F1为相反侧的半导体衬底10的第2面F2对半导体衬底10进行蚀刻。也就是说，将光阻层80用作掩膜，从与形成有半导体元件的第1面F1为相反侧的第2面F2(背面)形成接触孔CH。由此，形成从第2面F2到达至第1面F1的接触孔CH。为了使TSV40与导电体30、35连接，接触孔CH形成在STI20的区域中存在导电体30、35的区域上。通过形成接触孔CH而使STI20露出。
其次，像图5那样，使用RIE法对位于接触孔CH的底面的ST120的一部分进行蚀刻。此时，STI20的材料(例如，氧化硅膜)的蚀刻气体与半导体衬底10的材料(例如，硅)的蚀刻气体不同。例如，硅的蚀刻气体为SF6、SiF4、CF4、C4F8、Ar、HBr、O2气体或其等的混合气体等。氧化硅膜的蚀刻气体为CF4、CHF3、Ar、O2气体或其等的混合气体等。因此，STI20的蚀刻步骤与半导体衬底10的蚀刻步骤不同。例如，可在半导体衬底10的蚀刻后，使用与进行半导体衬底10的蚀刻的装置不同的装置执行STI20的蚀刻。或者也可在与半导体衬底10的蚀刻为同一装置内执行STI20的蚀刻，但需要更换蚀刻气体。
相较于接触孔CH的底部的中心部，蚀刻气体的离子更难以到达其端部，因此，像图5那样，在接触孔CH的底部，STI20的中心部的膜厚T20c相较于其端部的膜厚T20e变薄。由此，接触孔CH的底面呈碗型凹陷。也就是说，接触孔CH的底面较半导体衬底10的第1面F1更向导电体30、35侧凹陷，且随着向接触孔CH的中心部靠近而以向导电体30、35接近的方式倾斜。因此，STI20的厚度随着向接触孔CH的中心部靠近而变薄。
去除光阻层80后，像图6那样，使用CVD(Chemical Vapor Deposition，化学气相沉积)法或ALD(Atomic Layer Deposition，原子层沉积)法，在接触孔CH的内侧面、底面及半导体衬底10的第2面F2上形成间隔膜50。间隔膜50沿接触孔CH的内表面形成，因此，形成在接触孔CH的底面上的间隔膜50沿接触孔CH的碗型以良好的覆盖形成在半导体衬底10及STI20上。
此外，间隔膜50与接触孔CH的底面大致相同地呈碗型凹陷。也就是说，接触孔CH的底面的间隔膜50随着向接触孔CH的中心部靠近而以接近导电体30、35的方式倾斜。伴随于此，STI20及间隔膜50的边界面Fb1也较半导体衬底10的第1面F1更靠导电体30、35侧，且随着向接触孔CH的中心部靠近而以向导电体30、35接近的方式倾斜。也就是说，边界面Fbl较半导体衬底10的第1面F1更靠近导电体30、35，且朝向填充TSV40的接触孔CH的中心部而向远离半导体衬底10的方向倾斜。
此外，实际上，接触孔CH的纵横比相对较高，因此，形成在接触孔CH的开口部的间隔膜50相较于形成在接触孔CH的内部的间隔膜50变厚。因此，像图6那样，间隔膜50在接触孔CH的开口端在与第1面F1大致平行的方向上突出。以下，也将间隔膜50在接触孔CH的开口端突出的部分称为悬突部分OH。这种间隔膜50的悬突部分OH使接触孔CH的开口直径比接触孔CH的中间部分的直径稍窄。像图6那样，如果将间隔膜50的悬突部分OH的接触孔CH的开口直径设为φ1，将接触孔CH的中间部分的直径设为φ2，那么φ1<φ2。
其次，像图7那样，将位于接触孔CH的内侧面及半导体衬底10的第2面F2上的间隔膜50用作掩膜，利用RIE法对接触孔CH的底部的间隔膜50及STI20进行蚀刻。由此，接触孔CH贯通间隔膜50及STI20并到达至位于STI20之下的导电体30、35。也就是说，接触孔CH延长至STI20之下的导电体30、35。此时，如上所述，通过间隔膜50的悬突部分OH，接触孔CH的开口直径φ1相较于接触孔CH的中间部分的直径φ2变窄。将间隔膜50的悬突部分OH作为掩膜而对接触孔CH的底部的间隔膜50及STI20进行蚀刻。因此，形成在间隔膜50及STI20上的下部的接触孔CH的直径大致成为φ1。
另一方面，接触孔CH的底面呈碗型凹陷，STI20及间隔膜50的中心部的膜厚的和Ttlc相较于其等的端部的膜厚的和TtIe变薄。因此，间隔膜50及STI20变得容易贯通，即便为短时间的过蚀刻，也能够相对增大形成在间隔膜50及STI20上的接触孔CH的直径φc。由此，接下来形成的TSV40与导电体30、35之间的接触电阻变低。此外，能够使过蚀刻进行的时间短，因此，能够抑制接触孔CH穿透配线构造35。进而，由于接触孔CH的底面呈碗型凹陷，故而接触孔CH的内侧面几乎无与第1面F1大致平行的面，而在与第1面F1大致垂直的方向上延伸或者平滑地倾斜。也就是说，接触孔CH的内侧面成为几乎无级差的平滑的倾斜面。因此，以下说明的障壁金属BM及TSV40的覆盖变得良好。
其次，像图2那样，在接触孔CH内形成障壁金属BM，沉积TSV40的金属材料。由此，在接触孔CH内形成金属电极40、BM。障壁金属BM使用例如Ti、Ta、Ru或其积层膜。TSV40使用例如镍等金属材料。由此，能够使金属电极40、BM与导电体30、35连接，且能够向第2面F2侧引出。此时，如上所述，接触孔CH的内侧面成为几乎无级差的平滑的倾斜面。由此，障壁金属BM及TSV40的金属材料的覆盖变得良好。
其次，使用光刻技术及RIE法，对TSV40及障壁金属BM进行加工。由此，去除位于第2面F2(场)上的TSV40及障壁金属BM的材料。
其次，像图2那样，使用镀覆法等，在TSV40上形成凸块60。凸块60使用例如锡等。由此，完成本实施方式的半导体芯片1。再者，其后，可将半导体芯片1与其他半导体芯片积层，并经由TSV40及凸块60等与其他半导体芯片电连接。
如此，根据本实施方式，在对半导体衬底10进行蚀刻之后且形成间隔膜50之前，对接触孔CH底部的STI20的上部进行蚀刻。由此，接触孔CH的底部呈碗型凹陷，间隔膜50的覆盖变得良好。进而，间隔膜50也与接触孔CH的底面大致相同地呈碗型凹陷。由此，STI20及间隔膜50的厚度随着向接触孔CH或TSV40的中心部靠近而变薄，因此，在对接触孔CH的底部进行蚀刻时，接触孔CH变得容易贯通间隔膜50及STI20。因此，形成在间隔膜50及STI20上的接触孔CH的直径相对变大，金属电极40、BM与导电体30、35之间的接触电阻变低。而且，可缩短过蚀刻，因此，能够抑制接触孔CH穿透配线构造35。进而，在间隔膜50的内侧面无级差ST，因此，障壁金属BM或TSV40的金属材料的覆盖变得良好。
(第2实施方式)
图8是表示第2实施方式的半导体芯片的构成例的截面图。第2实施方式的半导体芯片1在TSV40或间隔膜50等的形状方面与第1实施方式不同。第2实施方式的其他构成可与第1实施方式的对应的构成相同。再者，图8也与图2相同地，为了容易理解，而示意性地强调表示TSV40或障壁金属BM与导电体30、35的连接部分。
在第2实施方式的半导体芯片1中，在与半导体衬底10的第1面F1及第2面F2大致垂直的方向的剖面上，将位于金属电极40、BM的两侧的金属电极40、BM与STI20之间的边界面设为第1边界面Fb11及第2边界面Fb12，将位于金属电极40、BM的两侧的间隔膜50与半导体衬底10的边界面设为第3边界面Fb13及第4边界面Fb14。此时，第1边界面Fb11与第2边界面Fb12之间的中心C11_12，从第3边界面Fb13与第4边界面Fb14之间的中心C13_14向第1方向D1偏移。
此外，位于半导体衬底10的第2面F2侧的金属电极40、BM与间隔膜50之间的边界面中位于第1方向D1上的边界面，在第2面F2侧的端部E21弯曲(带弧度)。也就是说，间隔膜50的上表面F50t1与侧面F50s1之间的端部E21以倒角的方式切削，相对于该上表面F50t1及侧面F50s1两者倾斜。另一方面，金属电极40、BM与间隔膜50之间的边界面中位于与第1方向D1为反方向的方向上的边界面，不在第2面F2侧的端部E22弯曲。也就是说，间隔膜50的上表面F50t2与侧面F50s2之间的端部E22未被倒角，与该上表面F50t2或侧面F50s2的任一者成为大致同一平面。
如此，从TSV40的中心观察，第1边界面Fb11与第2边界面Fb12之间的中心C11_12的偏离方向D1，与设置有弯曲的边界面Fb21的方向成为大致同一方向。这种构造可通过如下的半导体芯片1的制造方法形成。
图9～图11是表示第2实施方式的半导体芯片的制造方法的一例的截面图。以下，主要说明在半导体芯片1上形成TSV40的方法。
至形成接触孔CH为止的步骤可与第1实施方式相同。再者，在第2实施方式中，在该阶段不执行位于接触孔CH的底面的STI20的蚀刻。因此，接触孔CH的底面为与第1或第2面F1、F2大致平行的状态。
其次，像图9那样，使用CVD法或ALD法，在接触孔CH的内侧面、该接触孔CH的底面及半导体衬底10的第2面F2形成间隔膜50。此时，接触孔CH的纵横比相对较高，因此，间隔膜50在接触孔CH的开口端具有悬突部分OH。再者，如下所述，在第2面F2上的间隔膜50上形成抗蚀膜70。由此，第2面F2上的间隔膜50的膜厚增厚抗蚀膜70的厚度的量，包含间隔膜50及抗蚀膜70的掩膜材的膜厚充分变厚。由此，间隔膜50不需要考虑作为掩膜材的功能而形成得过厚，相对较薄即可。通过使间隔膜50的膜厚较薄，间隔膜50的悬突部分OH变小。由此，能够使接触孔CH的开口直径Φ1相对变大。由此，结果是金属电极40、BM与导电体30、35的接触面积变大，接触电阻变小。
其次，像图10那样，使用光刻技术，在位于半导体衬底10的第2面F2上的间隔膜50上形成抗蚀膜70作为掩膜材的一部分。当将抗蚀膜70涂布在半导体衬底10的第2面F2上时，抗蚀膜70可进入至接触孔CH内，也可不进入至接触孔CH内。通过抗蚀膜70的曝光与显影而去除位于接触孔CH上的抗蚀膜70，残留其他抗蚀膜70。由此，像图10那样，抗蚀膜70的开口部OP70以与接触孔CH的开口部OPch大致对应的方式形成。
然而，抗蚀膜70的开口部OP70的中心C70不与接触孔CH的开口部的中心Cch1一致。因此，像图10那样，从第2面F2的上方观察时，间隔膜50的一端部E22被抗蚀膜70遮掩，另一端部E21从抗蚀膜70露出。例如，抗蚀膜70的D1方向的端部E70_1相较于间隔膜50的D1方向的端部E21更向D1方向引退。另一方面，抗蚀膜70的与D1方向为相反方向的端部E70_2相较于间隔膜50的与D1方向为相反方向的端部E22向D1方向突出。端部E21或抗蚀膜70的端部E70_2的突出量例如为约1μm。
从第2面F2的上方观察时，抗蚀膜70的端部E70_1优选位于间隔膜50的端部E21与半导体衬底10的端部E11之间。由此，能够抑制间隔膜50的端部E21被过度蚀刻，从而能够抑制半导体衬底10与金属电极40、BM电性短路。进而优选端部E70_1比间隔膜50的端部E21与半导体衬底10的端部E11之间的中间位置更靠近端部E21。由此，能够更确实地抑制半导体衬底10与金属电极40、BM的电性短路。
此外，如上所述，当在第2面F2上的间隔膜50之上形成抗蚀膜70时，能够使间隔膜50的膜厚较薄。由此，能够缩小间隔膜50的悬突部分OH。这有助于金属电极40、BM与导电体30、35的接触面积的扩大。
其次，像图11那样，将抗蚀膜70及间隔膜50用作掩膜，利用RIE法对位于接触孔CH的底部的间隔膜50及STI20进行蚀刻。此时，间隔膜50的端部E22被抗蚀膜70遮掩，因此，未被蚀刻。因此，端部E22保持90度或者较此为锐角的状态。另一方面，间隔膜50的端部E21从抗蚀膜70露出，因此，被蚀刻。由此，间隔膜50的端部E21以倒角地方式切削而带弧度。间隔膜50的端部E21相对于该上表面F50t1及侧面F50s1两者倾斜。
此外，在接触孔CH的底部，间隔膜50及STI20将向D1方向偏移的抗蚀膜70或间隔膜50作为掩膜进行蚀刻。因此，形成在间隔膜50及STI20上的下部的接触孔CH的中心Cch2，从形成在半导体衬底10上的上部的接触孔CH的中心Cch1向D1方向偏移。该偏移量与抗蚀膜70的开口部的中心C70相对于接触孔CH的开口部的中心Cch1的偏移量大致相同。如此，第1边界面Fb11与第2边界面Fb12之间的中心，从第3边界面Fb13与第4边界面Fb14之间的中心向第1方向D1偏移。
其次，以第1实施方式所说明的方式形成障壁金属BM、TSV40及凸块60。由此，完成图8所示的第2实施方式的半导体芯片1。
根据第2实施方式的制造方法，在形成间隔膜50之后，在第2面F2上形成抗蚀膜70。由此，包含间隔膜50与抗蚀膜70的掩膜材的膜厚在第2面F2上充分变厚，能够使间隔膜50的膜厚较薄。通过使间隔膜50的膜厚较薄而缩小悬突部分OH，接触孔CH的开口直径φ1变大。由此，金属电极40、BM与导电体30、35的接触面积变大，可减小其等的接触电阻。此外，通过缩小悬突部分OH而缓和间隔膜50的倒锥形状，因此，障壁金属BM或TSV40的金属材料的覆盖变得良好。
第2实施方式也可与第1实施方式组合。由此，金属电极40、BM与导电体30、35的接触面积进一步增大，且障壁金属BM或TSV40的金属材料的覆盖变得更好。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例而提示的，并不意欲限定发明的范围。这些实施方式可通过其他各种形态实施，可在不脱离发明的主旨的范围内，进行各种省略、替换、变更。这些实施方式或其变化与包含在发明的范围或主旨内同样地包含在权利要求书中所记载的发明及其均等的范围内。
[符号的说明]
1 半导体芯片
10 半导体衬底
20 STI
30 焊垫
35 配线构造
BM 障壁金属
40 TSV
50 间隔膜
60 凸块

Claims (1)

1.一种半导体装置，其特征在于具备：
半导体衬底，具有第1面及第2面，所述第1面具有半导体元件，所述第2面位于该第1面的相反侧；
第1绝缘膜，设置在所述半导体衬底的所述第1面上；
导电体，设置在所述第1绝缘膜上；
金属电极，设置在所述第1面与所述第2面之间，贯通所述半导体衬底并与所述导电体接触；及
第2绝缘膜，设置在所述金属电极与所述半导体衬底之间；且
当在与所述第1面及所述第2面垂直的方向的剖面中，将位于所述金属电极的两侧的所述金属电极与所述第1绝缘膜之间的边界面作为第1及第2边界面，将位于所述金属电极的两侧的所述第2绝缘膜与所述半导体衬底的边界面作为第3及第4边界面时，所述第1边界面与所述第2边界面之间的中心，从所述第3边界面与所述第4边界面之间的中心向第1方向偏移，
在所述剖面中，所述金属电极与所述第2绝缘膜之间的边界面中位于所述第1方向侧的边界面，在所述第2面侧的端部弯曲。
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