JP2014049500A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2014049500A JP2014049500A JP2012189177A JP2012189177A JP2014049500A JP 2014049500 A JP2014049500 A JP 2014049500A JP 2012189177 A JP2012189177 A JP 2012189177A JP 2012189177 A JP2012189177 A JP 2012189177A JP 2014049500 A JP2014049500 A JP 2014049500A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 264
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 239000000758 substrate Substances 0.000 claims abstract description 150
- 238000000034 method Methods 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims description 82
- 239000002184 metal Substances 0.000 claims description 82
- 230000004888 barrier function Effects 0.000 claims description 68
- 239000011229 interlayer Substances 0.000 claims description 54
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 10
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 5
- 238000010884 ion-beam technique Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 6
- 239000010949 copper Substances 0.000 description 136
- 230000015572 biosynthetic process Effects 0.000 description 83
- 239000010410 layer Substances 0.000 description 80
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 69
- 229910052802 copper Inorganic materials 0.000 description 69
- 208000036252 interstitial lung disease 1 Diseases 0.000 description 25
- 230000008569 process Effects 0.000 description 20
- 238000007747 plating Methods 0.000 description 19
- 239000010936 titanium Substances 0.000 description 16
- 229910004298 SiO 2 Inorganic materials 0.000 description 14
- 208000036971 interstitial lung disease 2 Diseases 0.000 description 13
- 230000035515 penetration Effects 0.000 description 13
- 230000004048 modification Effects 0.000 description 11
- 238000012986 modification Methods 0.000 description 11
- 229910052715 tantalum Inorganic materials 0.000 description 11
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 101000971638 Homo sapiens Kinesin-like protein KIF1A Proteins 0.000 description 7
- 102100021527 Kinesin-like protein KIF1A Human genes 0.000 description 7
- 238000011109 contamination Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910017052 cobalt Inorganic materials 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 229910052707 ruthenium Inorganic materials 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 208000029523 Interstitial Lung disease Diseases 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Abstract
【解決手段】貫通電極を、半導体基板SWの主面S1側に形成した第1径を有する小径貫通電極TE1と、半導体基板SWの裏面S2側に形成した、上記第1径よりも大きい第2径を有する大径貫通電極TE2とにより構成し、平面視において小径貫通電極TE1の中心位置と大径貫通電極TE2の中心位置とが重ならないように、平面視において小径貫通電極TE1を大径貫通電極TE2の内側に配置する。
【選択図】図1
Description
本実施の形態によるTSV技術を採用した半導体装置がより明確となると思われるため、本発明者らが比較検討を行った半導体装置における課題について説明する。
半導体基板SWに、その主面S1から主面S1と反対側の裏面S2へ貫通する貫通電極TEを形成すると、貫通電極TEを構成する銅(Cu)と半導体基板SWを構成するシリコン(Si)との熱膨張係数の違いにより、貫通電極TE周辺の半導体基板SWに歪が生じる。そのため、半導体素子が配置できる領域が制限される。例えば口径が5μmのビアVIを半導体基板SWに形成した場合、そのビアVIの外周から1μm程度の範囲が半導体素子の配置が制限される領域(キープ・アウト・ゾーン)となる。この半導体素子の配置が制限される領域(キープ・アウト・ゾーン)は、ビアVIの口径が大きくなる従い、すなわち、ビアVIの内部に埋め込まれる銅(Cu)の体積が増加するに従い広くなる。
半導体基板SWの裏面S2を加工して、半導体基板SWの厚さを薄くする際、貫通電極TEの下面を覆う絶縁膜I1の一部が除去されて、貫通電極TEの下面が露出することが懸念された。貫通電極TEの下面が露出すると、貫通電極TEを構成する銅(Cu)が半導体基板SWの裏面S2から半導体基板SW内へ拡散する。その結果、銅(Cu)汚染によって半導体基板SWの主面S1に形成されている半導体素子の動作特性が変動してしまう。
また、本発明者らはビアラスト・ビアバック方式(半導体基板の主面側に半導体素子及び多層配線を形成した後に、半導体基板の裏面側から半導体基板にビアを形成し、ビアの内部に貫通電極を埋設する方式)による貫通電極の製造工程についても検討した。
≪半導体装置≫
本実施の形態1によるTSVを備える半導体装置を図1及び図2を用いて説明する。図1は半導体装置の要部断面図、図2は半導体装置の要部裏面図である。
次に、本実施の形態1によるTSV技術を採用した半導体装置の製造方法について図3〜図17を用いて工程順に説明する。図3〜図17は、半導体装置の製造工程中の半導体装置の要部断面図であり、素子形成領域の一部及びTSV形成領域の一部を示している。また、図3〜図17の素子形成領域には、半導体素子としてnMISFETを例示する。また、半導体装置には、例えば100個以上の貫通電極が形成されるが、便宜上、図3〜図17には小径貫通電極及び大径貫通電極から成る1個の貫通電極及びその周辺部を記載する。
まず、図3に示すように、例えば単結晶シリコン(Si)から成る半導体基板(ウエハと称する平面略円形状の半導体の薄板)SWを用意する。半導体基板SWの厚さ(第1厚さ)は、例えば700μm程度である。次に、半導体基板SWの主面(表面、第1主面)の素子分離領域に絶縁膜から成る分離部IRを形成する。続いて、nMISFETが形成される領域の半導体基板SWにp型の導電性を示す不純物をイオン注入してp型ウェルPWを形成する。
次に、図4に示すように、レジストパターンをマスクとして、TSV形成領域の層間絶縁膜ILD1、ストッパ絶縁膜SIF及び半導体基板SWを順次エッチングして、層間絶縁膜ILD1、ストッパ絶縁膜SIF及び半導体基板SWに小径ビア(貫通穴、接続孔、開口部;第1ビア)VI1を形成する。小径ビアVI1の口径(径、内径;第1口径)は、例えば2μm程度、その深さは、例えば10μm程度である。
次に、図8に示すように、半導体基板SWの主面側に第1層目の配線M1、接続パッドMC、第2層目の配線M2、銅(Cu)バンプCB及び外部端子(はんだボール)SBを順次形成する。
次に、図9に示すように、半導体基板SWの主面側に、接着層CLを介してガラス支持体GHを貼り付ける。
実施の形態1の第1変形例による貫通電極を図18を用いて説明する。図18(a)及び(b)はそれぞれ小径貫通電極及び大径貫通電極の配置を説明する要部平面図である。
実施の形態1の第2変形例による貫通電極を図19を用いて説明する。図19は貫通電極の要部断面図である。
実施の形態1の第3変形例による貫通電極を図20を用いて説明する。図20は貫通電極の要部断面図である。
本実施の形態2によるTSVを備える半導体装置を図21及び図22を用いて説明する。図21は実施の形態2によるTSV形成領域を平面視したときの小径貫通電極及び大径貫通電極の配置を説明する要部平面図である。図22は本発明者らによって比較検討されたTSV形成領域を平面視したときの小径貫通電極及び大径貫通電極の配置を説明する要部平面図である。
B1,B2 バリアメタル膜
BM,BM1,BM1c,BM1d,BM2,BM3 バリアメタル膜
BP バリアメタル膜
CB 銅バンプ
CE 接続電極(プラグ)
CL 接着層
CN 接続孔
CP1,CP2 銅めっき膜
CS 銅シート層
GE ゲート電極
GH ガラス支持体
GI ゲート絶縁膜
I1,I2 絶縁膜
IF1,IF1c,IF1d 第1絶縁膜
IF2 第2絶縁膜
IF3 第3絶縁膜
IN 窒化シリコン膜
IO 酸化シリコン膜
IR 分離部
IL 絶縁膜
ILD,ILD1,ILD2,ILD3 層間絶縁膜
KOZ キープ・アウト・ゾーン
M1,M2,M6 配線
MC,MCd 接続パッド
PW p型ウェル
RB 裏面バンプ
RS 封止樹脂
S1 主面(表面、第1主面)
S2 裏面(第2主面)
SB 外部端子(はんだボール)
SC 半導体チップ(半導体装置)
SD n型半導体領域
SIF ストッパ絶縁膜
SL サイドウォール
SW 半導体基板
TA 配線形成用の溝
TB 接続孔
TE,TEa,TEb,TEc 貫通電極
TE1,TE1a,TE1b,TE1c,TE1d 小径貫通電極(第1貫通電極)
TE2,TE2a,TE2b 大径貫通電極(第2貫通電極)
TE3 接続電極
TRa 配線形成用の溝
TRb 接続パッド形成用の溝
VI ビア(貫通穴、接続孔、開口部)
VI1,VI1c 小径ビア(貫通穴、接続孔、開口部;第1ビア)
VI2 大径ビア(貫通穴、接続孔、開口部;第2ビア)
VO 開口部
Claims (14)
- 半導体基板の第1主面から、前記第1主面と反対側の第2主面へ貫通する複数の貫通電極が形成された第1領域と、
前記半導体基板の前記第1主面に複数の半導体素子が形成された第2領域と、
を有する半導体装置であって、
前記複数の貫通電極の全部または一部の貫通電極は、
前記半導体基板の前記第1主面側に形成され、第1径を有する第1貫通電極と、
前記半導体基板の前記第2主面側に形成され、前記第1径よりも大きい第2径を有する第2貫通電極と、から構成され、
平面視において前記第1貫通電極は前記第2貫通電極の内側に位置し、平面視において前記第1貫通電極の中心位置は前記第2貫通電極の中心位置から離れている。 - 請求項1記載の半導体装置において、
前記複数の貫通電極の全部または一部の貫通電極は、1個の前記第2貫通電極と、複数個の前記第1貫通電極とから構成されている。 - 請求項1記載の半導体装置において、さらに、
前記半導体基板の前記第1主面上に、前記複数の半導体素子を覆うように形成された層間絶縁膜と、
前記第1領域の前記層間絶縁膜上に形成された接続パッドまたは配線と、
を有し、
前記第1貫通電極は、前記層間絶縁膜の上面から下面へ貫通する部分を有し、
前記第1貫通電極の一端は、前記接続パッドまたは前記配線と接続し、
前記第1貫通電極の前記一端と反対側の他端は、前記第2貫通電極と接続している。 - 請求項1記載の半導体装置において、さらに、
前記半導体基板の前記第1主面上に、前記複数の半導体素子を覆うように形成された層間絶縁膜と、
前記第1領域の前記層間絶縁膜を上面から下面へ貫通する接続電極と、
を有し、
前記第1貫通電極の一端は、前記接続電極と接続し、
前記第1貫通電極の前記一端と反対側の他端は、前記第2貫通電極と接続している。 - 請求項1記載の半導体装置において、さらに、
前記半導体基板の前記第1主面上に、前記複数の半導体素子を覆うように形成された層間絶縁膜と、
前記第1領域の前記層間絶縁膜上に形成された接続パッドまたは第1配線と、
前記第2領域の前記層間絶縁膜上に形成された第2配線と、
を有し、
前記第1貫通電極は、前記層間絶縁膜の上面から下面へ貫通する部分を有し、
前記第1貫通電極と前記接続パッドまたは前記第1配線とは同一の金属導電体によって一体に形成されている。 - 請求項5記載の半導体装置において、
前記第1貫通電極及び前記接続パッドまたは前記第1貫通電極及び前記第1配線は前記金属導電体によって前記第1領域に形成され、前記第2配線は前記金属導電体によって前記第2領域に形成されている。 - 請求項1記載の半導体装置において、
平面視において、前記第1領域内の最も外側に配置された前記第1貫通電極の中心位置は、前記第1領域の外周から離れる方向に配置されている。 - 請求項1記載の半導体装置において、
前記半導体基板と前記第1貫通電極との間には、前記半導体基板側から第1絶縁膜及び第1バリアメタル膜が形成され、
前記半導体基板と前記第2貫通電極との間には、前記半導体基板側から前記第1絶縁膜とは異なる第2絶縁膜及び前記第1バリアメタル膜とは異なる第2バリアメタル膜が形成されている。 - 請求項1記載の半導体装置において、
前記第1貫通電極と前記第2貫通電極との間には、バリアメタル膜が形成されている。 - 請求項1記載の半導体装置において、
前記第1領域において、複数の前記第2貫通電極は同一ピッチで配置されている。 - 以下の工程を含む半導体装置の製造方法:
(a)第1厚さを有する半導体基板の第1主面に、第1口径を有する第1ビアを形成する工程;
(b)前記第1ビアの底面及び側面に第1絶縁膜を形成した後、前記第1ビアの内部に第1バリアメタル膜を介して第1貫通電極を形成する工程;
(c)前記工程(b)の後、前記半導体基板を前記第1主面と反対側の第2主面から加工して、前記半導体基板の前記第1厚さを前記第1厚さよりも薄い第2厚さとする工程;
(d)前記工程(c)の後、前記半導体基板の前記第2主面上に第3絶縁膜を形成する工程;
(e)前記工程(d)の後、前記第3絶縁膜及び前記半導体基板を順次加工して、前記半導体基板の前記第2主面に、前記第1口径よりも大きい第2口径を有する第2ビアを形成し、前記第2ビアの底面から前記第1絶縁膜及び前記第1バリアメタル膜に覆われた前記第1貫通電極の一部を突出させる工程;
(f)前記工程(e)の後、前記第2ビアの底面及び側面に第2絶縁膜を形成した後、前記第2ビアの底面から突出する前記第1貫通電極の一部を覆う前記第2絶縁膜及び前記第1絶縁膜を除去して、前記第2ビアの底面から、前記第1貫通電極を覆う前記第1バリアメタル膜を露出させる工程;
(g)前記工程(f)の後、前記第2ビアの内部に第2バリアメタル膜を介して第2貫通電極を形成する工程、
ここで、平面視において前記第1貫通電極は前記第2貫通電極の内側に位置し、平面視において前記第1貫通電極の中心位置は前記第2貫通電極の中心位置から離れている。 - 請求項11記載の半導体装置の製造方法において、
前記工程(a)の前に、さらに、
(h)前記半導体基板の前記第1主面上に、層間絶縁膜を形成する工程、
を有し、
前記工程(a)では、前記層間絶縁膜及び前記半導体基板の前記第1主面に、前記第1口径を有する前記第1ビアが形成される。 - 請求項11記載の半導体装置の製造方法において、
前記第1絶縁膜及び前記第2絶縁膜は酸化シリコン膜であり、前記第3絶縁膜は前記半導体基板の前記第2主面側から窒化シリコン膜及び酸化シリコン膜を順次形成した積層膜である。 - 請求項11記載の半導体装置の製造方法において、
前記第3絶縁膜は、プラズマCVD法またはガス・クラスタ・イオンビーム法により形成される。
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JP2015216251A (ja) * | 2014-05-12 | 2015-12-03 | 国立大学法人東北大学 | 半導体装置およびその製造方法 |
US11908785B2 (en) | 2020-05-19 | 2024-02-20 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device and methods of manufacturing semiconductor device |
JP7462269B2 (ja) | 2020-05-19 | 2024-04-05 | パナソニックIpマネジメント株式会社 | 半導体装置及び半導体装置の製造方法 |
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KR20140029178A (ko) | 2014-03-10 |
TWI588962B (zh) | 2017-06-21 |
US20140061940A1 (en) | 2014-03-06 |
CN103681616A (zh) | 2014-03-26 |
CN103681616B (zh) | 2018-06-26 |
US9275935B2 (en) | 2016-03-01 |
JP5955706B2 (ja) | 2016-07-20 |
US9779992B2 (en) | 2017-10-03 |
US20160148841A1 (en) | 2016-05-26 |
TW201419483A (zh) | 2014-05-16 |
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