TWI512896B - 半導體晶粒及在基板穿孔上形成內連線結構的方法 - Google Patents
半導體晶粒及在基板穿孔上形成內連線結構的方法 Download PDFInfo
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Description
本發明係有關於一種半導體晶粒,且特別是有關於一種可減少短路的半導體晶粒。
隨著半導體科技的持續演進,半導體晶片/晶粒的尺寸愈發縮小。而同時,亦整合了更多的功能到半導體晶粒之中。因此,越來越多的輸出/輸入墊要放進半導體晶粒之越來越小的區域中。因此,半導體晶粒的封裝變得愈發重要、愈發具有挑戰性。
本發明提供一種半導體晶粒,包括:一基板穿孔形成於一半導體晶粒之一基板中;以及一插槽金屬墊形成於前述基板穿孔之正上方,其中前述插槽金屬墊具有一上表面,前述上表面之表面積大於前述基板穿孔之一上表面之表面積,其中前述插槽金屬墊在一第一方向具有複數個金屬柱,以及其中於前述複數個金屬柱間的插槽填入一介電材料以形成複數個介電柱。
本發明亦提供一種半導體晶粒,包括:一基板穿孔形成於一半導體晶粒之一基板中;以及一金屬插塞墊形成於
前述基板穿孔之正上方,其中前述插槽金屬墊具有一上表面,前述上表面之表面積大於前述基板穿孔之一上表面之表面積,其中前述插槽金屬墊在一第一方向具有複數個金屬柱,以及其中於前述複數個金屬柱間的插塞填入一介電材料以形成複數個介電柱,其中位於前述插塞金屬墊邊緣的前述複數個金屬柱之一第一金屬柱具有寬於遠離前述插塞金屬墊邊緣的前述複數個金屬柱之一第二金屬柱的寬度。
本發明更提供一種在基板穿孔上形成內連線結構的方法,包括:提供一具有基板穿孔的基板;形成一介電層在前述基板穿孔之上;形成複數個開口於前述介電層之中,其中前述複數個開口係連接的,其中在前述複數個開口間具有前述介電層之複數個介電結構;沈積一擴散阻障層以內襯前述複數個開口;沈積一導電層以填充前述複數個開口之空隙;平坦化前述導電層以及前述擴散阻障層以移除在複數個開口外的前述導電層以及前述擴散阻障層而形成一插槽金屬墊,其中前述平坦化步驟不會在靠近前述插槽金屬墊的中心區域造成明顯的碟狀效應。
100‧‧‧封裝體
120A
、120B
、130‧‧‧晶粒
125A
、125B
‧‧‧接合結構
131‧‧‧基板穿孔
132、150‧‧‧內連線結構
133‧‧‧接觸結構
135‧‧‧外部連結器
140‧‧‧基板
141‧‧‧金屬墊
142‧‧‧金屬層
141’、141”、141*、141^‧‧‧插槽金屬墊
143、144、153‧‧‧介電層
147、147A
、147B
‧‧‧金屬線
149E
、149M
、149C
‧‧‧金屬柱
143D
‧‧‧介電柱
143S
‧‧‧金屬橫條
146‧‧‧介層插塞
151、159‧‧‧導電層
152、158、162‧‧‧擴散阻障層
154、161‧‧‧蝕刻停止層
156‧‧‧平坦化停止層
157‧‧‧開口
190‧‧‧裝置結構
A‧‧‧表面積
W‧‧‧寬度
D‧‧‧直徑
L‧‧‧長度
第1圖為一截面示意圖,其顯示根據一些實施例中之封裝結構;第2A圖為一截面示意圖,其顯示根據一些實施例中之一靠近基板穿孔的區域;第2B圖為一俯視示意圖,其顯示根據一些實施例中之在
第2A圖之基板穿孔上的金屬墊;第3A圖為一截面示意圖,其顯示根據一些實施例中與第2A圖之類似區域並具有一插槽金屬墊;第3B圖為一俯視示意圖,其顯示根據一些實施例之在基板穿孔之上的插槽金屬墊;第4A-4C圖為一些實施例中之插槽金屬墊的俯視示意圖;第5A-5H圖為一系列製程步驟,顯示根據一些實施例形成插槽金屬墊於一基板穿孔之上的製程步驟,以及根據一些實施例之在插槽金屬墊上的內連線結構。
以下說明本發明實施例之製作與使用。然而,可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明,並非用以侷限本發明的範圍。
自從積體電路發明後,半導體工業由於各種電子元件(例如,電晶體、二極體、電阻器、電容器等等)在整合密度上持續進步的關係,正經歷持續而快速的成長。大多數情況下,整合密度上的進步來自於重複縮減最小特徵尺寸,使得更多元件可整合到一特定區域內。
這些整合上的進步在本質上是二維,而那些佔有空間的積體元件基本上是放置在半導體晶圓表面。雖然在微影技術上顯著的進步大大改進了二維積體電路的形成,然二維密度有其物理侷限性。這些限制之其一為這些元件的最小製作尺寸。以及,當要放越多裝置到一個晶片中時,即需要越複雜的
設計。
三維積體電路相應而生以解除上述限制。在一些三維積體電路的形成製程中,將形成二個或以上的晶圓,並各自包括一個積體電路。接著,將這些晶圓接合並將其裝置對準。基板穿孔(through substrate vias,TSV),亦稱為矽穿孔或晶圓穿孔,越來越常用於實現三維積體電路。基板穿孔經常用於三維積體電路以及晶粒堆疊以提供電性連接,及/或協助散熱。而在三維積體電路及/或晶粒堆疊中形成基板穿孔仍存有挑戰。
第1圖為一截面示意圖,其為根據一些實施例中的封裝結構。封裝結構100包括兩個晶粒120A
及120B
,接合至另一個晶粒130。在一些實施例中,晶粒120A
及120B
各自包括一半導體基板,用於半導體積體電路製程,以及此積體電路可形成於其中或其上。半導體基板係包括任何半導體材料的建造,其包括,但不限於,主體矽(bulk silicon),半導體晶圓、絕緣體上矽(silicon on insulator,SOI)基板、或SiGe基板。亦可應用其他半導體材料,包括第三、四、及五族元素。半導體基板可進一步包括複數個隔離特徵(未繪出),例如淺溝槽隔離特徵(shallow trench isolation,STI)或局部氧化矽特徵(local oxidation of silicon,LOCOS)。隔離特徵可定義並隔離各個微電子元件。各個微電子元件(未繪出)可例如形成於半導體基板中,包括電晶體(如金氧半場效電晶體(MOSFET)、互補式金氧半電晶體(CMOS)、雙極性接面電晶體(BJT)、高電壓電晶體、高頻率電晶體、p型通道場效電晶體、及/或n型通道場效電晶
體等等);電阻器;二極體;電容器;電感器;熔斷器;及其他合適的元件。
形成各種微電子元件需施行多種不同製程,包括:沈積、蝕刻、植入、光微影、退火、及/或其他合宜的製程。互連各個微電子元件以形成積體電路裝置,例如邏輯裝置、儲存裝置(例如SRAM)、射頻裝置(radio frequency device)、輸入/輸出(I/O)裝置、系統單晶片裝置(system-on-chip,SoC)、前述之組合、或其他合宜之裝置種類。
晶粒130包括多個基板穿孔131。晶粒130可包括各式被動以及主動微電子裝置(未繪出),例如電阻器、電容器、電感器、二極體、金氧半場效電晶體、互補式金氧半電晶體、雙極接面電晶體、射頻橫向擴散金氧半(laterally diffused MOS)電晶體、高功率金氧半場效電晶體(high power MOS transistor)、鰭式場效電晶體、其他類型的電晶體、及/或任何前述之組合。晶粒130為一中介片,其提供給三維封裝系統電性連接及/或散熱的功能。具有主動裝置的中介片可被稱為主動中介片。不具有主動裝置的中介片則可被稱為被動中介片。
在第1圖中的晶粒130亦包括內連線結構132。內連線結構132促進具有基板穿孔131的晶粒120A
及120B
與在晶粒130上的被動及/或主動裝置(如果有的話)的電性連接。內連線結構132包括多個導電結構及一層或一層以上的介電層,其保護並隔離導電結構。晶粒120A
及120B
藉由接合結構125A
及125B
連結內連線結構132以連接基板穿孔131。在晶粒130的內連線結構132之異側具有一接觸結構133以連接外部連結器135。
第2A圖為一剖面圖,其顯示靠近晶粒130中基板141上之基板穿孔131的一區域。第2A圖顯示一已形成於第一基板100上的裝置結構190。此裝置結構可以是前述被動或主動微電子裝置之一。
一金屬層142形成於基板穿孔131之上,以及一金屬墊141形成於基板穿孔131上方。在一些實施例中,金屬墊141較基板穿孔131寬以確保其完全覆蓋於基板穿孔131之上表面。在不限制本發明範圍之前提下,較寬的金屬墊被認為能夠減少基板穿孔131發生爆出缺陷(pop-up defect)的可能。第2B圖顯示金屬墊141在基板穿孔131之上的俯視圖實施例。第2B圖顯示基板穿孔131具有一直徑為D的圓形上表面。金屬墊141則係為一寬度為W的方形。W大於D。而(W-D)/2大於對準誤差T(alignment tolerance)。在一些實施例中,D約介於3-30μ
m。在一些實施例中W約介於10-50μ
m。在一些實施例中,T介於0-10μ
m。金屬線(未繪出)與金屬層142位於同層以使金屬層142連結至金屬墊141進而允許基板穿孔131藉由金屬墊141電性連接至各種裝置及結構。
為形成金屬層142,如用以形成金屬墊141的開口會先形成於介電層143中。接著以導電材料填入開口,其亦可包括一阻障或黏著層以及一主要為導電材料的金屬層142。阻障或黏著層以及主要導電材料不僅是沈積於開口中,其亦沈積於介電層143之表面上。可使用如化學機械平坦化等平坦化製程移除在開口外之多餘材料。由於金屬墊141相對較寬的寬度,化學機械平坦化會造成碟狀效應(dishing effect),其亦即
是使金屬墊141的表面中心凹陷而低於金屬墊141的邊緣,如第2A中之區域M。
金屬墊141的凹陷可能影響其上方層之平坦化。在化學機械平坦化製程完成後,一介電層144沈積於基板140表面之上。靠近金屬墊141中心的凹陷則移轉至其上的介電層144,如第2A圖中區域N之實施例所示。在介電層144沈積後,圖案化基板140以形成介層插塞146以及金屬線147之開口。在一些實施例中,在前述開口中填入如前述金屬層142之導電材料145。接著移除在金屬線147外之多餘導電材料。由於介電層144中的凹陷,一些金屬脈線(metal stringers)可能滯留於表面。此些金屬脈線可能造成不必要的金屬線間短路。如第2A圖所示,在區域N之金屬脈線可能造成兩條相鄰金屬線147A
及147B
的短路。
介層插塞、多條金屬線147以及介電層144在插槽金屬墊141形成形成一內連線結構150。亦可形成額外的內連線結構(未繪出)於內連線結構150之上。可形成接合結構於前述內連線結構之上,包括內連線結構150,以連結至晶粒120A
以及120B
。在一些實施例中,內連線結構150為第1圖中內連線結構132之一部分。在一些實施例中,內連線結構150稱為重分佈結構,幫助穿過晶粒130的連接重分佈以促進對外部接觸點的連接。在一些實施例中,金屬線147包括金屬墊(未繪出)以形成凸塊結構以連接外部連結器。凸塊結構以及外部連結器形成前述之接合結構125A
以及125B
。
重分佈結構、接合結構及其形成方法皆記載於
2012年3月12日提出的美國申請專利第13/427753號之”Bump Structures for Multi-chip Packaging”以及2011年12月28日提出的美國申請專利第13/338820號之”Packaged Semiconductor Device and Method of Packaging the Semiconductor Device”。於此併入作為參考之用。
第3A圖所示為具有插槽金屬墊141’(slotted metal pad)而近似於第2A圖中區域之截面圖。插槽金屬墊141’具有填入介電層143之材料的開口而形成鑲嵌在插槽金屬墊141’中之介電柱149D
。可利用此些作為研磨中止點並減少用以形成金屬墊141所造成之碟狀效應。第3A圖顯示出藉由使用介電柱,將插槽金屬墊141’之碟狀縮減至無或幾乎不存在。因此在金屬線147A
’及147B
’間之金屬脈線148亦完全移除,並且在金屬線147A
’及147B
’間沒有產生短路的風險。
第3B圖所示為在基板穿孔131之上的插槽金屬墊141’之俯視圖。插槽金屬墊141’具有一寬度W並為一正方形金屬墊。基板穿孔131之寬度為D。W與D之一些範圍的實施例已如前述。插槽金屬墊141’的金屬表面積為AM
而介電表面積為AD
。插槽金屬墊141’的總表面積為AM
+AD
,即為A。而金屬比例AM
/A不宜太低,以確保插槽金屬墊141’與基板穿孔131之間具有足夠接觸並確保插槽金屬墊141’之電阻不會太高而影響裝置性能。在另一方面,亦須限制金屬比例AM
/A以避免碟狀效應。在一些實施例中,金屬比例AM
/A介於50%~90%之間。
在一些實施例中,第3B圖之插槽金屬墊141’具有一寬度W並為一正方形金屬墊,而基板穿孔131之寬度為D。基
板穿孔之上表面積為AT
,其等於D2
π/4。基板穿孔之上表面積對插槽金屬墊之總表面積A(即W2
)之比例A/AT
不宜過低,以確保在能夠對應各式對準方式的前提下.插槽金屬墊141’完整覆蓋於基板穿孔。在另一方面,亦須限制基板穿孔對總表面積之比例A/AT
以避免插槽金屬墊141’佔用晶粒過多的區域。在一些實施例中,A/AT
比例約介於1.2(T=0)-3.5之間。
在一些實施例中,第3B圖顯示插槽金屬墊141’的金屬柱149E
較金屬柱149M
為寬。金屬柱149E
位在插槽金屬墊141’之邊緣並在介電層143區域旁。因此,相較金屬柱149M
間之金屬柱149E
而言,金屬柱149E
受到碟狀效應影響的風險較低。而連結至金屬柱149M
及金屬柱149E
的金屬柱149C
亦位於插槽金屬墊141’的邊緣。然,金屬柱149C
由於連結至金屬柱149M
,其受到碟狀效應的影響大於金屬柱149E
而小於金屬柱149M
。遠離插槽金屬墊141’邊緣之金屬柱149M
受碟狀效應的影響度為金屬柱149M
的寬度WM
對金屬柱149M
間介電柱143D
的寬度WD
比例WM
/WD
。WM
/WD
比例越高,插槽金屬墊141’越易於在化學機械平坦化製程中受碟狀效應影響。在一些實施例中,WM
/WD
比例約介於0.5-1.2之間。WM
/WD
比例受到化學機械平坦化製程及介電層143所使用的材料所影響。製程條件,包括所使用之拋光墊以及研磨漿,以及介電層143所使用的材料電阻皆可能影響插槽金屬墊141’可使用之WM
/WD
比例範圍。如前述,插槽金屬墊141’之金屬表面積AM
相對於總表面積A比例AM
/A不宜太低,以防止插槽金屬墊之電阻過高。因此,與AM
/A比例相關的WM
/WD
比例不可過低。在一些實施例中,WM
/WD
約介於0.8-1.0之間。
在一些實施例中,插槽金屬墊141’的總寬度W約介於11-34μm之間。在一些實施例中,金屬柱149E
的寬度WA
約介於0.4-4μm之間。在一些實施例中,WM
約大於0.4μm。在一些實施例中,WC
約介於0.4-4μm之間。在一些實施例中,WD
約大於0.4μm。WA
、WM
、WC
及WD
之下限係根據特定技術節點所設定,其根據不同技術節點可能較大或較小。
前述之插槽金屬墊141’僅為實施例之一,亦可應用其他插槽金屬墊的結構。第4A圖所示為一插槽金屬墊141”之俯視圖。插槽金屬墊141”在靠近其中心處具有較窄寬度WM”
的金屬柱。插槽金屬墊141”之中心區域相較於邊緣具有較高的風險發生碟狀效應。可將金屬柱寬度WM”
對介電柱寬度WD
之比例維持較低於靠近邊緣者的比例以求減少碟狀效應。
第4B圖所示為一插槽金屬墊141*之俯視圖。插槽金屬墊141*在靠近其中心處具有較窄寬度WM*
的金屬柱及較寬寬度的介電柱(寬度WD*
)。插槽金屬墊141*之中心區域相較於邊緣具有較高的風險發生碟狀效應。藉由在插槽金屬墊141*中心區域中較窄的金屬柱以及較寬的介電柱,可降低碟狀效應的風險並且可讓金屬柱更寬。在一些實施例中,WM*
/WD*
比例約介於0.5-0.95。在一些實施例中,介電柱的寬度WD*
補償了較窄金屬柱WB*
。如第4B圖所示,靠近插槽金屬墊141*中心區域之較窄金屬柱具有一長度LC
。在一些實施例中,LC
/W的比例約介於0.2-0.8。
除了前述圖案之外,插槽金屬墊的其他圖案亦可
行。第4C圖所示為一插槽金屬墊141^之俯視圖。第4C圖所示為靠近插槽金屬墊141^之各對相鄰的金屬柱143^藉由一些金屬條149S
連接在一起。然而靠近插槽金屬墊141^中心區域的相鄰金屬柱並未藉由金屬橫條149S
連接。連接之金屬橫條149S
可降低插槽金屬墊141^的電阻。只要是可以減少碟狀效應的任何其他圖案設計皆可行。
第5A-5H圖所示為一系列形成插槽金屬墊141’於基板穿孔131之上並形成一內連線結構150於插槽金屬墊141’之上的連續製程步驟之截面圖。第5A圖所示為一基板140,其提供一基板穿孔131。基板穿孔131包括一導電層151。在一些實施例中,導電層151係以銅或銅合金製成。導電層151周圍環繞一層擴散阻障層152以防止銅擴散進基板140中,進而影響裝置性能。在一些實施例中,擴散阻障層係由TaN所製成。在一些實施例中,擴散阻障層之厚度約介於0.5-1.5μm之間。而一介電層153環繞於擴散阻障層152,以將基板穿孔131與基板140隔絕。在一些實施例中,介電層153係由SiO2
所製成。在一些實施例中,介電層153之厚度約介於0.5-1.5μm之間。一裝置結構190形成於基板140之上。
第5B圖所示為蝕刻中止層154、介電層143、以及平坦化中止層156依序沈積於第5A圖中之基板上的一些實施例。在一些實施例中,蝕刻中止層154為SiN所形成,其厚度約介於40-60nm之間。介電層143可利用任何可行的材料,例如SiO2、低介電常數(low-k)材料。在一些實施例中,低介電常數材料的k值小於2.5。在一些實施例中,介電層143之厚度約介
於0.8-1μm。在一些實施例中,平坦化中止層156為SiON所形成,其厚度約介於50-70nm之間。
在各層蝕刻中止層154、介電層143、平坦化中止層156依序沈積後,為了後續將形成之插槽金屬墊,圖案化前述各層以形成開口157,如第5C圖所示之實施例。圖案化製程涉及光微影製程及蝕刻製程。蝕刻中止層154用於控制蝕刻製程的結束點。在開口157中填入一或多種導電材料以形成插槽金屬墊141’。在一些實施例中,先沈積一擴散阻障層158以作為開口157之內襯,如第5D圖所示。在一些實施例中,擴散阻障層係以TaN所形成,其厚度約介於2-10nm。根據一些實施例,沈積一晶種薄層(未繪出)於擴散阻障層158之上,其係作為電鍍用以填入開口157的導電層的功能。之後,沈積導電層159以填入開口157。在一些實施例中,導電層係以銅或銅合金所形成。可藉由電鍍製程形成導電層,並在一些實施例中,晶種層為銅晶種層。由於晶種層與導電層係使用同一種材料,兩者在之後將融合為一。因此,在第5D圖中並未顯示晶種層。在一些實施例中,晶種薄層之厚度約介於0.1-0.2μm之間。並沈積足夠厚度之導電159以填入開口157。
在導電層之沈積後,使用一平坦化製程以移除在開口157外的多餘導電層159及擴散阻障層158。在一些實施例中,平坦化製程為化學平坦化(CMP)製程。平坦化中止層156係作為研磨的中止。而平坦化中止層156所餘下部分亦在平坦化製程後移除,例如藉由蝕刻製程。第5E圖所示為在平坦化製程完成後之基板140的實施例。插槽金屬墊141’已形成。藉由
在金屬柱149E
及149M
之間的介電柱149D
,基板140並無明顯的碟狀效應。
在平坦化製程後,基板140進行額外的製程步驟以形成內連線結構150。一蝕刻中止層161沈積於插槽金屬墊141’之上,如第5F圖所示之實施例。其後,介電層144形成於蝕刻中止層161之上。在一些實施例中,蝕刻中止層161係由SiC所形成,其厚度約介於50-60nm之間。介電層144可利用任何可行的材料,例如SiO2
、低介電常數(low-k)材料。在一些實施例中,低介電常數材料的k值小於3.5。在一些實施例中,低介電常數材料的k值小於2.5。在一些實施例中,介電層144之厚度約介於0.6-0.7μm。
在蝕刻中止層161、介電層144沈積後,圖案化並蝕刻基板140以形成介層插塞及金屬線的開口。接著沈積一擴散阻障層162至介層插塞及金屬線的開口中,並填入導電層147,如第5G圖所示之實施例。在一些實施例中,形成擴散阻障層162以及導電層147之材料及方法分別近似於擴散阻障層158及導電層159。其後,移除在金屬線開口外多餘的導電層147及擴散阻障層162並形成內連線結構於插槽金屬墊之上,如第5H圖所示之實施例。
此處提供多個形成插槽金屬墊於基板穿孔上的機制。在插槽金屬墊中的介電結構減少在插槽金屬墊平坦化製程中的碟狀效應。因此,因碟狀效應而在金屬層上部造成的金屬脈線可大大減少。
在一些實施例中,提供一種半導體晶粒。半導體
晶粒包括一基板穿孔形成於一半導體晶粒之一基板,以及一插槽金屬墊形成於前述基板穿孔之正上方。前述插槽金屬墊具有一上表面,前述上表面之表面積大於前述基板穿孔之一上表面之表面積,以及前述插槽金屬墊在一第一方向具有複數個金屬柱。於前述複數個金屬柱間的插塞填入一介電材料以形成複數個介電柱。
在一些實施例中提供一種半導體晶粒。半導體晶粒包括一基板穿孔形成於一半導體晶粒之一基板中。半導體晶粒亦包括一金屬插塞墊形成於前述基板穿孔之正上方,並且前述插槽金屬墊具有一上表面,前述上表面之表面積大於前述基板穿孔之一上表面之表面積。前述插槽金屬墊在一第一方向具有複數個金屬柱,以及其中於前述複數個金屬柱間的插塞填入一介電材料以形成複數個介電柱。位於前述插塞金屬墊邊緣的前述複數個金屬柱之一第一金屬柱具有寬於遠離前述插塞金屬墊邊緣的前述複數個金屬柱之一第二金屬柱的寬度。
更在另一些實施例中,提供一種在基板穿孔上形成內連線結構的方法。此方法包括提供一具有基板穿孔的基板,並形成一介電層在前述基板穿孔之上。此方法亦包括形成複數個開口於前述介電層之中,且前述複數個開口係連接的。在前述複數個開口間具有前述介電層之複數個介電結構。此方法另包括沈積一擴散阻障層以內襯前述複數個開口,並沈積一導電層以填充前述複數個開口之空隙。此外,此方法包括平坦化前述導電層以及前述擴散阻障層以移除在複數個開口外的前述導電層以及前述擴散阻障層而形成一插塞金屬墊。前述平
坦化步驟不會在靠近前述插塞金屬墊的中心區域造成明顯的碟狀效應。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作更動、替代與潤飾。舉例來說,任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。再者,本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟,任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟,只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此,本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外,每一申請專利範圍構成個別的實施例,且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
140‧‧‧基板
150‧‧‧內連線結構
141‧‧‧金屬墊
143、144‧‧‧介電層
146‧‧‧介層插塞
147、147A
、147B
‧‧‧金屬線
149E
、149M
‧‧‧金屬柱
190‧‧‧裝置結構
154、161‧‧‧蝕刻停止層
162‧‧‧擴散阻障層
Claims (10)
- 一種半導體晶粒,包括:一基板穿孔形成於一半導體晶粒之一基板中;以及一插槽金屬墊形成於該基板穿孔之正上方,其中該插槽金屬墊具有一上表面,該上表面之表面積大於該基板穿孔之一上表面之表面積,其中該插槽金屬墊在一第一方向具有複數個金屬柱,以及其中於該複數個金屬柱間的插槽填入一介電材料以形成複數個介電柱。
- 如申請專利範圍第1項所述之半導體晶粒,其中位於該插槽金屬墊邊緣的該複數個金屬柱之一第一金屬柱具有寬於遠離該插槽金屬墊邊緣的該複數個金屬柱之一第二金屬柱的寬度。
- 如申請專利範圍第1項所述之半導體晶粒,其中具有一垂直於該第一方向之第二方向之一第三金屬柱連接至該複數個金屬柱。
- 如申請專利範圍第2項所述之半導體晶粒,其中該第二金屬柱具有一中段區域及一邊緣區域,該邊緣區域較該中段區域靠近該插槽金屬墊之邊緣,該中段區域在垂直於該第一方向之一方向較該邊緣區域窄。
- 如申請專利範圍第1項所述之半導體晶粒,其中該插槽金屬墊面向該基板穿孔之金屬表面對該插槽金屬墊總表面之表面積比係介於50-90%,以及該插槽金屬墊面向該基板穿孔之總表面對接觸該插槽金屬墊之基板穿孔之表面的表面積比係介於1.2-3.5。
- 如申請專利範圍第2項所述之半導體晶粒,其中靠近該插槽金屬墊中心區域之一第四金屬柱較該第二金屬柱窄。
- 如申請專利範圍第1項所述之半導體晶粒,更包括連結該複數個金屬柱中之相鄰金屬柱的複數個額外金屬條,其中該額外金屬條非位於該插槽金屬墊之邊緣,以及其中該額外金屬條非位於該插槽金屬墊之中心區域。
- 一種在基板穿孔上形成內連線結構的方法,包括:提供一具有基板穿孔的基板;形成一介電層在該基板穿孔之上;形成複數個開口於該介電層之中,其中該複數個開口係連接的,其中在該複數個開口間具有該介電層之複數個介電結構;沈積一擴散阻障層以內襯該複數個開口;沈積一導電層以填充該複數個開口之空隙;以及平坦化該導電層以及該擴散阻障層以移除在複數個開口外的該導電層以及該擴散阻障層而形成一插槽金屬墊,其中該平坦化步驟不會在靠近該插槽金屬墊的中心區域造成明顯的碟狀效應。
- 如申請專利範圍第8項所述之在基板穿孔上形成內連線結構的方法,其中該插槽金屬墊具有一大於該基板穿孔上表面之上表面,其中該插槽金屬墊在第一方向具有複數個金屬柱,以及其中在複數個金屬柱間之插塞中填入介電材料以形成複數個介電柱;以及更包括形成一內連線結構於該插槽金屬墊之正上方。
- 如申請專利範圍第8項所述之在基板穿孔上形成內連線結構的方法,其中該插槽金屬墊面向該基板穿孔之金屬表面對該插槽金屬墊總表面之表面積比係介於50-90%。
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