TW202109790A - 封裝 - Google Patents

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Publication number
TW202109790A
TW202109790A TW109113393A TW109113393A TW202109790A TW 202109790 A TW202109790 A TW 202109790A TW 109113393 A TW109113393 A TW 109113393A TW 109113393 A TW109113393 A TW 109113393A TW 202109790 A TW202109790 A TW 202109790A
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Taiwan
Prior art keywords
die
bonding
layer
tiv
pad
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TW109113393A
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English (en)
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陳明發
葉松峯
洪建瑋
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台灣積體電路製造股份有限公司
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Publication of TW202109790A publication Critical patent/TW202109790A/zh

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Abstract

一種封裝包括第一晶粒、第二晶粒、第一包封體、第一絕緣層穿孔（TIV）、第二包封體及第二TIV。第二晶粒堆疊在第一晶粒上。第一包封體在側向上包封第一晶粒。第一TIV位於第一晶粒旁。第一TIV穿透過第一包封體且是電性浮動的。第二包封體在側向上包封第二晶粒。第二TIV位於第二晶粒旁。第二TIV穿透過第二包封體且是電性浮動的。第二TIV實質上與第一TIV對齊。

Description

封裝
本發明實施例是有關於一種封裝，且特別是有關於一種具有電性浮動的絕緣層穿孔的封裝。
各種電子裝置（例如，手機及其他移動電子設備）中所使用的半導體裝置及積體電路通常是在單個半導體晶圓（semiconductor wafer）上製造。晶圓的晶粒可以晶圓級（wafer level）來與其他半導體裝置或晶粒一起進行處理及封裝，且已針對晶圓級封裝（wafer level packaging）開發了各種技術及應用。多個半導體裝置的集成已成為此領域中的挑戰。
一種封裝包括第一晶粒、第二晶粒、第一包封體、第一絕緣層穿孔（through insulating via；TIV）、第二包封體、及第二TIV。所述第二晶粒堆疊在所述第一晶粒上。所述第一包封體在側向上包封所述第一晶粒。所述第一TIV位於所述第一晶粒旁。所述第一TIV穿透過所述第一包封體且是電性浮動的。所述第二包封體在側向上包封所述第二晶粒。所述第二TIV位於所述第二晶粒旁。所述第二TIV穿透過所述第二包封體且是電性浮動的。所述第二TIV實質上與所述第一TIV對齊。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及佈置的具體實例以簡化本公開。當然，這些僅為實例而非旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵從而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本公開可能在各種實例中重複使用參考編號和/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身指示所論述的各種實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在...之下（beneath）”、“在...下方（below）”、“下部的（lower）”、“在...上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括器件在使用或操作中的不同取向。裝置可具有其他取向（旋轉90度或處於其他取向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
本公開也可包括其他特徵及製程。舉例來說，可包括測試結構，以説明對三維（three-dimensional；3D）封裝或三維積體電路（three-dimensional integrated circuit；3DIC）裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或在基板上形成的測試墊，以使得能夠對3D封裝或3DIC進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與包括對已知良好晶粒（known good die）進行中間驗證的測試方法一起使用，以提高良率並降低成本。
圖1A到圖1P是根據本公開的一些實施例的封裝10的製造流程的示意性剖視圖。參考圖1A，提供半導體載板110。在一些實施例中，半導體載板110可由以下半導體製成：合適的元素半導體，例如晶體矽、金剛石或鍺；合適的化合物半導體，例如砷化鎵、碳化矽、砷化銦或磷化銦；或者合適的合金半導體，例如碳化矽鍺、磷化鎵砷或磷化鎵銦。在一些實施例中，半導體載板110不含主動元件及被動元件。在一些實施例中，半導體載板110具有多個晶粒區DR及多個切割道區SR。每一切割道區SR位於兩個相鄰的晶粒區DR之間。為了簡明起見，在圖1A中示出了兩個晶粒區DR及一個切割道區SR。
在一些實施例中，多個接觸通孔112嵌置在半導體載板110中。在一些實施例中，接觸通孔112由金屬製成。舉例來說，接觸通孔112可包含鋁、鈦、銅、鎳、鎢及/或其合金。如圖1A所示，接觸通孔112位於晶粒區DR中。在一些實施例中，接觸通孔112的頂表面與半導體載板110的頂表面共面。在一些實施例中，接觸通孔112被電性接地。舉例來說，接觸通孔112電性連接到地電壓（ground voltage）。在一些實施例中，接觸通孔112直接接觸半導體載板110。舉例來說，接觸通孔112的側壁及底表面直接接觸半導體載板110。
如圖1A所示，對位層120及介電層130依序地形成在半導體載板110上。在一些實施例中，對位層120包括介電層122及嵌置在介電層122中的多個對位標記124。舉例來說，介電層122環繞對位標記124。在一些實施例中，介電層122可通過合適的製作技術（例如氣相沉積、旋轉塗布（spin coating）、原子層沉積（atomic layer deposition；ALD）、熱氧化、一些其他合適的沉積或生長製程、或其組合）形成。氣相沉積可包括例如化學氣相沉積（chemical vapor deposition；CVD）、物理氣相沉積（physical vapor deposition；PVD）、一些其他合適的氣相沉積製程或其組合。在一些實施例中，介電層122的材料可為聚醯亞胺、聚苯並噁唑（polybenzoxazole；PBO）、苯並環丁烯（benzocyclobutene；BCB）、氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、未摻雜的矽酸鹽玻璃（undoped silicate glass；USG）、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽酸鹽玻璃（borosilicate glass；BSG）、硼摻雜的磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG）、其組合等。在一些實施例中，對位標記124可為圖案化銅層（patterned copper layer）或其他合適的圖案化金屬層。在一些實施例中，對位標記124可通過電鍍或沉積形成。應注意的是，對位標記124的形狀及數目在本公開中不受限制，且可基於需求及/或設計佈局來加以修改。在一些實施例中，介電層122的頂表面實質上與對位標記124的頂表面齊平。如圖1A所示，對位標記124直接接觸接觸通孔112。在一些實施例中，對位標記124電性連接到接觸通孔112。舉例來說，對位標記124通過接觸通孔112被電性接地。
在一些實施例中，介電層130是具有連續均勻表面的平滑層，且上覆在介電層122及對位標記124上。在一些實施例中，介電層130的材料可包括氮氧化矽（SiON）、氧化矽、氮化矽等。在一些實施例中，介電層130可通過沉積等形成。在一些實施例中，介電層130具有實質上均一且均勻的厚度。
參考圖1B，在半導體載板110上放置多個晶粒200。在一些實施例中，每一晶粒200包括半導體基板210、內連結構220、鈍化層230、導電墊240及多個半導體穿孔（through semiconductor via；TSV）250。在一些實施例中，內連結構220設置在半導體基板210上。半導體基板210可由以下半導體製成：合適的元素半導體，例如晶體矽、金剛石或鍺；合適的化合物半導體，例如砷化鎵、碳化矽、砷化銦或磷化銦；或者合適的合金半導體，例如碳化矽鍺、磷化鎵砷或磷化鎵銦。在一些實施例中，半導體基板210可包括形成在其中的主動元件（例如，電晶體等）及/或被動元件（例如，電阻器、電容器、電感器等）。
在一些實施例中，內連結構220包括介電間層（inter-dielectric layer）222及嵌置在介電間層222中的多個導電圖案224。在一些實施例中，內連結構220的導電圖案224電性連接到嵌置在半導體基板210中的主動元件及/或被動組件。在一些實施例中，介電間層222的材料包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、BCB、PBO、其組合或其他合適的介電材料。介電間層222可通過合適的製作技術（例如旋轉塗布、疊層（lamination）、CVD等）形成。在一些實施例中，導電圖案224的材料包括鋁、鈦、銅、鎳、鎢及/或其合金。導電圖案224可通過例如電鍍、沉積及/或微影及蝕刻來形成。為了簡明起見，在圖1B中內連結構220被示出為具有一層介電間層222及一層導電圖案224。然而，本公開並不限於此。在一些替代性實施例中，介電間層222的層數及導電圖案224的層數可根據佈線要求來調整。舉例來說，可在內連結構220中存在多層介電間層222及多層導電圖案224，且導電圖案224與介電間層222可交替堆疊。
在一些實施例中，導電墊240設置在內連結構220上。在一些實施例中，導電墊240電性連接到內連結構220的導電圖案224。在一些實施例中，導電墊240用於與隨後形成或提供的其他元件（未繪示）或晶粒（未繪示）建立電性連接。在一些實施例中，導電墊240可為鋁墊、銅墊或其他合適的金屬墊。應注意的是，可基於需求來選擇導電墊240的數目及形狀。
在一些實施例中，鈍化層230形成在內連結構220上以密封導電墊240。在一些實施例中，鈍化層230的材料包括氧化物，例如氧化矽等。作為另外一種選擇，鈍化層230可包含聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、BCB、PBO或任何其他合適的聚合物系介電材料。鈍化層230例如可通過合適的製作技術（例如旋轉塗布、CVD、電漿增強化學氣相沉積（plasma enhanced chemical vapor deposition；PECVD）等）形成。在一些實施例中，TSV 250嵌置在半導體基板210中。在一些實施例中，TSV 250直接接觸導電圖案224，以實現與內連結構220的電性連接。
在一些實施例中，晶粒200能夠執行邏輯功能。舉例來說，晶粒200可為中央處理器（Central Process Unit；CPU）晶粒、圖形處理單元（Graphic Process Unit；GPU）晶粒、現場可程式設計閘陣列（Field-Programmable Gate Array；FPGA）等。
在一些實施例中，每一晶粒200具有主動表面200a及與主動表面200a相對的後表面200b。在一些實施例中，在放置晶粒200之前，在每一晶粒200的主動表面200a上形成接合層300。舉例來說，接合層300形成在晶粒200的鈍化層230上。在一些實施例中，接合層300是具有連續均勻表面的平滑層。在一些實施例中，接合層300的材料可包括氮氧化矽（SiON）、氧化矽、氮化矽等，且接合層300可通過沉積等形成。
在一些實施例中，上面形成有接合層300的晶粒200被拾取並放置（picked-and-placed）在介電層130上，使得接合層300通過熔融接合（fusion bonding）黏附到介電層130。熔融接合製程可包括親水性熔融接合製程（hydrophilic fusion bonding process），其中可用的工作溫度約大於或實質上等於約100℃，且可用的工作壓力約大於或實質上等於約1 kg/cm2 。在一些實施例中，熔融接合製程不涉及金屬對金屬接合。如圖1B所示，晶粒200以面朝下的方式接合到半導體載板110。也就是說，晶粒200的主動表面200a面向半導體載板110。在一些實施例中，晶粒200被放置在晶粒區DR中。舉例來說，晶粒200以陣列方式排列。
參考圖1C，在介電層130上形成包封體材料400’，以共形地覆蓋晶粒200。在一些實施例中，包封體材料400’包括模製化合物或聚合材料（例如聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、BCB、PBO、其組合或其他合適的聚合物系介電材料）。在一些替代性實施例中，包封體材料400’可包括氧化矽及/或氮化矽。在一些實施例中，包封體材料400’還包含填料（filler）。作為另外一種選擇，包封體材料400’可不含填料。在一些實施例中，包封體材料400’可通過模製製程（例如壓縮模製製程（compression molding process））、旋轉塗布製程、CVD製程、PECVD製程、ALD製程等形成。如圖1C所示，晶粒200並未被顯露出且被包封體材料400’良好地保護住。
參考圖1C及圖1D，對包封體材料400’進行薄化以形成包封體400。也就是說，對包封體材料400’進行薄化直到暴露出晶粒200的半導體基板210。如圖1D所示，介電層130夾置在對位層120與包封體400之間。在一些實施例中，在半導體基板210被顯露出之後，可進一步對半導體基板210及包封體400進行薄化以減小晶粒200的總厚度。在一些實施例中，可通過研磨製程（例如機械研磨製程（mechanical grinding process）、化學機械拋光（chemical mechanical polishing；CMP）製程等）對包封體材料400’及半導體基板210進行薄化或平坦化。在一些實施例中，包封體400在側向上包封晶粒200。也就是說，晶粒200的後表面200b實質上與包封體400的頂表面共面，且包封體400覆蓋晶粒200的側壁。在一些實施例中，包封體400可被稱為「間隙填充氧化物（gap fill oxide）」。
參考圖1E，在包封體400及介電層130中形成多個絕緣層穿孔（through insulating via；TIV）500。在一些實施例中，TIV 500形成在晶粒200旁。在一些實施例中，TIV 500穿透過包封體400及介電層130，以直接接觸對位標記124。也就是說，對位標記124位於TIV 500與接觸通孔112之間。在一些實施例中，TIV 500電性連接到對位標記124及接觸通孔112。換句話說，TIV 500通過對位標記124及接觸通孔112被電性接地。在一些實施例中，TIV 500的材料包括鋁、鈦、銅、鎳、鎢及/或其合金。在一些實施例中，TIV 500可通過以下步驟形成。首先，對包封體400及介電層130執行雷射鑽孔或蝕刻製程以形成多個開口（未繪示）。所述開口暴露出每一對位標記124的至少一部分。此後，執行鍍覆製程以填充開口，從而形成TIV 500。
參考圖1E及圖1F，將圖1E所示的結構放置在薄化平臺ST1上。在一些實施例中，薄化平臺ST1可被電性連接到地（ground）。隨後，對晶粒200、包封體400及TIV 500進行薄化，直到暴露出晶粒200的TSV 250。也就是說，晶粒200從後表面200b進行薄化。在一些實施例中，可通過研磨製程（例如機械研磨製程、CMP製程等）對晶粒200、包封體400及TIV 500進行薄化或平坦化。在一些實施例中，在暴露出TSV 250之後，可進一步對晶粒200、包封體400及TIV 500進行薄化，以減小晶粒200的總厚度。在薄化製程之後，晶粒200的後表面200c實質上與包封體400的頂表面400a及TIV 500的頂表面500a共面。如圖1F所示，在薄化製程之後，TSV 250穿透過晶粒200的半導體基板210。
在一些實施例中，在薄化製程期間，電子會在研磨表面（即，晶粒200的後表面200c、包封體400的頂表面400a及TIV 500的頂表面500a）產生並累積。電子的累積會導致TSV 250及TIV 500的腐蝕問題（corrosion issue）。不過，由於TIV 500被電性接地，所以TIV 500能夠建立使所累積的電子耗盡（deplete）的路徑。換句話說，如圖1F所示，所累積的電子將被下拉且依序經過TIV 500及對位標記124而到達接觸通孔112。接觸通孔112中的電子可進一步被轉移出所述結構。因此，由電子累積引起的腐蝕問題可得到解決。
參考圖1G，移除每一晶粒200的一部分以形成多個凹槽R1。舉例來說，移除每一晶粒200的半導體基板210的一部分以形成凹槽R1。如圖1G所示，TSV 250局部地位於凹槽R1中。在一些實施例中，每一TSV 250的至少一部分從晶粒200的半導體基板210突出。也就是說，TSV 250的頂表面250a、包封體400的頂表面400a及TIV 500的頂表面500a位於比晶粒200的後表面200d高的水平高度處。在一些實施例中，可通過蝕刻製程局部地移除半導體基板210。蝕刻製程包括例如等向性蝕刻製程（isotropic etching process）及/或非等向性蝕刻製程（anisotropic etching process）。舉例來說，可通過濕式蝕刻製程、乾式蝕刻製程或其組合局部地移除半導體基板210。
參考圖1H，形成保護層600以填充凹槽R1。在一些實施例中，保護層600包括模製化合物、模製底部填充膠等。作為另外一種選擇，保護層600可由聚合材料（例如聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、BCB、PBO或其他合適的聚合物系介電材料）製成。在一些實施例中，保護層600可包含填料。作為另外一種選擇，保護層600可不含填料。如圖1H所示，每一TSV 250的突出部分由保護層600在側向上包封。在一些實施例中，保護層600可通過以下步驟形成。首先，保護材料層（未繪示）形成在凹槽R1中以及包封體400及TIV 500上。隨後，對保護材料層執行研磨或薄化製程，直到顯露出TSV 250及TIV 500。薄化製程包括例如機械研磨製程、CMP製程等。類似於圖1F所示的製程，在薄化製程期間，會在研磨表面產生且累積電子。再次，被電性接地的TIV 500能夠建立使所累積的電子耗盡的路徑，從而解決由電子累積引起的腐蝕問題。
參考圖1H及圖1I，從薄化平臺ST1分離所述結構。此後，在晶粒200、包封體400及TIV 500上形成接合層700。在一些實施例中，接合層700是與接合層300相對地形成在晶粒200上。在一些實施例中，接合層700包括介電層702、多個接合墊704及多個連接墊706。在一些實施例中，接合墊704及連接墊706嵌置在介電層702中。在一些實施例中，接合墊704形成在晶粒200的TSV 250上，而連接墊706形成在TIV 500上。也就是說，接合墊704連接到TSV 250，且連接墊706連接到TIV 500。舉例來說，連接墊706通過TIV 500、對位標記124及接觸通孔112被電性接地。在一些實施例中，連接墊706可為可選的。
在一些實施例中，介電層702的材料包括氧化物，例如氧化矽等。作為另外一種選擇，介電層702可包含聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、BCB、PBO或任何其他合適的聚合物系介電材料。舉例來說，介電層702可通過合適的製作技術（例如旋轉塗布、CVD、PECVD等）形成。在一些實施例中，接合墊704及連接墊706包含相同的材料。用於接合墊704及連接墊706的材料例如是鋁、鈦、銅、鎳、鎢或其合金。在一些實施例中，接合墊704及連接墊706可同時形成。
在一些實施例中，介電層702的頂表面、接合墊704的頂表面與連接墊706的頂表面可被統稱為接合表面S700 。如圖1I所示，介電層702的頂表面、接合墊704的頂表面與連接墊706的頂表面實質上位於相同的水平高度處，以提供適合於混合接合（hybrid bonding）的接合表面S700 。
參考圖1J，在晶粒200上堆疊多個晶粒800。在一些實施例中，每一晶粒800包括半導體基板810、內連結構820、鈍化層830、導電墊840、多個半導體穿孔（through semiconductor via；TSV）850及多個接合通孔860。在一些實施例中，圖1J中的半導體基板810類似於圖1B中的半導體基板210，因此在此不再對其予以贅述。如圖1J所示，內連結構820設置在半導體基板810上。在一些實施例中，內連結構820包括介電間層822及多個導電圖案824。內連結構820的介電間層822及導電圖案824分別類似於內連結構220的介電間層222及導電圖案224，因此在此不再對其予以贅述。
在一些實施例中，導電墊840設置在內連結構820上且電性連接到內連結構820。另一方面，鈍化層830形成在內連結構820上以密封導電墊840。如圖1J所示，TSV 850嵌置在半導體基板810中。在一些實施例中，TSV 850電性連接到內連結構820的導電圖案824。晶粒800的鈍化層830、導電墊840及TSV 850分別類似於晶粒200的鈍化層230、導電墊240及TSV 250，因此在此不再對其予以贅述。
在一些實施例中，接合通孔860穿透過鈍化層830以建立與內連結構820的導電圖案824的電性連接。在一些實施例中，接合通孔860的材料可包括鋁、鈦、銅、鎳、鎢或其合金。在一些實施例中，接合通孔860可通過鍍覆製程等形成。
在一些實施例中，晶粒800能夠執行儲存功能。舉例來說，晶粒800可為動態隨機存取記憶體（Dynamic Random Access Memory；DRAM）、電阻式隨機存取記憶體（Resistive Random Access Memory；RRAM）、靜態隨機存取記憶體（Static Random Access Memory；SRAM）等。然而，本公開並不僅限於此。在一些替代性實施例中，晶粒800可為中央處理器（CPU）晶粒、圖形處理單元（GPU）晶粒、現場可程式設計閘陣列（FPGA）等。
在一些實施例中，每一晶粒800具有主動表面800a及與主動表面800a相對的後表面800b。在一些實施例中，在放置晶粒800之前，在每一晶粒800的主動表面800a上形成接合層900。舉例來說，接合層900形成在晶粒800的鈍化層830及接合通孔860上。在一些實施例中，接合層900包括介電層902及嵌置在介電層902中的多個接合墊904。在一些實施例中，接合層900的接合墊904電性連接到接合通孔860。也就是說，接合通孔860電性連接內連結構820與接合層900的接合墊904。圖1J中的介電層902及接合墊904分別類似於圖1I中的介電層702及接合墊704，因此在此不再對其予以贅述。
在一些實施例中，介電層902的底表面與接合墊904的底表面可被統稱為接合表面S900 。如圖1J所示，介電層902的底表面與接合墊904的底表面實質上位於相同的水平高度處，以提供適合於混合接合的接合表面S900 。
如圖1J所示，各個晶粒800被單獨放置在對應的晶粒200上，使得每一晶粒800通過接合層700及接合層900而接合到對應的晶粒200。舉例來說，接合層900夾置在接合層700與晶粒800之間。在一些實施例中，接合層700通過混合接合製程接合到接合層900。在一些實施例中，混合接合製程的溫度介於從約150℃到約400℃的範圍內。混合接合製程將在下文詳細闡述。
在一些實施例中，上面形成有接合層900的晶粒800可被拾取並放置到接合層700的接合表面S700 上，使得晶粒800電性連接到晶粒200。在一些實施例中，接合層900的接合表面S900 與接合層700的接合表面S700 接觸。舉例來說，接合層900的接合墊904實質上與接合層700的對應的接合墊704對齊且直接接觸。在一些實施例中，為了促進接合層700與接合層900之間的混合接合，可執行對接合層700與接合層900的接合表面（即，接合表面S700 與接合表面S900 ）的表面準備。舉例來說，表面準備可包括表面清潔及活化。可對接合表面S700 及接合表面S900 執行表面清潔，以移除介電層702的接合表面、接合墊704的接合表面、介電層902的接合表面及接合墊904的接合表面上的顆粒。在一些實施例中，例如，可通過濕式清潔（wet cleaning）來清潔接合表面S700 及接合表面S900 。不僅顆粒被移除，而且形成在接合墊704與接合墊904的接合表面上的原生氧化物（native oxide）也可被移除。舉例來說，可通過在濕式清潔製程中使用的化學品來移除形成在接合墊704的接合表面及接合墊904的接合表面上的原生氧化物。
在清潔接合層700的接合表面S700 及接合層900的接合表面S900 之後，可執行介電層702的接合表面及介電層902的接合表面的活化，以形成高接合強度。在一些實施例中，可執行電漿活化來處理介電層702的接合表面及介電層902的接合表面。當介電層702的經活化的接合表面接觸介電層902的經活化的接合表面時，接合層700的介電層702與接合層900的介電層902被預接合。
在將接合層900預接合到接合層700上之後，執行接合層700與接合層900的混合接合。接合層700與接合層900的混合接合可包括用於介電質接合的熱處理及用於導體接合的熱退火（thermal annealing）。在一些實施例中，執行用於介電質接合的熱處理以強化介電層702與介電層902之間的接合。舉例來說，用於介電質接合的熱處理可在介於從約200℃到約400℃的範圍內的溫度下執行。在執行用於介電質接合的熱處理之後，執行用於導體接合的熱退火以促進接合墊704與接合墊904之間的接合。舉例來說，用於導體接合的熱退火可在介於從約150℃到約400℃的範圍內的溫度下執行。在執行用於導體接合的熱退火之後，介電層702被混合接合到介電層902且接合墊704被混合接合到接合墊904。舉例來說，介電層702直接接觸介電層902。類似地，接合墊704直接接觸接合墊904。因此，接合層700被混合接合到接合層900。儘管圖1J示出接合墊704及接合墊904具有尖角（側壁垂直於頂表面/底表面），但本公開並不限於此。在一些替代性實施例中，在接合墊704被混合接合到接合墊904之後，可發生接合墊的角圓化（corner rounding）。舉例來說，面向接合墊904的接合墊704的為圓角。類似地，面向接合墊704的接合墊904的角也為圓角。也就是說，每一接合墊704的頂表面的邊緣為弧形的。類似地，每一接合墊904的底表面的邊緣也為弧形的。此外，儘管圖1J示出接合墊704與接合墊904具有相同的寬度且接合墊704的側壁與接合墊904的側壁對齊，但本公開並不限於此。在一些替代性實施例中，每一接合墊704的寬度可小於或大於每一接合墊904的寬度。
在一些實施例中，由於圖1I中的結構是晶圓形式（wafer form），且在上面形成有接合層900的晶粒800是晶片形式（chip form），因此圖1J中的混合接合製程可被稱為「晶圓上晶片接合製程（chip-on-wafer bonding process）」。
參考圖1K，在接合層700上形成包封體1000，以在側向上包封晶粒800及接合層900。也就是說，晶粒800的後表面800b實質上與包封體1000的頂表面共面，且包封體1000覆蓋晶粒800的側壁及接合層900的側壁。在一些實施例中，包封體1000可被稱為「間隙填充氧化物」。在一些實施例中，圖1K中的包封體1000的材料及形成方法類似於圖1D中的包封體400，因此在此不再對其予以贅述。
參考圖1L，在晶粒800及包封體1000上依序地形成介電層1100、接合層1200及載板1300。在一些實施例中，介電層1100可通過合適的製作技術（例如氣相沉積、旋轉塗布、ALD、熱氧化、一些其他合適的沉積或生長製程、或其組合）形成。氣相沉積可包括例如CVD、PVD、一些其他合適的氣相沉積製程或其組合。在一些實施例中，介電層1100的材料可為聚醯亞胺、PBO、BCB、氮化物（例如氮化矽）、氧化物（例如氧化矽）、USG、PSG、BSG、BPSG、其組合等。在一些實施例中，介電層1100能夠在後續製程期間控制翹曲（warpage）。
在一些實施例中，接合層1200是具有連續均勻表面的平滑層。在一些實施例中，接合層1200的材料可包括氮氧化矽（SiON）、氧化矽、氮化矽等，且接合層1200可通過沉積等形成。在一些實施例中，接合層1200具有實質上均一且均勻的厚度。
在一些實施例中，載板1300接合到接合層1200。在一些實施例中，載板1300包括半導體材料。舉例來說，載板1300可由以下半導體製成：合適的元素半導體，例如晶體矽、金剛石或鍺；合適的化合物半導體，例如砷化鎵、碳化矽、砷化銦或磷化銦；或者合適的合金半導體，例如碳化矽鍺、磷化鎵砷或磷化鎵銦。然而，本公開並不限於此。在一些替代性實施例中，載板1300可為玻璃基板。在一些實施例中，載板1300不含主動元件及被動元件。在一些實施例中，載板1300也不包括佈線。舉例來說，載板1300可為空白基板（blank substrate），其僅用作支撐元件，而不提供任何信號傳輸功能。在一些實施例中，由於載板1300是晶圓形式，所以圖1L所示的製程可被稱為「晶圓對晶圓接合（wafer-to-wafer bonding）」。
參考圖1L及圖1M，移除半導體基板110、接觸通孔112、對位層120、介電層130、接合層300、每一TIV 500的一部分及包封體400的一部分，以暴露出包封體400、TIV 500及晶粒200的主動表面200a。在一些實施例中，這些元件可通過機械研磨製程、CMP製程或蝕刻製程來移除。在一些實施例中，在移除接觸通孔112之後，TIV 500及連接墊706不再連接到地電壓。也就是說，在移除接觸通孔112之後，TIV 500及連接墊706是電性浮動（electrically floating）的。
參考圖1N，在晶粒200、TIV 500及包封體400上形成介電層1400。在一些實施例中，介電層1400可通過合適的製作技術（例如氣相沉積、旋轉塗布、ALD、熱氧化、一些其他合適的沉積或生長製程、或其組合）形成。氣相沉積可包括例如CVD、PVD、一些其他合適的氣相沉積製程或其組合。在一些實施例中，介電層1400的材料可為聚醯亞胺、PBO、BCB、氮化物（例如氮化矽）、氧化物（例如氧化矽）、USG、PSG、BSG、BPSG、其組合等。
參考1O，在介電層1400上形成多個導電端子1500。在一些實施例中，導電端子1500例如是焊料球、球柵陣列（ball grid array；BGA）球或受控塌陷晶片連接（controlled collapse chip connection；C4）凸塊。在一些實施例中，導電端子1500由具有低電阻率的導電材料（例如Sn、Pb、Ag、Cu、Ni、Bi或其合金）製成。在一些實施例中，導電端子1500可通過以下步驟形成。首先，在介電層1400及晶粒200的鈍化層230中形成多個開口（未繪示），以暴露出晶粒200的導電墊240。隨後，通過植球製程（ball placement process）等在介電層1400上形成導電端子1500。在一些實施例中，導電端子1500延伸到開口中，以直接接觸晶粒200的導電墊240。換句話說，導電端子1500電性連接到晶粒200的導電墊240。
參考圖1O及圖1P，在切割道區SR上執行單體化製程以形成多個封裝10。在一些實施例中，切割製程（dicing process）或單體化製程通常涉及使用旋轉刀片（rotating blade）或雷射光束進行切割。換句話說，切割或單體化製程舉例來說是雷射切削製程、機械切削製程或其他合適的製程。如圖1P所示，晶粒800堆疊在晶粒200上。換句話說，多個晶粒200、800被集成到單個封裝10中。因此，封裝10可被稱為「積體電路級系統（system on integrated circuit，SOIC）封裝」。在一些實施例中，封裝10可用於其他模組/應用中，例如基板上晶圓上晶片（chip on wafer on substrate；CoWoS）封裝、覆晶（flip-chip）封裝、積體扇出（integrated fan-out；InFO）封裝、扇出晶圓級封裝（fan-out wafer level packaging；fan-out WLP）等。
圖2A到圖2E是根據本公開的一些替代性實施例的封裝20的製造流程的示意性剖視圖。參考圖2A，圖2A中的結構類似於圖1L中的結構，因此其類似的元件由相同的附圖標號表示，且在此不再對其予以贅述。換句話說，圖2A中的結構可通過執行圖1A到圖1L中所示的步驟來獲得。然而，在圖2A中的結構的製造流程中省略了介電層130的形成。換句話說，圖2A中的結構與圖1L中的結構之間的差異在於省略了介電層130，且對位標記124直接接觸圖2A中的包封體400。
參考圖2B到圖2E，圖2B到圖2E中的步驟類似於圖1M到圖1P中所示的步驟，因此其類似的元件由相同的附圖標號表示，且在此不再對其予以贅述。參考圖2E，獲得多個封裝20。如圖2E所示，晶粒800堆疊在晶粒200上。換句話說，多個晶粒200、800被集成到單個封裝20中。因此，封裝20可被稱為「SOIC封裝」。在一些實施例中，封裝20可用於其他模組/應用中，例如CoWoS封裝、覆晶封裝、InFO封裝、扇出WLP等。
圖3A到圖3E是根據本公開的一些替代性實施例的封裝30的製造流程的示意性剖視圖。參考圖3A，圖3A中的結構類似於圖1L中的結構，因此其類似的元件由相同的附圖標號表示，且在此不再對其予以贅述。換句話說，圖3A中的結構可通過執行圖1A到圖1L中所示的步驟來獲得。然而，在圖3A中，接觸通孔112、對位標記124、TIV 500及連接墊706形成在切割道區SR中。
參考圖3B到圖3E，圖3B到圖3E中的步驟類似於圖1M到圖1P中所示的步驟，因此其類似的元件由相同的附圖標號表示，且在此不再對其予以贅述。參考圖3D及圖3E，在切割道區SR上執行單體化製程以形成多個封裝30。換句話說，移除位於切割道區SR中的TIV 500及連接墊706。如圖3E所示，晶粒800堆疊在晶粒200上。換句話說，多個晶粒200、800被集成到單個封裝30中。因此，封裝30可被稱為「SOIC封裝」。在一些實施例中，封裝30可用於其他模組/應用中，例如CoWoS封裝、覆晶封裝、InFO封裝、扇出WLP等。
圖4A到圖4M是根據本公開的一些替代性實施例的封裝40的製造流程的示意性剖視圖。參考圖4A，圖4A中的結構類似於圖1K中的結構，因此其類似的元件由相同的附圖標號表示，且在此不再對其予以贅述。換句話說，圖4A中的結構可通過執行圖1A到圖1K中所示的步驟來獲得。
參考圖4B，在包封體1000中形成多個TIV 1600。在一些實施例中，TIV 1600形成在晶粒800旁。在一些實施例中，TIV 1600穿透過包封體1000以直接接觸連接墊706。在一些實施例中，TIV 1600電性連接到連接墊706。換句話說，TIV 1600通過連接墊706、TIV 500、對位標記124及接觸通孔112被電性接地。如圖4B所示，TIV 1600實質上與TIV 500對齊。在一些實施例中，TIV 1600的材料包括鋁、鈦、銅、鎳、鎢及/或其合金。在一些實施例中，TIV 1600可通過以下步驟形成。首先，對包封體1000執行雷射鑽孔或蝕刻製程以形成多個開口（未繪示）。所述開口暴露出每一連接墊706的至少一部分。此後，可執行鍍覆製程以填充開口，從而形成TIV 1600。
參考圖4B及圖4C，將圖4B所示的結構放置在薄化平臺ST2上。在一些實施例中，薄化平臺ST2可被電性連接到地。隨後，對晶粒800、包封體1000及TIV 1600進行薄化，直到暴露出晶粒800的TSV 850。也就是說，晶粒800從後表面800b進行薄化。在一些實施例中，可通過研磨製程（例如機械研磨製程、CMP製程等）對晶粒800、包封體1000及TIV 1600進行薄化或平坦化。在一些實施例中，在暴露出TSV 850之後，可進一步對晶粒800、包封體1000及TIV 1600進行薄化，以減小晶粒800的總厚度。在薄化製程之後，晶粒800的後表面800c實質上與包封體1000的頂表面1000a及TIV 1600的頂表面1600a共面。如圖4C所示，在薄化製程之後，TSV 850穿透過晶粒800的半導體基板810。
在一些實施例中，在薄化製程期間，電子會在研磨表面（即，晶粒800的後表面800c、包封體1000的頂表面1000a及TIV 1600的頂表面1600a）產生並累積。電子的累積會導致TSV 850及TIV 1600的腐蝕問題。不過，由於TIV 1600被電性接地，所以TIV 1600能夠建立使所累積的電子耗盡的路徑。換句話說，如圖4C所示，所累積的電子將被下拉且依序經過TIV 1600、連接墊706、TIV 500及對位標記124而到達接觸通孔112。接觸通孔112中的電子可進一步被轉移出所述結構。因此，由電子累積引起的腐蝕問題可得到解決。
參考圖4D，移除每一晶粒800的一部分以形成多個凹槽R2。舉例來說，移除每一晶粒800的半導體基板810的一部分以形成凹槽R2。如圖4D所示，TSV 850局部地位於凹槽R2中。在一些實施例中，每一TSV 850的至少一部分從晶粒800的半導體基板810突出。也就是說，TSV 850的頂表面850a、包封體1000的頂表面1000a及TIV 1600的頂表面1600a位於比晶粒800的後表面800d高的水平高度處。在一些實施例中，可通過蝕刻製程局部地移除半導體基板810。蝕刻製程包括例如等向性蝕刻製程及/或非等向性蝕刻製程。舉例來說，可通過濕式蝕刻製程、乾式蝕刻製程或其組合局部地移除半導體基板810。
參考圖4E，形成保護層1700以填充凹槽R2。在一些實施例中，保護層1700包括模製化合物、模製底部填充膠等。作為另外一種選擇，保護層1700可由聚合材料（例如聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、BCB、PBO或其他合適的聚合物系介電材料）製成。在一些實施例中，保護層1700可包含填料。作為另外一種選擇，保護層1700可不含填料。如圖4E所示，每一TSV 850的突出部分由保護層1700在側向上包封。在一些實施例中，保護層1700可通過以下步驟形成。首先，保護材料層（未繪示）形成在凹槽R2中以及包封體1000及TIV 1600上。隨後，對保護材料層執行研磨或薄化製程，直到顯露出TSV 850及TIV 1600。在一些實施例中，薄化製程包括例如機械研磨製程、CMP製程等。類似於圖4C所示的製程，在薄化製程期間，會在研磨表面產生且累積電子。再次，被電性接地的TIV 1600能夠建立使所累積的電子耗盡的路徑，從而解決由電子累積引起的腐蝕問題。
參考圖4E及圖4F，從薄化平臺ST2分離所述結構。此後，在晶粒800、包封體1000、及TIV 1600上形成接合層1800。在一些實施例中，接合層1800是與接合層900相對地形成在晶粒800上。在一些實施例中，接合層1800包括介電層1802、多個接合墊1804及多個連接墊1806。在一些實施例中，接合墊1804及連接墊1806嵌置在介電層1802中。在一些實施例中，接合墊1804形成在晶粒800的TSV 850上，而連接墊1806形成在TIV 1600上。也就是說，接合墊1804連接到TSV 850，且連接墊1806連接到TIV 1600。舉例來說，連接墊1806通過TIV 1600、連接墊706、TIV 500、對位標記124及接觸通孔112被電性接地。在一些實施例中，連接墊1806可為可選的。
在一些實施例中，圖4F中的介電層1802、接合墊1804及連接墊1806分別類似於圖1I中的介電層702、接合墊704及連接墊706，因此在此不再對其予以贅述。在一些實施例中，介電層1802的頂表面、接合墊1804的頂表面及連接墊1806的頂表面可被統稱為接合表面S1800 。如圖4F所示，介電層1802的頂表面、接合墊1804的頂表面與連接墊1806的頂表面實質上位於相同的水平高度處，以提供適合於混合接合的接合表面S1800 。
參考圖4G，在晶粒800上堆疊多個晶粒1900。在一些實施例中，每一晶粒1900包括半導體基板1910、內連結構1920、鈍化層1930、導電墊1940、多個TSV 1950及多個接合通孔1960。在一些實施例中，內連結構1920包括介電間層1922及多個導電圖案1924。在一些實施例中，圖4G中的半導體基板1910、內連結構1920、鈍化層1930、導電墊1940、TSV 1950及接合通孔1960分別類似於圖1J中的半導體基板810、內連結構820、鈍化層830、導電墊840、TSV 850及接合通孔860，因此在此不再對其予以贅述。
在一些實施例中，晶粒1900能夠執行儲存功能。舉例來說，晶粒1900可為動態隨機存取記憶體（DRAM）、電阻式隨機存取記憶體（RRAM）、靜態隨機存取記憶體（SRAM）等。然而，本公開並不僅限於此。在一些替代性實施例中，晶粒1900可為中央處理器（CPU）晶粒、圖形處理單元（GPU）晶粒、現場可程式設計閘陣列（FPGA）等。
在一些實施例中，每一晶粒1900具有主動表面1900a及與主動表面1900a相對的後表面1900b。在一些實施例中，在放置晶粒1900之前，在每一晶粒1900的主動表面1900a上形成接合層2000。舉例來說，接合層2000形成在晶粒1900的鈍化層1930及接合通孔1960上。在一些實施例中，接合層2000包括介電層2002及嵌置在介電層2002中的多個接合墊2004。在一些實施例中，接合層2000的接合墊2004電性連接到接合通孔1960。也就是說，接合通孔1960電性連接內連結構1920與接合層2000的接合墊2004。圖4G中的介電層2002及接合墊2004分別類似於圖1J中的介電層902及接合墊904，因此在此不再對其予以贅述。
在一些實施例中，介電層2002的底表面與接合墊2004的底表面可被統稱為接合表面S2000 。如圖4G所示，介電層2002的底表面與接合墊2004的底表面實質上位於相同的水平高度處，以提供適合於混合接合的接合表面S2000 。
如圖4G所示，各個晶粒1900被單獨放置在對應的晶粒800上，使得每一晶粒1900通過接合層1800及接合層2000而接合到對應的晶粒800。舉例來說，接合層2000夾置在接合層1800與晶粒1900之間。在一些實施例中，接合層1800通過混合接合製程接合到接合層2000。圖4G中的混合接合製程可類似於圖1J中所示的混合接合製程，因此在此不再對其予以贅述。
參考圖4H，在接合層1800上形成包封體2100，以在側向上包封晶粒1900及接合層2000。也就是說，晶粒1900的後表面1900b實質上與包封體2100的頂表面共面，且包封體2100覆蓋晶粒1900的側壁及接合層2000的側壁。在一些實施例中，包封體2100可被稱為「間隙填充氧化物」。在一些實施例中，圖4H中的包封體2100的材料及形成方法類似於圖1K中的包封體1000，因此在此不再對其予以贅述。
參考圖4I，在晶粒1900及包封體2100上依序地形成介電層2200、接合層2300及載板2400。在一些實施例中，圖4I中的介電層2200、接合層2300及載板2400分別類似於圖1L中的介電層1100、接合層1200及載板1300，因此在此不再對其予以贅述。在一些實施例中，由於載板2400是晶圓形式，所以圖4I中所示的製程可被稱為「晶圓對晶圓接合」。
參考圖4I及圖4J，移除半導體基板110、接觸通孔112、對位層120、介電層130、接合層300、每一TIV 500的一部分及包封體400的一部分，以暴露出包封體400、TIV 500及晶粒200的主動表面200a。在一些實施例中，這些元件可通過機械研磨製程、CMP製程或蝕刻製程來移除。在一些實施例中，在移除接觸通孔112之後，TIV 500、連接墊706、TIV 1600及連接墊1806不再連接到地電壓。也就是說，在移除接觸通孔112之後，TIV 500、連接墊706、TIV 1600及連接墊1806是電性浮動的。
參考圖4K，在晶粒200、TIV 500及包封體400上形成介電層2500。在一些實施例中，圖4K中的介電層2500類似於圖1N中的介電層1400，因此在此不再對其予以贅述。
參考圖4L，在介電層2500上形成多個導電端子2600。在一些實施例中，圖4L中的導電端子2600類似於圖1O中的導電端子1500，因此在此不再對其予以贅述。
參考圖4L到圖4M，在切割道區SR上執行單體化製程以形成多個封裝40。在一些實施例中，切割製程或單體化製程通常涉及使用旋轉刀片或雷射光束進行切割。換句話說，切割或單體化製程舉例來說是雷射切削製程、機械切削製程或其他合適的製程。如圖4M所示，晶粒800堆疊在晶粒200上且晶粒1900堆疊在晶粒800上。換句話說，多個晶粒200、800、1900被集成到單個封裝40中。因此，封裝40可被稱為「SOIC封裝」。在一些實施例中，封裝40可用於其他模組/應用中，例如CoWoS封裝、覆晶封裝、InFO封裝、扇出WLP等。
圖5A到圖5E是根據本公開的一些替代性實施例的封裝50的製造流程的示意性剖視圖。參考圖5A，圖5A中的結構類似於圖4I中的結構，因此其類似的元件由相同的附圖標號表示，且在此不再對其予以贅述。換句話說，圖5A中的結構可通過執行圖4A到圖4I中所示的步驟來獲得。然而，在圖5A的結構的製造流程中省略了介電層130的形成。換句話說，圖5A中的結構與圖4I中的結構之間的差異在於省略了介電層130，且對位標記124直接接觸圖5A中的包封體400。
參考圖5B到圖5E，圖5B到圖5E中的步驟類似於圖4J到圖4M中所示的步驟，因此其類似的元件由相同的附圖標號表示，且在此不再對其予以贅述。參考圖5E，獲得多個封裝50。如圖5E所示，晶粒800堆疊在晶粒200上且晶粒1900堆疊在晶粒800上。換句話說，多個晶粒200、800、1900被集成到單個封裝50中。因此，封裝50可被稱為「SOIC封裝」。在一些實施例中，封裝50可用於其他模組/應用中，例如CoWoS封裝、覆晶封裝、InFO封裝、扇出WLP等。
根據本公開的一些實施例，一種封裝包括第一晶粒、第二晶粒、第一包封體、第一絕緣層穿孔（through insulating via；TIV）、第二包封體以及第二TIV。所述第二晶粒堆疊在所述第一晶粒上。所述第一包封體在側向上包封所述第一晶粒。所述第一TIV位於所述第一晶粒旁。所述第一TIV穿透過所述第一包封體且是電性浮動的。所述第二包封體在側向上包封所述第二晶粒。所述第二TIV位於所述第二晶粒旁。所述第二TIV穿透過所述第二包封體且是電性浮動的。所述第二TIV實質上與所述第一TIV對齊。
根據本公開的一些實施例，所述封裝還包括第一接合層以及第二接合層。所述第一接合層位於所述第一晶粒、所述第一包封體及所述第一絕緣層穿孔上。所述第一接合層包括第一接合墊及連接墊，且所述第一絕緣層穿孔連接到所述連接墊。所述第二接合層夾置在所述第一接合層與所述第二晶粒之間。所述第二接合層包括第二接合墊，且所述第一接合墊被混合接合到所述第二接合墊。
根據本公開的一些實施例，所述封裝還包括載板。所述載板位於所述第二晶粒及所述第二包封體上。
根據本公開的一些實施例，所述第一晶粒包括第一半導體基板、第一半導體穿孔（through semiconductor via；TSV）、第一內連結構、第一鈍化層以及第一導電墊。所述第一半導體穿孔穿透過所述第一半導體基板。所述第一內連結構位於所述第一半導體基板上且電性連接到所述第一半導體穿孔。所述第一鈍化層位於所述第一內連結構上。所述第一導電墊位於所述第一內連結構上且電性連接到所述第一內連結構。
根據本公開的一些實施例，所述封裝還包括電性連接到所述第一晶粒的所述第一導電墊的導電端子。
根據本公開的一些實施例，所述第二晶粒包括第二半導體基板、第二半導體穿孔、第二內連結構、第二鈍化層以及第二導電墊。所述第二半導體穿孔嵌置在所述第二半導體基板中。所述第二內連結構位於所述第二半導體基板上且電性連接到所述第二半導體穿孔。所述第二鈍化層位於所述第二內連結構上。所述第二導電墊嵌置在所述第二鈍化層中。
根據本公開的一些實施例，所述封裝還包括第三晶粒、第三包封體以及載板。所述第三晶粒堆疊在所述第二晶粒上。所述第三包封體在側向上包封所述第三晶粒。所述載板位於所述第三晶粒及所述第三包封體上。
根據本公開的一些實施例，一種封裝的製造方法包括至少以下步驟。提供其中嵌置有接觸通孔的半導體載板。所述接觸通孔被電性接地。將第一晶粒放置在所述半導體載板上。所述第一晶粒包括第一半導體基板及嵌置在所述第一半導體基板中的第一半導體穿孔（through semiconductor via；TSV）。使用第一包封體在側向上包封所述第一晶粒。在所述第一包封體中形成第一絕緣層穿孔（through insulating via；TIV）。所述第一TIV通過所述接觸通孔被電性接地。對所述第一晶粒、所述第一包封體及所述第一TIV進行研磨，直到暴露出所述第一晶粒的所述第一TSV。將第二晶粒堆疊在所述第一晶粒上。移除所述半導體載板。
根據本公開的一些實施例，所述封裝的製造方法還包括在所述半導體載板上形成對位層，其中所述對位層包括對位標記。
根據本公開的一些實施例，所述對位標記形成在所述接觸通孔與所述第一絕緣層穿孔之間且電性連接到所述接觸通孔及所述第一絕緣層穿孔。
根據本公開的一些實施例，所述封裝的製造方法還包括在所述對位層與所述第一包封體之間形成介電層，其中所述第一絕緣層穿孔穿透過所述介電層。
根據本公開的一些實施例，所述封裝的製造方法還包括至少以下步驟。在所述第一晶粒、所述第一包封體及所述第一絕緣層穿孔上形成第一接合層。在所述第二晶粒上形成第二接合層，其中所述第一接合層被混合接合到所述第二接合層。
根據本公開的一些實施例，所述封裝的製造方法還包括至少以下步驟。使用第二包封體在側向上包封所述第二晶粒及所述第二接合層。在所述第二晶粒及所述第二包封體上形成載板。
根據本公開的一些實施例，所述第二晶粒包括第二半導體基板及嵌置在所述第二半導體基板中的第二半導體穿孔，且所述封裝的製造方法還包括至少以下步驟。使用第二包封體在側向上包封所述第二晶粒。在所述第二包封體中形成第二絕緣層穿孔，其中所述第二絕緣層穿孔通過所述第一絕緣層穿孔及所述接觸通孔被電性接地。對所述第二晶粒、所述第二包封體及所述第二絕緣層穿孔進行研磨，直到暴露出所述第二晶粒的所述第二半導體穿孔。
根據本公開的一些實施例，所述封裝的製造方法還包括至少以下步驟。將第三晶粒接合到所述第二晶粒。使用第三包封體在側向上包封所述第三晶粒。在所述第三晶粒及所述第三包封體上形成載板。
根據本公開的一些實施例，在對所述第一晶粒、所述第一包封體及所述第一絕緣層穿孔進行所述研磨期間，因所述研磨而產生的電子通過所述第一絕緣層穿孔從研磨表面行進到所述接觸通孔。
根據本公開的一些替代性實施例，一種封裝的製造方法包括至少以下步驟。提供其中嵌置有接觸通孔的半導體載板。所述半導體載板具有晶粒區及位於兩個相鄰的晶粒區之間的切割道區。所述接觸通孔位於所述切割道區中並被電性接地。將所述第一晶粒放置在所述半導體載板上的所述晶粒區中。所述第一晶粒中的每一第一晶粒包括半導體基板及嵌置在所述半導體基板中的半導體穿孔（through semiconductor via；TSV）。使用第一包封體在側向上包封所述第一晶粒。在所述第一包封體中形成絕緣層穿孔（through insulating via；TIV）。所述TIV位於所述切割道區中且通過所述接觸通孔被電性接地。對所述第一晶粒、所述第一包封體及所述TIV進行研磨，直到暴露出所述第一晶粒的所述TSV。將第二晶粒堆疊在所述第一晶粒上。移除所述半導體載板。執行單體化製程，以移除位於所述切割道區中的所述TIV。
根據本公開的一些替代性實施例，所述封裝的製造方法還包括至少以下步驟。在所述第一晶粒、所述第一包封體及所述絕緣層穿孔上形成第一接合層。在所述第二晶粒上形成第二接合層，其中所述第一接合層被混合接合到所述第二接合層。
根據本公開的一些替代性實施例，所述封裝的製造方法還包括至少以下步驟。使用第二包封體在側向上包封所述第二晶粒及所述第二接合層。在所述第二晶粒及所述第二包封體上形成載板。
根據本公開的一些替代性實施例，所述封裝的製造方法還包括至少以下步驟。移除每一第一晶粒的所述半導體基板的一部分，以形成凹槽。形成保護層來填充所述凹槽。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這種等效構造並不背離本公開的精神及範圍，且他們可在不背離本公開的精神及範圍的條件下在本文中作出各種改變、代替及變更。
10、20、30、40、50:封裝 110:半導體載板 112:接觸通孔 120:對位層 122、130、702、902、1100、1400、1802、2002、2200、2500:介電層 124:對位標記 200、800、1900:晶粒 200a、800a、1900a:主動表面 200b、200c、200d、800b、800c、800d、1900b:後表面 210、810、1910:半導體基板 220、820、1920:內連結構 222、822、1922:介電間層 224、824、1924:導電圖案 230、830、1930:鈍化層 240、840、1940:導電墊 250、850、1950:半導體穿孔 250a、400a、500a、850a、1000a、1600a:頂表面 300、700、900、1200、1800、2000、2300:接合層 400、1000、2100:包封體 400’:包封體材料 500、1600:絕緣層穿孔 600、1700:保護層 704、904、1804、2004:接合墊 706、1806:連接墊 860、1960:接合通孔 1300、2400:載板 1500、2600:導電端子 DR:晶粒區 R1、R2:凹槽 S700 、S900 、S1800 、S2000 :接合表面 SR:切割道區 ST1、ST2:薄化平臺
圖1A到圖1P是根據本公開的一些實施例的封裝的製造流程的示意性剖視圖。 圖2A到圖2E是根據本公開的一些替代性實施例的封裝的製造流程的示意性剖視圖。 圖3A到圖3E是根據本公開的一些替代性實施例的封裝的製造流程的示意性剖視圖。 圖4A到圖4M是根據本公開的一些替代性實施例的封裝的製造流程的示意性剖視圖。 圖5A到圖5E是根據本公開的一些替代性實施例的封裝的製造流程的示意性剖視圖。
10:封裝
702、902、1100、1400:介電層
200、800:晶粒
210、810:半導體基板
220、820:內連結構
222、822:介電間層
224、824:導電圖案
230、830:鈍化層
240、840:導電墊
250、850:半導體穿孔
700、900、1200:接合層
400、1000:包封體
500:絕緣層穿孔
600:保護層
704、904:接合墊
706:連接墊
860:接合通孔
1300:載板
1500:導電端子

Claims (1)

  1. 一種封裝，包括： 第一晶粒； 第二晶粒，堆疊在所述第一晶粒上； 第一包封體，在側向上包封所述第一晶粒； 第一絕緣層穿孔，位於所述第一晶粒旁，其中所述第一絕緣層穿孔穿透過所述第一包封體且是電性浮動的； 第二包封體，在側向上包封所述第二晶粒；以及 第二絕緣層穿孔，位於所述第二晶粒旁，其中所述第二絕緣層穿孔穿透過所述第二包封體且是電性浮動的，且所述第二絕緣層穿孔與所述第一絕緣層穿孔對齊。
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