TWI628762B - 半導體封裝及其製作方法 - Google Patents

半導體封裝及其製作方法 Download PDF

Info

Publication number
TWI628762B
TWI628762B TW106104555A TW106104555A TWI628762B TW I628762 B TWI628762 B TW I628762B TW 106104555 A TW106104555 A TW 106104555A TW 106104555 A TW106104555 A TW 106104555A TW I628762 B TWI628762 B TW I628762B
Authority
TW
Taiwan
Prior art keywords
substrate
metal
passivation layer
forming
item
Prior art date
Application number
TW106104555A
Other languages
English (en)
Other versions
TW201818520A (zh
Inventor
施信益
Original Assignee
美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美光科技公司 filed Critical 美光科技公司
Publication of TW201818520A publication Critical patent/TW201818520A/zh
Application granted granted Critical
Publication of TWI628762B publication Critical patent/TWI628762B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

本發明披露一種製作半導體封裝的方法。首先，提供一基板；接著於基板上形成一第一鈍化層；再形成複數個溝槽，延伸進入基板；然後於溝槽中形成金屬介層結構；隨後於第一鈍化層上形成一重佈線層結構；於重佈線層結構上形成一第二鈍化層；之後，於第二鈍化層中形成開孔，顯露出凸塊接墊；接著於凸塊接墊上形成第一金屬柱；然後於金屬柱上安置半導體晶片；再形成一成型模料，覆蓋半導體晶片；之後移除基板，從而顯露出第一鈍化層及各金屬介層結構的突出部分(第二金屬柱)；最後，分別於各第二金屬柱上直接形成C4凸塊。

Description

半導體封裝及其製作方法
本發明係有關於半導體封裝技術領域，更特定言之，本發明係有關於一種製作具有重佈線中介層結構的半導體封裝的方法。
積體電路(IC)晶片通常先經過封裝，再焊接到印刷電路板(PCB)上。積體電路晶片可透過控制崩塌晶片連接(C4)製程藉由多個焊錫凸塊連接到封裝基板。
如本領域所已知的，在半導體封裝中通常使用具有穿矽通孔(TSV)的中介層基板(諸如矽中介層)來「扇出」積體電路晶片的接點。然而，TSV矽中介層較為昂貴，因此，本領域仍期望提供一種具有中介層的改良半導體封裝，其不使用TSV和矽基板(無TSV的中介層)，而中介層仍然能夠提供非常細密的互連間距。
然而，沒有TSV的重佈線中介層結構厚度較薄，在封裝過程中不易處理。例如，中介層上用來進一步連接的接墊開孔通常是利用光學微影製程定義，而厚度較薄的重佈線中介層結構容易翹曲，可能導致光學微影製程對不準 問題，並因此造成良率降低。由此可知，本領域仍期望提供一種利用這種薄重佈線中介層結構來製造半導體封裝的方法，同時能夠克服上述的困難。
本發明的目的在提供一種改良的方法，用於製作具有薄重佈線中介層結構的半導體封裝，能解決上述先前技藝的不足與缺點。
本發明一方面，提出一種製作重佈線中介層結構的方法。首先，提供一基板，包含相對的一第一表面及一第二表面；接著於基板的第一表面上形成一第一鈍化層；再形成複數個溝槽，貫通第一鈍化層，並延伸進入基板；然後於溝槽中形成金屬介層結構；隨後於第一鈍化層上形成一重佈線層結構；最後，在重佈線層結構上形成用於進一步連接到半導體晶片的第一金屬柱。於重佈線層結構上形成第一金屬柱。
本發明一方面，提出一種製作半導體封裝的方法。首先，提供一基板，包含相對的一第一表面及一第二表面；接著於基板的第一表面上形成一第一鈍化層；再形成複數個溝槽，貫通第一鈍化層，並延伸進入基板；然後於複數個溝槽中形成凸塊下金屬(UBM)材料，以形成金屬介層結構；隨後於第一鈍化層上形成一重佈線層結構；於重佈線層結構上形成一第二鈍化層；之後，於第二鈍化層中形成開孔，顯露出重佈線層結構的凸塊接墊；接著於凸塊接墊上分別形成第一金屬柱；然後進行一晶片貼合製程，於第一金屬柱上安置半導體晶片；再形成一成型模料，覆蓋半導體晶片及第一鈍化層；之後透過研磨移除部分基板；隨後進行一濕式蝕刻製程，移除基板的剩餘部分，以顯露出第一鈍化層及各金屬介層結構的突出部分，從而形成第二金屬柱；最後，分別於各第 二金屬柱上直接形成一連接件(諸如焊錫凸塊)。
本發明另一方面，提出一種製作半導體封裝的方法。首先，提供一基板，包含相對的一第一表面及一第二表面；接著於基板的第一表面上形成一第一鈍化層；再形成複數個溝槽，貫通第一鈍化層，並延伸進入基板；然後於複數個溝槽中填入導電材料以形成金屬介層結構；隨後於第一鈍化層上形成一重佈線層結構；再於重佈線層結構上形成一第二鈍化層；之後，於第二鈍化層中形成開孔，顯露出重佈線層結構的凸塊接墊；接著於凸塊接墊上分別形成第一金屬柱；然後將重佈線層結構貼合一載板；接著對基板進行一基板薄化製程，移除部分基板；隨後進行一濕式回蝕刻製程，移除基板的剩餘部分，以顯露出第一鈍化層及各金屬介層結構的突出部分，以及形成第二金屬柱；之後於第二金屬柱上接合一半導體晶片；再形成一成型模料，覆蓋半導體晶片及第一鈍化層；接著移除載板，顯露出第一金屬柱及第二鈍化層；最後，分別於各第一金屬柱上直接形成一連接件(諸如焊錫凸塊)。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
10‧‧‧基板
10a‧‧‧第一表面
10b‧‧‧第二表面
11‧‧‧第一鈍化層
110‧‧‧溝槽
112‧‧‧金屬介層結構
20‧‧‧重佈線層(RDL)結構
201‧‧‧介電層
202‧‧‧繞線層
204‧‧‧凸塊接墊
21‧‧‧第二鈍化層
210‧‧‧開孔
320‧‧‧第一金屬柱
320a‧‧‧凸塊下金屬結構
320b‧‧‧導電凸塊
101‧‧‧第一半導體晶片
102‧‧‧第二半導體晶片
400‧‧‧成型模料
400a‧‧‧表面
112a‧‧‧第二金屬柱
620‧‧‧連接件
122‧‧‧金屬介層結構
322‧‧‧第一金屬柱
40‧‧‧載板
42‧‧‧黏著層
122a‧‧‧第二金屬柱
622‧‧‧連接件
附圖包括對本發明的實施例提供進一步的理解，及被併入且構成說明書中的一部份。圖示說明一些本發明的實施例，並與說明書一起用於解釋其原理。
第1圖至第9圖係根據本發明的一實施例所繪示的製作半導體封裝的示例性方法的剖面圖；以及第10圖至第20圖係根據本發明的另一實施例所繪示的製作半導體封裝的示例性方法的剖面圖。
於下文中，係加以陳述本發明之具體實施方式，該些具體實施方式可參考相對應的圖式，俾使該些圖式構成實施方式之一部分。同時也藉由說明，揭露本發明可據以施行之方式。該等實施例已被清楚地描述足夠的細節，俾使該技術領域中具有通常技術者可據以實施本發明。其他實施例亦可被加以施行，且對於其結構上所做之改變仍屬本發明所涵蓋之範疇。
因此，下文的細節描述將不被視為一種限定，且本發明所涵蓋之範疇僅被所附之申請專利範圍以及其同意義的涵蓋範圍。
本發明之一或多個實施例將參照附圖描述，其中，相同元件符號始終用以表示相同元件，且其中闡述的結構未必按比例所繪製。術語「晶粒」、「晶片」、「半導體晶片」及「半導體晶粒」於本說明書中可互換使用。
文中所使用的用語「晶圓」及「基板」包括任何具有暴露表面之結構，根據本發明，於該表面上可沉積有一至少層材料，例如，形成諸如重佈線層的電路結構。用語「基板」被理解為包括半導體晶圓，但不限於此。用語「基板」亦可用以指加工過程中之半導體結構，且可包括已被製造在其上之其它層。
第1圖至第9圖係根據本發明的一實施例所繪示的製作半導體封裝的示例性方法的剖面圖，其中，第1圖至第4圖說明製作薄重佈線中介層結構的示例性方法。
如第1圖所示，首先，提供一基板10。根據本發明一實施例，基板10可以包含矽或III-V半導體，但不限於此。例如，根據本發明一實施例，基板10可以是晶圓形狀的矽基板。基板10具有相對的第一表面10a和第二表面10b。第一鈍化層11沉積在基板10的第一表面10a上。第一鈍化層11可以包含介電層。例如，第一鈍化層11可以包含氮化矽、氧化矽、氮氧化矽、聚醯亞胺或其任何組合。
如第2圖所示，利用光學微影、機械鑽孔、雷射鑽孔、反應離子蝕刻(RIE)或其組合，形成完全貫通第一鈍化層11的複數個溝槽110，各溝槽110並延伸進入基板10。各溝槽110從第一表面10a部分深入基板10的厚度，但各溝槽110不貫穿基板10。根據本發明一實施例，例如，各溝槽110的深度不超過50微米。
根據本發明一實施例，溝槽110可以具有相同的寬度。根據本發明另一實施例，溝槽110可以具有不同的寬度。
隨後，如第3圖所示，於溝槽110中填入一導電材料，從而形成金屬介層結構112。導電材料可包含銅、鉻、鎳、鋁、金、銀、鎢、鈦或氮化鈦，但不限於此。導電材料可透過使用電解電鍍、無電電鍍、蒸發、濺射、印刷或其他合適的金屬沉積製程來形成。
根據本發明一實施例，導電材料完全填滿溝槽110。導電材料可具有包含例如黏著層、一阻障金屬、一晶種層、一溼潤層或以上組合的多層結構。根據本發明一實施例，在基板10和填入到溝槽110中的導電材料之間不形成介電襯層。
應理解的是，在沉積導電材料之後，可以透過化學機械研磨(CMP)方法去除或平坦化第一鈍化層11上多餘的導電材料。在CMP之後，顯露第一鈍化層11的上表面。
隨後，如第4圖所示，於第一鈍化層11上形成重佈線層(RDL)結構20。根據本發明的實施例，RDL結構20可以包含至少一個介電層201和至少一個繞線層202。應理解的是，RDL結構20可以包含多層介電材料和多層繞線層，如第4圖所示。
根據本發明一實施例，介電層201可包含聚醯亞胺、苯環丁烯(BCB)等。根據本發明另一實施例，介電層201可包含氧化矽、氮化矽、氮氧化矽，但不限於此。繞線層202可以包含銅、鋁或合適的金屬合金，但不限於此。繞線層202可以具有細間距鑲嵌佈線結構，例如銅鑲嵌結構。
根據本發明一實施例，多個凸塊接墊204可形成在RDL結構20中並電連接至繞線層202。根據本發明一實施例，金屬介層結構112電連接至繞線層202。
根據本發明一實施例，於重佈線層結構20上形成一第二鈍化層21。 分別透過於第二鈍化層21中的開孔210顯露出凸塊接墊204。根據本發明一實施例，第二鈍化層21可以包含介電層，但不限於此。例如，第二鈍化層21可以包含氮化矽、氧化矽、氮氧化矽、聚醯亞胺或以上組合。根據本發明另一實施例，第二鈍化層21可以包含防焊層，但不限於此。
在各凸塊接墊204上形成複數個第一金屬柱320，例如微凸塊等。根據本發明一實施例，各第一金屬柱320可包含凸塊下金屬結構320a和覆蓋在凸塊下金屬結構320a上的導電凸塊320b。導電凸塊320b可以包含一焊錫凸塊或一金屬凸塊。例如，第一金屬柱320可具有一凸塊間距，其與半導體晶片的主動面上的輸入/輸出(I/O)墊間距相匹配。例如，第一金屬柱320可以包含銅、金或任何合適的金屬。可理解的是，第一金屬柱320可另包含金屬處理層和形成在第一金屬柱320上的焊料蓋(未明確示出)。
如第5圖所示，進行一晶片貼合製程，於第一金屬柱320上安置至少一第一半導體晶片101及至少一第二半導體晶片102。第一半導體晶片101和第二半導體晶片102可以是覆晶晶片，其主動面面向下朝向第一金屬柱320。第一半導體晶片101和第二半導體晶片102透過第一金屬柱320電連接至RDL結構20。
儘管在第5圖中未繪示，但是應當理解，在第一半導體晶片101和第二半導體晶片102上的對應接合焊墊上以形成有微凸塊。當第一半導體晶片101和第二半導體晶片102與RDL結構20接合時，使第一半導體晶片101和第二半導體晶片102上對應接合焊墊上的微凸塊與複數個第一金屬柱320對準。
第一半導體晶片101和第二半導體晶片102是具有一些功能的主動積 體電路晶片，例如GPU(圖形處理單元)、CPU(中央處理單元)、記憶體晶片等。根據本發明一實施例，第一半導體晶片101和第二半導體晶片102可以一起設置在同一封裝中，並且可以是具有特定功能的不同晶片。另外，可以選擇在各晶片下方使用底膠(圖未示)。
如第6圖所示，形成一成型模料400覆蓋第一半導體晶片101、第二半導體晶片102和第二鈍化層21的上表面。隨後，可以對成型模料400進行一固化處理。根據本發明一實施例，成型模料400可以包含環氧樹脂和二氧化矽填料的混合物，但不限於此。
後續，可選擇研磨成型模料400的上部，使第一半導體晶片101及第二半導體晶片102的被動面被顯露出來，且與成型模料400的一表面400a共平面。
如第7圖所示，在形成成型模料400之後，對基板10進行一基板薄化製程，移除部分厚度的該基板。例如，可以對基板10的第二表面10b進行研磨製程以移除基板10的大部分厚度。在研磨製程完成之後，基板10的剩餘部分仍然覆蓋金屬介層結構112且金屬介層結構112在此時不會被顯露出來。
如第8圖所示，在基板薄化製程之後，進行一矽濕式回蝕刻製程，移除基板10的剩餘部分，以顯露出第一鈍化層11及各金屬介層結構112的突出部分。在RDL結構20的底側(或PCB側)，金屬介層結構112的突出部分構成第二金屬柱112a。根據本發明一實施例，第二金屬柱112a可以為凸塊下金屬(UBM)凸塊。
或者，可在完成基板薄化製程之後暴露出金屬介層結構112。在這種情況下，可以省略前述的矽濕式回蝕刻製程。
如第9圖所示，複數個連接件620分別直接形成在各第二金屬柱112a上。複數個連接件620可包含焊錫凸塊或C4凸塊。連接件620可包含金、銀、銅、鎳、鎢、錫或以上組合。連接件620可具有與封裝基板或印刷電路板(PCB)的墊間距相匹配的凸塊間距。隨後，進行一切割製程以將各半導體封裝彼此分離。
根據本發明一實施例，連接件620可以透過電鍍或落球法形成在第二金屬柱112a上，但不限於此。根據本發明另一實施例，連接件620可以僅形成在各第二金屬柱112a的上表面上。
本發明的方法的優點在於，連接件620的形成不涉及光學微影製程，因此可以避免晶圓級組件翹曲而導致的開口對不準問題，如此改善封裝製程餘裕及封裝製程良率。
此外，本發明的一個技術特徵在於，用於在PCB側上形成焊錫凸塊或C4凸塊的第二金屬柱112a及第一金屬柱320是在去除基板10之前就已經製作完成。
第10圖至第20圖係根據本發明的另一實施例所繪示的製作半導體封裝的示例性方法的剖面圖，其中相同的元件符號表示相同的元件、層或區域。第10圖至第13圖說明製作薄重佈線中介層結構的示例性方法。
首先，同樣地，如第10圖所示，提供一基板10。根據本發明一實施例，基板10可以包含矽或III-V半導體，但不限於此。例如，根據本發明一實施例，基板10可以是晶圓形狀的矽基板。基板10具有相對的第一表面10a和第二表面10b。第一鈍化層11沉積在基板10的第一表面10a上。第一鈍化層11可以包含介電層。例如，第一鈍化層11可以包含氮化矽、氧化矽、氮氧化矽、聚醯亞胺或其任何組合。
如第11圖所示，利用光學微影、機械鑽孔、雷射鑽孔、反應離子蝕刻(RIE)或其組合，形成完全貫通第一鈍化層11的複數個溝槽110，各溝槽110並延伸進入基板10。各溝槽110從第一表面10a部分深入基板10的厚度，但各溝槽110不貫穿基板10。根據本發明一實施例，例如，各溝槽110的深度不超過50微米。根據本發明另一實施例，溝槽110可以具有不同的寬度。
隨後，如第12圖所示，於溝槽110中填入一導電材料，從而形成金屬介層結構122。導電材料可包含銅、鉻、鎳、鋁、金、銀、鎢、鈦或氮化鈦，但不限於此。導電材料可透過使用電解電鍍、無電電鍍、蒸發、濺射、印刷或其他合適的金屬沉積製程來形成。根據本發明一實施例，導電材料完全填滿溝槽110。
應理解的是，在沉積導電材料之後，可以透過化學機械研磨(CMP)方法去除或平坦化第一鈍化層11上多餘的導電材料。在CMP之後，顯露第一鈍化層11的上表面。
隨後，如第13圖所示，於第一鈍化層11上形成重佈線層(RDL)結構20。根據本發明的實施例，RDL結構20可以包含至少一個介電層201和至少一個繞線層202。應理解的是，RDL結構20可以包含多層介電材料和多層繞線層，如第13圖所示。
根據本發明一實施例，介電層201可包含聚醯亞胺、苯環丁烯(BCB)等。根據本發明另一實施例，介電層201可包含氧化矽、氮化矽、氮氧化矽，但不限於此。繞線層202可以包含銅、鋁或合適的金屬合金，但不限於此。繞線層202可以具有細間距鑲嵌佈線結構，例如銅鑲嵌結構。
根據本發明一實施例，多個凸塊接墊204可形成在RDL結構20中並電連接至繞線層202。根據本發明一實施例，金屬介層結構122電連接至繞線層202。
根據本發明一實施例，於重佈線層結構20上形成一第二鈍化層21。分別透過於第二鈍化層21中的開孔210顯露出凸塊接墊204。根據本發明一實施例，第二鈍化層21可以包含介電層，但不限於此。例如，第二鈍化層21可以包含氮化矽、氧化矽、氮氧化矽、聚醯亞胺或以上組合。根據本發明另一實施例，第二鈍化層21可以包含防焊層，但不限於此。
在各凸塊接墊204上形成複數個第一金屬柱322。例如，第一金屬柱322可以作為用於著陸焊錫凸塊或錫球的UBM凸塊，且可具有與封裝基板或印刷電路板(PCB)的墊間距相匹配的凸塊間距。例如，第一金屬柱322可以包含銅、鉻、鎳、鋁、金、銀、鎢、鈦或氮化鈦，或任何合適的金屬。
根據本發明一實施例，第一金屬柱322可以從第二鈍化層21的上表面突出。
如第14圖所示，進行一載板接合製程。載板40可以透過使用黏著層42接合到RDL結構20上。載板40可以是玻璃基板、金屬片或矽基板，但不限於此。
如第15圖所示，在進行一載板接合製程之後，對基板10進行一基板薄化製程，移除部分厚度的該基板。例如，可以對基板10的第二表面10b進行研磨製程以移除基板10的大部分厚度。在研磨製程完成之後，基板10的剩餘部分仍然覆蓋金屬介層結構122且金屬介層結構122在此時不會被顯露出來。
如第16圖所示，在基板薄化製程之後，進行一矽濕式回蝕刻製程，移除基板10的剩餘部分，以顯露出第一鈍化層11及各金屬介層結構122的突出部分。在RDL結構20的底側(或晶片側)，金屬介層結構122的突出部分構成第二金屬柱122a。根據本發明一實施例，第二金屬柱122a可以用於連接到晶片的微凸塊。
或者，可在完成基板薄化製程之後暴露出金屬介層結構122。在這種情況下，可以省略前述的矽濕式回蝕刻製程。
如第17圖所示，隨後，進行一晶片貼合製程，於第二金屬柱122a上安置至少一第一半導體晶片101及至少一第二半導體晶片102。第一半導體晶片101和第二半導體晶片102可以是覆晶晶片，其主動面面向下朝向第二金屬柱122a。第一半導體晶片101和第二半導體晶片102透過第二金屬柱122a電連接至 RDL結構20。
第一半導體晶片101和第二半導體晶片102是具有一些功能的主動積體電路晶片，例如GPU(圖形處理單元)、CPU(中央處理單元)、記憶體晶片等。根據本發明一實施例，第一半導體晶片101和第二半導體晶片102可以一起設置在同一封裝中，並且可以是具有特定功能的不同晶片。另外，可以選擇在各晶片下方使用底膠(圖未示)。
如第18圖所示，形成一成型模料400覆蓋第一半導體晶片101、第二半導體晶片102和第一鈍化層11的上表面。隨後，可以對成型模料400進行一固化處理。根據本發明一實施例，成型模料400可以包含環氧樹脂和二氧化矽填料的混合物，但不限於此。
後續，可選擇研磨成型模料400的上部，使第一半導體晶片101及第二半導體晶片102的被動面被顯露出來，且與成型模料400的一表面400a共平面。
如第19圖所示，在形成成型模料400之後，去除載板40和黏著層42，從來顯露出第一金屬柱322和第二鈍化層21。
如第20圖所示，複數個連接件622分別直接形成在各第一金屬柱322上。複數個連接件622可包含焊錫凸塊或C4凸塊。連接件622可包含金、銀、銅、鎳、鎢、錫或以上組合。隨後，進行一切割製程以將各半導體封裝彼此分離。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等 變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (18)

  1. 一種用於製作一半導體裝置封裝的方法，其包含：提供一基板，其包含相對的一第一表面及一第二表面；形成金屬介層結構，其等延伸進入該基板的該第一表面，其中形成該金屬介層結構包括：在該基板之該第一表面上形成一第一鈍化層；形成複數個溝槽，其等貫通該第一鈍化層並部分穿過該基板；以及於該複數個溝槽中填入一導電材料；於該基板上形成一重佈線層(RDL)結構，使其電連接該等金屬介層結構；於該RDL結構上形成第一金屬柱；進行一晶片貼合製程，以在該等第一金屬柱上安置半導體晶片(die)；去除該基板以顯露出該等金屬介層結構的突出部分，以構成第二金屬柱，其中去除該基板以顯露出該等金屬介層結構的該等突出部分包含：對該基板進行一基板薄化製程，以移除該基板之一部分；以及進行一濕式回蝕刻製程，以移除該基板的一剩餘部分，以顯露出該第一鈍化層及該等金屬介層結構之每一者的該突出部分；以及於該等第二金屬柱上形成連接件。
  2. 如申請專利範圍第1項所述的方法，其進一步包含將該等溝槽之每一者形成為一深度，該深度不超過50微米。
  3. 如申請專利範圍第1項所述的方法，其進一步包含將該等溝槽形成為實質相同的寬度。
  4. 如申請專利範圍第1項所述的方法，其進一步包含將該等溝槽形成為不同的寬度。
  5. 如申請專利範圍第1項所述的方法，其中於該等溝槽中填入該導電材料包含於該等溝槽中填入銅、鉻、鎳、鋁、金、銀、鎢、鈦或氮化鈦。
  6. 如申請專利範圍第1項所述的方法，其中於該等溝槽中填入該導電材料包含在該等溝槽中形成一多層結構，該多層結構包含一黏著層、一阻障層、一晶種層、一溼潤層或以上組合。
  7. 如申請專利範圍第1項所述的方法，其中於該RDL結構上形成該等第一金屬柱包含：於該RDL結構上形成一第二鈍化層；於該第二鈍化層中形成接墊開孔，以顯露出該RDL結構的凸塊接墊；以及於該等凸塊接墊上各別形成該等第一金屬柱。
  8. 如申請專利範圍第7項所述的方法，其中形成該第一鈍化層及該第二鈍化層包含自氮化矽、氧化矽、氮氧化矽、聚醯亞胺或以上組合形成。
  9. 如申請專利範圍第1項所述的方法，其中提供該基板包含提供一矽基板。
  10. 如申請專利範圍第1項所述的方法，其進一步包含：形成一成型模料，以覆蓋該等半導體晶片及該第一鈍化層；以及研磨該成型模料，以顯露該等半導體晶片的被動面，其中該成型模料之一表面與該等被動面共平面。
  11. 如申請專利範圍第1項所述的方法，其中該等第一金屬柱形成為微凸塊(micro-bump)，且該等第二金屬柱形成為凸塊下金屬(UBM)凸塊。
  12. 如申請專利範圍第11項所述的方法，其中形成該等第一金屬柱包含形成一UBM結構及形成蓋在該UBM結構上的一導電凸塊。
  13. 如申請專利範圍第12項所述的方法，其中形成該導電凸塊包含形成一焊錫凸塊或一金屬凸塊。
  14. 如申請專利範圍第1項所述的方法，其中形成該等連接件包含形成焊錫凸塊或C4凸塊。
  15. 一種用於製作一半導體封裝的方法，其包含：提供一基板，其包含相對的一第一表面及一第二表面；在該基板的該第一表面上形成一第一鈍化層及金屬介層結構，其中該等金屬介層結構延伸進入該基板的該第一表面；於該基板上形成一重佈線層(RDL)結構，使其電連接該等金屬介層結構；於該RDL結構上形成一第二鈍化層及第一金屬柱；將一載板貼合至該RDL結構；去除該基板以顯露出該等金屬介層結構的突出部分，以構成第二金屬柱；於該等第二金屬柱上接合半導體晶片；移除該載板，以顯露出該等第一金屬柱及該第二鈍化層；以及於該等第一金屬柱上形成連接件。
  16. 如申請專利範圍第15項所述的方法，其中所述去除該基板以顯露出該等金屬介層結構的該等突出部分包含：對該基板進行一基板薄化製程，以移除該基板之一部分；以及進行一濕式回蝕刻製程，以移除該基板的一剩餘部分，以顯露出該第一鈍化層及各金屬介層結構的該突出部分。
  17. 如申請專利範圍第16項所述的方法，其進一步包含：形成一成型模料，以覆蓋該等半導體晶片及該第一鈍化層；以及研磨該成型模料，以顯露該等半導體晶片的被動面，其中該成型模料之一表面與該等被動面共平面。
  18. 如申請專利範圍第15項所述的方法，其中該第一金屬柱形成為UBM凸塊，且該第二金屬柱形成為微凸塊。
TW106104555A 2016-11-03 2017-02-13 半導體封裝及其製作方法 TWI628762B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/342,124 2016-11-03
US15/342,124 US9922845B1 (en) 2016-11-03 2016-11-03 Semiconductor package and fabrication method thereof

Publications (2)

Publication Number Publication Date
TW201818520A TW201818520A (zh) 2018-05-16
TWI628762B true TWI628762B (zh) 2018-07-01

Family

ID=61598678

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106104555A TWI628762B (zh) 2016-11-03 2017-02-13 半導體封裝及其製作方法

Country Status (3)

Country Link
US (1) US9922845B1 (zh)
CN (1) CN108022871B (zh)
TW (1) TWI628762B (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10784219B2 (en) * 2017-11-30 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing
US10699980B2 (en) 2018-03-28 2020-06-30 Intel IP Corporation Fan out package with integrated peripheral devices and methods
US10515920B2 (en) * 2018-04-09 2019-12-24 Google Llc High bandwidth memory package for high performance processors
US10999939B2 (en) 2018-06-08 2021-05-04 Unimicron Technology Corp. Circuit carrier board and manufacturing method thereof
US20190385962A1 (en) * 2018-06-15 2019-12-19 Texas Instruments Incorporated Semiconductor structure and method for wafer scale chip package
US10573572B2 (en) * 2018-07-19 2020-02-25 Advanced Semiconductor Engineering, Inc. Electronic device and method for manufacturing a semiconductor package structure
KR102530754B1 (ko) * 2018-08-24 2023-05-10 삼성전자주식회사 재배선층을 갖는 반도체 패키지 제조 방법
CN113228268B (zh) * 2018-12-29 2023-09-29 华为技术有限公司 芯片封装结构、电子设备、芯片封装方法以及封装设备
US11063146B2 (en) 2019-01-10 2021-07-13 Texas Instruments Incorporated Back-to-back power field-effect transistors with associated current sensors
KR102551352B1 (ko) 2019-06-28 2023-07-04 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
CN110739292A (zh) * 2019-09-02 2020-01-31 上海先方半导体有限公司 一种3d封装结构及其制作方法
KR102615198B1 (ko) 2019-10-15 2023-12-18 삼성전자주식회사 반도체 패키지
KR20220022762A (ko) 2020-08-19 2022-02-28 삼성전자주식회사 반도체 패키지
CN113078149B (zh) * 2021-03-12 2023-11-10 上海易卜半导体有限公司 半导体封装结构、方法、器件和电子产品
CN113097201B (zh) * 2021-04-01 2023-10-27 上海易卜半导体有限公司 半导体封装结构、方法、器件和电子产品
US20220336335A1 (en) * 2021-04-16 2022-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package having multiple substrates
TWI823582B (zh) * 2022-09-22 2023-11-21 頎邦科技股份有限公司 具黏合層之封裝結構及其封裝方法
CN116153795A (zh) * 2023-04-20 2023-05-23 广东赛昉科技有限公司 一种多芯片封装方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201108367A (en) * 2009-08-18 2011-03-01 Unimicron Technology Corp Coreless package substrate and method of forming the same
TW201322388A (zh) * 2011-11-30 2013-06-01 Taiwan Semiconductor Mfg 晶片封裝及其形成方法及基板及形成複數個凸塊結構於基板上的方法
TW201413887A (zh) * 2012-09-26 2014-04-01 Unimicron Technology Corp 封裝基板與封裝結構之製法
TW201417235A (zh) * 2012-10-30 2014-05-01 矽品精密工業股份有限公司 封裝結構及其製法
TW201428919A (zh) * 2013-01-04 2014-07-16 Taiwan Semiconductor Mfg 裝置
TW201448068A (zh) * 2013-06-03 2014-12-16 Powertech Technology Inc 矽穿孔底部形成凸塊之製程與結構
TW201618256A (zh) * 2014-11-12 2016-05-16 矽品精密工業股份有限公司 半導體封裝結構及其製法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5147779B2 (ja) * 2009-04-16 2013-02-20 新光電気工業株式会社 配線基板の製造方法及び半導体パッケージの製造方法
US10297550B2 (en) * 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US8928159B2 (en) * 2010-09-02 2015-01-06 Taiwan Semiconductor Manufacturing & Company, Ltd. Alignment marks in substrate having through-substrate via (TSV)
US8698303B2 (en) * 2010-11-23 2014-04-15 Ibiden Co., Ltd. Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
US8871568B2 (en) * 2012-01-06 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and method of forming the same
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR102078848B1 (ko) * 2013-03-15 2020-02-18 삼성전자 주식회사 멀티 칩 적층 패키지들을 제조하는 방법
KR102077153B1 (ko) * 2013-06-21 2020-02-14 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
US20150262902A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9449935B1 (en) * 2015-07-27 2016-09-20 Inotera Memories, Inc. Wafer level package and fabrication method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201108367A (en) * 2009-08-18 2011-03-01 Unimicron Technology Corp Coreless package substrate and method of forming the same
TW201322388A (zh) * 2011-11-30 2013-06-01 Taiwan Semiconductor Mfg 晶片封裝及其形成方法及基板及形成複數個凸塊結構於基板上的方法
TW201413887A (zh) * 2012-09-26 2014-04-01 Unimicron Technology Corp 封裝基板與封裝結構之製法
TW201417235A (zh) * 2012-10-30 2014-05-01 矽品精密工業股份有限公司 封裝結構及其製法
TW201428919A (zh) * 2013-01-04 2014-07-16 Taiwan Semiconductor Mfg 裝置
TW201448068A (zh) * 2013-06-03 2014-12-16 Powertech Technology Inc 矽穿孔底部形成凸塊之製程與結構
TW201618256A (zh) * 2014-11-12 2016-05-16 矽品精密工業股份有限公司 半導體封裝結構及其製法

Also Published As

Publication number Publication date
CN108022871B (zh) 2019-04-12
CN108022871A (zh) 2018-05-11
US9922845B1 (en) 2018-03-20
TW201818520A (zh) 2018-05-16

Similar Documents

Publication Publication Date Title
TWI628762B (zh) 半導體封裝及其製作方法
US10665474B2 (en) 3D packages and methods for forming the same
CN110634847B (zh) 半导体器件和方法
US8669174B2 (en) Multi-die stacking using bumps with different sizes
US11063022B2 (en) Package and manufacturing method of reconstructed wafer
TW201916304A (zh) 半導體封裝
KR102401309B1 (ko) 반도체 디바이스 및 그를 형성하는 방법
US11145562B2 (en) Package structure and method of manufacturing the same
TWI719730B (zh) 積體電路封裝及其製作方法
US20210320097A1 (en) Integrated circuit package and method of forming same
US11699638B2 (en) Package and manufacturing method thereof
US11164824B2 (en) Package structure and method of fabricating the same
US11443993B2 (en) Chip package structure with cavity in interposer
TW202109790A (zh) 封裝
US11705343B2 (en) Integrated circuit package and method of forming thereof
CN111128933B (zh) 半导体封装件及其形成方法
US20220230969A1 (en) Package structure and method of fabricating the same
CN117650063A (zh) 集成电路器件的形成方法
TW202306066A (zh) 積體電路元件和其形成方法
US11810830B2 (en) Chip package structure with cavity in interposer
CN220692015U (zh) 半导体装置
TWI727483B (zh) 封裝及其製造方法