TW201322388A - 晶片封裝及其形成方法及基板及形成複數個凸塊結構於基板上的方法 - Google Patents

晶片封裝及其形成方法及基板及形成複數個凸塊結構於基板上的方法 Download PDF

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TW201322388A
TW201322388A TW101122587A TW101122587A TW201322388A TW 201322388 A TW201322388 A TW 201322388A TW 101122587 A TW101122587 A TW 101122587A TW 101122587 A TW101122587 A TW 101122587A TW 201322388 A TW201322388 A TW 201322388A
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Taiwan
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substrate
wafer
bump
layer
bump structures
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TW101122587A
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English (en)
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TWI540694B (zh
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Jing-Cheng Lin
Po-Hao Tsai
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Taiwan Semiconductor Mfg
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Abstract

形成凸塊結構的機制會降低晶片與封裝基板之間間距的變異。藉由平坦化晶片及/或基板上的凸塊上的焊層，而達到控制凸塊結構的高度將晶粒中及晶圓中位置、圖案密度、晶粒尺寸、及製程變異而造成的變異最小化。如此一來，晶片與基板之間的間距可控制均勻以增進底膠的品質。

Description

晶片封裝及其形成方法及基板及形成複數個凸塊結構於基板上的方法
本發明係有關一種晶片封裝及其形成方法，特別是一種形成複數個凸塊結構的晶片封裝。
現代電路製程通常包括數個步驟。首先在包括數個重複半導體晶片的半導體晶圓上製作積體電路，其中每個半導體晶片都包括積體電路。接著從晶圓切割出半導體晶片並封裝該些半導體晶片。封裝製程具有兩個主要目的：保護脆弱的半導體晶片；以及連接內部積體電路至外部連接。
在封裝製程中，藉由覆晶接合將半導體晶粒(或晶片)置於一封裝元件上。將一底膠填入半導體晶粒與封裝元件之間的間隙，以避免凸塊或焊球中的焊料產生裂縫，其中裂縫通常是由於熱應力而造成。底膠也減少了介電界面的脫層。封裝元件為一中介板(interposer)，其中中介板包括用以在相反側之間傳送電信訊號的金屬連線。晶粒是藉由直接金屬接合、焊料接合等方式被接合至中介板。封裝元件也可為其他種類的基板。晶粒封裝仍存在許多挑戰。
本發明係有關一種晶片封裝，包括：複數個凸塊結構，於該晶片封裝的一第一晶片與一基板之間；及一位於該複數個凸塊結構中且靠近該第一晶片中心的焊層比另一位於該複數個凸塊結構中且靠近該第一晶片邊緣的焊層更厚。
本發明亦有關一種基板，包括：複數個凸塊結構，每一個凸塊結構包括：一焊層；一銅層；及一金屬層，其中 該金屬層位於該焊層與該銅層之間，其中一位於該複數個凸塊結構中且靠近該第一晶片中心的焊層比另一位於該複數個凸塊結構中且靠近該第一晶片邊緣的焊層更厚。
本發明更有關一種形成複數個凸塊結構於一基板上的方法，包括：形成一凸塊下金屬層於該基板上，其中該凸塊下金屬層接觸該基板上的金屬墊；形成一光阻層於該凸塊下金屬層上方，其中該光阻層定義用以形成該複數個凸塊結構的開口；鍍複數個金屬層於該些開口中，其中該些金屬層為該複數個凸塊結構的部份；及在該些金屬層被鍍到距離該基板表面一目標高度之後，平坦化該複數個凸塊結構。
本發明還有關一種晶片封裝的形成方法，包括：提供一第一晶片，其具有一第一複數個凸塊結構，其中該第一複數個凸塊結構被平坦化至第一高度；提供一具有一第二複數個凸塊結構的基板，其中該第二複數個凸塊結構被平坦化至第二高度；及接合該第一及第二複數個凸塊結構，其中該第一晶片與該基板之間的間距為一數值。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
將在以下詳細討論本揭露實施例的組成及使用。應能理解的是實施例提供許多發明概念已實施在多種特定情況。在此討論的特定實施例僅為說明用且不對本揭露之範疇有限定性。
第1圖顯示根據一些實施例之晶片封裝100、100＊的剖面示意圖，其中晶片封裝100具有位於一基板30上的積體電路晶粒50，且晶片封裝100＊具有位於一基板30＊上的積體電路晶粒50＊。封裝100與封裝100＊相似，其中基板30、30＊相似，且積體電路晶粒50、積體電路晶粒50＊相似。在一些實施例中，基板30及30＊為半導體晶圓、或者晶圓的一些部分。在一些實施例中，基板30及30＊包括矽、砷化鎵、絕緣體上覆矽、或其他相似材料。在一些實施例中，基板30及30＊也包括被動裝置，例如電阻、電容、電感器等，或也包括主動裝置，例如電晶體。在一些範例實施例中，基板30及30＊包括額外的積體電路。在一些實施例中，基板30及30＊包括基板穿孔(through substrate via)35及35＊，如第1圖所示。在一些實施例中，基板30及30＊為中介板。再者，在替代實施例中，基板30及30＊為其他材料製成。舉例來說，在一些實施例中，是使用多層電路板。在一些實施例中，基板30及30＊也包括BT(bismaleimide triazine,BT)樹脂、FR-4(一種由防火環氧樹脂黏結劑與玻璃纖維布組成的複合材料)、陶瓷、玻璃、塑膠、膠帶、薄膜、或其他可承載導電墊(pad or land)的支撐材料，其中導電墊為覆晶積體電路晶粒50及50＊接收連接端點15及15＊所需的。
第1圖顯示積體電路晶粒50到基板30的接合是藉由將積體電路晶粒50上的凸塊51連接到基板30上的凸塊31。類似地，積體電路晶粒50＊到基板30＊的接合是藉由將積體電路晶粒50＊上的凸塊51＊連接到基板30＊上的凸塊 31＊。以底膠(underfill)55填入晶粒50與基板30之間的空間。相似地，以底膠55＊填入晶粒50＊與基板30＊之間的空間。底膠55＊是由一底膠材料製成且大抵填入積體電路晶粒50＊與基板30＊之間所有的空間。在一些實施例中，底膠55＊具有連續且漸縮的輪廓(profiles)。如上所述，底膠55＊為積體電路晶粒50＊提供支撐且避免凸塊結構31＊與51＊之間的連接焊料(joint solder)53＊產生裂縫。積體電路晶粒50＊與基板30＊之間的距離H1 ＊被稱為「間距」(standoff)。
相反地，底膠55並不填入積體電路晶粒50與基板30之間的空間，且積體電路晶粒50與基板30之間留有一空隙(void)54及一填角料(fillet)56，其中填角料56為空隙下底膠的一延伸填角料。空隙54會降低底膠55避免焊料產生裂縫的效果，其中焊料為例如接近空隙54的焊料53。填角料56容易從剩下的底膠55脫離，而這可能會更加弱化及損害底膠55。底膠55之所以不正確地形成是因為積體電路晶粒50與基板30之間間距H1比積體電路晶粒50＊與基板30＊之間間距H1 ＊更高而造成。
使用同樣的底膠製程於封裝100及100＊。底膠製程使用一具有固定體積V的底膠材料。具有較高間距H1的封裝使具有固定體積V的底膠材料不夠填入積體電路晶粒50與基板30之間，而形成空隙54。具有較小間距的封裝具有多餘底膠，其中多餘底膠形成大的填角料56，而大的填角料會影響鄰近晶粒底膠的正確形成。因此，控制封裝晶粒間距對於得到良好晶片封裝良率及足夠耐用的晶片封裝為重要的。
第2A圖顯示根據一些實施例之一具有基板210的凸塊結構200。在一些實施例中，基板210為一半導體基板，例如塊狀矽基板，雖然基板210可包括其他半導體材料，例如第III族、第IV族、及/或第V族元素。在一些實施例中，半導體裝置214，例如電晶體，形成於基板210的表面。一內連線結構212形成於基板210上，其中內連線結構212包括形成於其中且連接至半導體裝置214的金屬走線及導孔(未繪示)。在一些實施例中，金屬走線及導孔是由銅或銅合金製成並經由一習知鑲嵌製程形成。在一些實施例中，內連接結構212包括習知的層間介電及金屬間介電。
一金屬墊228形成於內連接結構212上方。在一些實施例中，金屬墊228包括鋁，且因此被稱作鋁墊228。在其他實施例中，金屬墊是由其它材料製成或者包括其他材料，而其他材料為例如銅、銀、金、鎳、鎢、上述之合金、及/或上述之多層。在一些實施例中，金屬墊228電性連接至半導體裝置214，例如藉由其下的內連線結構212。在一些實施例中，形成一保護層230以覆蓋金屬墊228的邊緣部份。在一些實施例中，保護層230為聚亞醯胺或其他已知介電材料。在一些實施例中，額外的保護層形成於內連線結構212上方且與金屬墊228位於同樣高度或者在金屬墊228上方。在一些實施例中，額外的保護層為例如氧化矽、氮化矽、未摻雜矽酸鹽玻璃(un-doped silicate glass,USG)、聚亞醯胺、及/或上述之多層。
於保護層230中形成一開口，暴露出金屬墊228。一 擴散阻障層240及一薄的晶種層242覆蓋該開口，且擴散阻障層240接觸薄的晶種層242。在一些實施例中，擴散阻障層240為一鈦層，一氮化鈦層、一鉭層、或一氮化鉭層。在一些實施例中，晶種層242的材料包括銅或銅合金，且因此在之後將晶種層242稱為銅晶種層。在一些實施例中，銅晶種層包括其他金屬，例如銀、金、鋁、及上述之組合。在一些實施例中，使用濺鍍形成擴散阻障層240及銅晶種層242。擴散阻障層240與薄晶種層242的組合被稱為一凸塊下金屬層245。
根據一些實施例，在銅晶種層242上方有一罩幕使銅層250被鍍在銅晶種層242暴露出的表面上。在一些實施例中，一額外的金屬層252位於銅層250上。在一些實施例中，金屬層252為一含鎳層，其包括例如一鎳層或一鎳合金層。一焊層260位於鎳層252上。在一些實施例中，焊層260為無鉛預焊(lead-free pre-solder)層，其為例如錫-銀(SnAg)或一包括錫、鉛、銀、銅、鎳、鉍、或上述合金之焊料製成。
移除罩幕而暴露出銅晶種層242於罩幕下的部份。銅晶種層242暴露出的部份接著以一蝕刻製程被移除。接著，擴散阻障層240暴露出的部份也被移除。在第2A圖中，銅層250的厚度小於焊層260的厚度；凸塊結構被稱作焊料凸塊200。
第2B圖的元件與第2A圖的元件相似。舉例來說，基板210＊與基板210相似；內連線結構212＊與內連線結構212相似；半導體裝置214＊與半導體裝置214相似；金屬 墊228＊與金屬墊228相似；保護層230＊與保護層230相似；擴散阻障層240＊與擴散阻障層240相似；晶種層242＊與晶種層242相似；銅層250＊與銅層250相似；金屬層252＊與金屬層252相似；焊層260＊與焊層260。擴散阻障層240＊與薄晶種層242＊的組合被稱作凸塊下金屬層245＊。然而，根據一些實施例且如第2B圖所示，銅層250＊的厚度大於焊層260＊的厚度，凸塊結構被稱作銅柱(post or pillar)凸塊結構200＊。
第2A及2B圖所示的實施例僅為範例；亦有可能為其他凸塊實施例。凸塊形成製程的進一步細節可參見2010年7月23號提出申請的美國專利申請案No.12/842,617之中，其名稱為「避免在凸塊形成製程中凸塊下金屬的氧化」，以及2010年7月29號提出申請的美國專利申請案No.12/846,353，其名稱為「銅柱的形成機制」(Mechanisms for forming copper pillar bumps)，在此併入以上兩篇之全文作為參考。
在一些實施例中，第2A及2B圖中的銅層250及250＊、金屬層252及252＊、及焊層260及260＊是藉由電鍍(plating)沉積。電鍍層250、262、及260所使用的電鍍製程為電化學電鍍，其會被電流密度、凸塊圖案密度、及晶片尺寸影響。第3A圖顯示根據一些實施例之積體電路晶片300的凸塊高度分佈。存在不同的凸塊高度測量區域，例如區域A、B、C、D、E、F、及G。凸塊高度測量反映了每個區域中的平均值。積體電路晶片300的凸塊在晶片300上各處相當均勻。凸塊晶片300上的凸塊高度分布顯 示晶片300的邊緣具有較高的凸塊高度而在晶片300的中心具有較低的凸塊高度。舉例來說，區域B具有約25.3微米的凸塊高度，而區域D具有約21.8微米的凸塊高度。區域B和C都接近晶粒300的邊緣。相反地，區域G接近晶片300的中心(或遠離邊緣)且具有最低的凸塊高度，其約為18.1微米。
晶圓晶片300各處電流密度的變異造成凸塊高度從積體電路晶片300的中心到邊緣具有大的變異。在邊緣的電鍍電流密度最高，且其隨著越接近晶片300的中心而減少。這是因為邊緣的周圍缺少圖案。因此在晶片邊緣的電流密度最高。再者，在靠近晶片中心的地方電鍍化學成分濃度的耗竭也是因素之一。
第3B圖顯示根據一些實施例之在完成電鍍焊層之後的晶片310。在一些實施例中，銅層250的一寬度W等於或小於約30微米。第3C圖顯示根據一些實施例之基板320具有位於金屬墊327下的矽穿孔(through silicon vias)328。根據一些實施例，基板320為一中介板。基板320也具有銅柱結構321-326，其具有一銅層250＊、一金屬層252＊、及焊層260＊。在此實施例中，銅層250＊、金屬層252＊、及焊層260＊都是藉由電鍍而沉積。基板320的銅柱結構321-326是用來接合晶片310的銅柱結構311-316。。中心到邊緣凸塊高度的變異使得接合變得困難。
如上所述，凸塊電鍍也會被晶片尺寸及凸塊密度影響。具有更大尺寸以及更高凸塊密度的晶片相較於具有更小尺寸以及更低凸塊密度的晶片具有較高的電流密度變 異。再者，對於具有較大尺寸以及更高凸塊密度的晶片來說，化學耗竭效應(chemical depletion effect)也更嚴重。因此，較大的晶片(或晶粒)及具有較高凸塊密度的晶片比起較小及具有較低凸塊密度的晶片具有更顯著的凸塊高度變異(中間至邊緣)。第3D圖根據一些實施例比較兩個晶粒的銅層250＊及焊層260＊厚度的變異。其中一個晶粒的尺寸為116平方毫米(mm2)且具有4.49%的圖案密度，而另外一個晶粒的尺寸為759平方毫米且具有19.01%的圖案密度。圖案密度被定義為一晶粒表面被圖案覆蓋的表面部份相對於總表面積的比率。第3D圖的資料顯示較大晶粒尺寸面積及圖案密度使得銅層250＊及焊層260＊厚度變異更加顯著。
除晶片中變異(within die variation)之外，晶圓各處的電鍍厚度也會變異。所電鍍的凸塊結構的厚度，比起在晶圓邊緣，在晶圓中心會較低。再者，電鍍製程隨著電鍍浴(plating bath)的新鮮度變異，並也因不同的電鍍系統而變異。上述各種因素增加間距的變異，其中間距也就是晶片之間或者晶片與基板之間的高度。研究顯示在一些情況下封裝晶片的晶圓中(within wafer)間距變異約為21微米或更高。如上所述，間距的變異造成底膠難以正確形成且造成封裝覆晶可靠度或缺陷問題。
第4A圖顯示根據一些實施例之晶片310上凸塊311-316的焊層260被平坦化以達到位於晶片310的基板表面301上的一目標凸塊高度，HT。平坦化使得焊層260的一部份被移除以控制目標凸塊高度HT。如此的平坦化減少由上述因素所造成的變異。在一些實施例中，可藉由研磨 達成平坦化。在其他實施例中，是使用其他的平坦化製程。在一些實施例中，使用一高度測量裝置以監控凸塊高度使焊層260的平坦化可被控制而達到目標高度HT。舉例來說，在一些實施例中，高度測量裝置使用共焦(confocal)或者三角測量(triangulation)高度測量方法。由於平坦化的緣故，焊層260在接近晶片310中心的高度HC比起焊層260在接近晶片310邊緣的高度HE更高。
第4B圖顯示根據一些實施例之基板320上凸塊321-326的焊層260＊被平坦化以達到位於基板320表面302上的一目標凸塊高度，HST。相似地，平坦化使得焊層260＊的一部份被移除以控制目標凸塊高度HST。如此的平坦化減少由上述因素所造成的變異。在一些實施例中，可藉由研磨達成平坦化。在其他實施例中，是使用其他的平坦化製程。在一些實施例中，使用一高度測量裝置以監控凸塊高度使焊層260＊的平坦化為可被控制而達到目標高度HST。由於平坦化的緣故，焊層260＊在接近基板320中心的高度HCC比起焊層260＊在接近晶片310邊緣的高度HEE更高。
平坦化凸塊結構的焊層，例如上述的焊層260及260＊，也減少了被電鍍焊層的表面粗糙度。研究顯示在一些情況下，非平坦化凸塊表面的粗糙度為從約442奈米至約516奈米。在平坦化製程後，表面粗糙度被減少至約3奈米至約9奈米。減少的表面粗糙度增進焊料連接界面。
第4C圖顯示根據一些實施例之晶片310的經平面化的凸塊結構被接合至基板320的凸塊結構。在一些實施例 中，對基板320實施更進一步的製程，例如研磨以暴露出矽穿孔328及形成用於外部連接的焊墊及保護層。被接合的封裝，如第4C圖所示，已經過一回焊製程以使焊層被連接在一起。由於平坦化的緣故，接近被接合封裝中心的焊層總高度HTC大於靠近晶片邊緣的焊層總高度HTE。
凸塊結構的平坦化使第4C圖所示封裝結構的間距H可被控制。平坦化移除晶粒以及晶圓各處由於製程、圖案密度、及晶粒尺寸造成的變異。舉例來說，不對焊層進行平坦化所得間距的範圍為約20-25微米。藉由對焊層進行平坦化，間距變異被減少至等於或小於約3微米。不同封裝中一致的間距使底膠能夠正確且一致地形成。
第5A圖顯示根據一些實施例之在電鍍一焊層260＊於基板上之後，一基板400的剖面示意圖。第5A圖中的凸塊450包括一銅層250＊及一金屬層252＊。在一光阻410形成於一基板400上之後，銅層250＊、金屬層252＊、及焊層260＊被鍍在基板400上。光阻410是在一擴散阻障層240＊及一薄的晶種層242＊形成於基板400上之後形成。在一些實施例中，光阻為濕式光阻或乾式光阻。如上所述，擴散阻障層240＊與薄的晶種層242＊的組合被稱作一金屬下凸塊層245＊。第5A圖中所有的層將會以相似的層元件標號敘述。如上所述，凸塊高度隨著基板400的中心到邊緣變化。
之後，實施一平坦化製程。在一些實施例中，基板400在平坦化之前被固定至一支撐工作件，使基板400在進行平坦化時能夠被固定。第5B圖顯示根據一些實施例之在平 坦化製程之後基板400的剖面示意圖。對基板400進行平坦化直到基板400具有一目標厚度HST。之後，藉由移除光阻層410及以蝕刻移除暴露出的凸塊下金屬層245。第5C圖顯示在移除光阻層410及蝕刻暴露出的凸塊下金屬層245之後的基板400之剖面示意圖。接著將支撐住基板400的工作件從基板400分離。在一些實施例中，對基板400進行背側研磨以暴露矽穿孔328及形成用以外部電性連接的結構。根據一些實施例，基板400包括複數個晶粒，且這些晶粒被切割並且從基板400分離以形成單獨的晶粒。
第5D圖顯示在覆晶接合後兩個晶片470及480。相似於上述的晶片300或310，在晶片470上實施相似的平坦化製程及凸塊形成製程。平坦化製程移除晶片470上焊層的一些部份以達到目標凸塊高度。根據一些實施例及如第5D圖所示，在基板400及晶片470兩者的凸塊結構形成及被平坦化之後，晶片470被接合至基板400。第5D圖顯示另一晶片480也被接合至基板400。在一些實施例中，晶片480相較於晶片470具有不同的尺寸及圖案密度。然而，藉由在凸塊形成中加入平坦化製程，晶片470與基板400之間的間距HA以及晶片480及基板400之間的間距HB大約相同。
在將晶片470及480置於基板400上之後，對於元件組(包括基板及晶片)進行回焊。如此一來，由晶片及基板經回焊的焊層形成之焊層265及265＊稍微被圓化。之後，將底膠490填入於晶片470、480及基板400之間的空間。在一些實施例中，實施固化(curing)以固化底膠490。由於 間距HA及HB大抵相同，底膠形成製程為可控制且可重複的。底膠490在不形成空隙或填角料的情況下正確地形成。
上述之晶片封裝範例係有關在具有凸塊結構的基板上之晶片。然而，在一些實施例中，凸塊結構的平坦化製程被應用在有關在不具有凸塊結構的基板上之晶片的晶片封裝。第5E圖顯示。晶片460被封裝於具有接觸墊491的基板490上。平坦化凸塊結構465上的焊層會控制晶片封裝495的間距KK。
凸塊結構的形成機制會降低晶片與封裝基板之間間距的變異。藉由平坦化晶片及/或基板上的凸塊上的焊層，而達到控制凸塊結構的高度以最小化由於晶粒中及晶圓中位置、圖案密度、晶粒尺寸、及製程變異而造成的變異。如此一來，晶片與基板之間的間距被控制為均勻的。結果增進了底膠的品質。
根據一些實施例，提供一種晶片封裝。晶片封裝包括複數個凸塊結構，於該晶片封裝的一第一晶片與一基板之間。晶片封裝也包括一位於該複數個凸塊結構中且靠近該第一晶片中心的焊層比另一位於該複數個凸塊結構中且靠近該第一晶片邊緣的焊層更厚。
根據一些其他的實施例，提供一種具有複數個凸塊結構的基板。基板包括一焊層；一銅層；及一金屬層。該金屬層位於該焊層與該銅層之間。一位於該複數個凸塊結構中且靠近該第一晶片中心的焊層比另一位於該複數個凸塊結構中且靠近該第一晶片邊緣的焊層更厚。
根據又一些其他實施例，提供一種形成複數個凸塊結 構於一基板上的方法。該方法包括：形成一凸塊下金屬層於該基板上，其中該凸塊下金屬層接觸該基板上的金屬墊；形成一光阻層於該凸塊下金屬層上方，其中該光阻層定義用以形成該複數個凸塊結構的開口；鍍複數個金屬層於該些開口中，其中該些金屬層為該複數個凸塊結構的部份；及在鍍該些金屬層直到距離該基板表面一目標高度之後，平坦化該複數個凸塊結構。
根據又一些其他實施例，提供一種晶片封裝的形成方法。該方法包括：提供一第一晶片，其具有一第一複數個凸塊結構，其中該第一複數個凸塊結構被平坦化至第一高度。該方法也提供一具有一第二複數個凸塊結構的基板，其中該第二複數個凸塊結構被平坦化至第二高度。該方法更包括接合該第一及第二複數個凸塊結構，其中該第一晶片與該基板之間的間距為一數值。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。再者，本說明書所敘述的製程、機器、產品、物質組成、手段、方法、及步驟之特定實施例並非用以限定本揭露的範疇。一般技藝人士已能從本揭露理解的是，可根據本揭露使用與在此敘述之相對應實施例實質執行相同功能或達到實質上相同的結果之現有的或以後發展的製程、機器、產品、物質組成、手段、方法、或步驟。因此，所附申請專利範圍並不意圖包括上述製程、機器、產品、 物質組成、手段、方法、或步驟。再者，每一項請求項組成一獨立的實施例，且各個請求項及實施例的組合落在本揭露的範疇內。
15、15＊‧‧‧連接端點
30、30＊、210、210＊、320、400‧‧‧基板
31、31＊、51、51＊、200、200＊、450‧‧‧凸塊
35、35＊‧‧‧基板穿孔
50、50＊‧‧‧積體電路晶粒
53、53＊‧‧‧焊料
54‧‧‧空隙
55、55＊、490‧‧‧底膠
56‧‧‧填角料
100、100＊‧‧‧晶片封裝
212、212＊‧‧‧內連線結構
214、214＊‧‧‧半導體裝置
228、228＊‧‧‧金屬墊
230‧‧‧保護層
240、240＊‧‧‧擴散阻障層
242、242＊‧‧‧晶種層
245、245＊‧‧‧金屬下凸塊層
250、250＊‧‧‧銅層
252、252＊‧‧‧金屬層
260、260＊、265、265＊‧‧‧焊層
300、310、460、470、480‧‧‧晶片
301、302‧‧‧表面
311-316、321-326‧‧‧銅柱結構
328‧‧‧矽穿孔
400‧‧‧基板
410‧‧‧光阻
450、465‧‧‧凸塊
495‧‧‧晶片封裝
A、B、C、D、E、F、G‧‧‧區域
H、H1、H1 ＊、HA、HB、KK‧‧‧間距
HC、HE、HT、HCC、HEE、HTC、HTE‧‧‧高度
HST‧‧‧目標厚度
V‧‧‧固定體積
第1圖顯示根據一些實施例之兩個晶片封裝，其中每個晶片封裝具有在一基板上的積體電路晶粒。
第2A及2B圖顯示根據一些實施例之兩個凸塊結構。
第3A圖顯示根據一些實施例之一積體電路晶片上的間距分佈。
第3B及3C圖顯示根據一些實施例之在一晶片及一基板上鍍焊層之後，該晶片及基板的剖面示意圖。
第3D圖根據一些實施例比較兩個晶粒的銅層及焊層厚度的變異。
第4A及4B圖顯示根據一些實施例之從凸塊結構平面化焊層。
第4C圖顯示根據一些實施例之一晶片的經平面化的凸塊結構被接合至基板的凸塊結構。
第5A-5D圖顯示根據一些實施例之一晶片封裝的準備流程圖。
第5E圖顯示根據一些實施例之一具有凸塊結構的晶片。
301‧‧‧表面
310‧‧‧晶片
311-316‧‧‧銅柱結構
HC、HE、HT‧‧‧高度
250‧‧‧銅層
252‧‧‧金屬層
260‧‧‧焊層

Claims (10)

  1. 一種晶片封裝，包括：複數個凸塊結構，於該晶片封裝的一第一晶片與一基板之間；及一位於該複數個凸塊結構中且靠近該第一晶片中心的焊層比另一位於該複數個凸塊結構中且靠近該第一晶片邊緣的焊層更厚。
  2. 如申請專利範圍第1項所述之晶片封裝，其中每一個凸塊結構包括一銅層及一金屬層，其中該金屬層位於該銅層與該焊層之間。
  3. 如申請專利範圍第1項所述之晶片封裝，其中一第二晶片藉由另一複數個凸塊結構被接合至該基板，且其中該第一晶片與該基板之間的一第一間距與該第二晶片及該基板之間的一第二間距大抵相同。
  4. 如申請專利範圍第1項所述之晶片封裝，其中該複數個凸塊結構為銅柱結構。
  5. 一種基板，包括：複數個凸塊結構，每一個凸塊結構包括：一焊層；一銅層；及一金屬層，其中該金屬層位於該焊層與該銅層之間；其中一位於該複數個凸塊結構中且靠近該第一晶片中心的焊層比另一位於該複數個凸塊結構中且靠近該第一晶片邊緣的焊層更厚。
  6. 如申請專利範圍第5項所述之基板，其中每一個焊 層被平坦化，且該複數個凸塊結構的高度大抵相同。
  7. 一種形成複數個凸塊結構於一基板上的方法，包括：形成一凸塊下金屬層於該基板上，其中該凸塊下金屬層接觸該基板上的金屬墊；形成一光阻層於該凸塊下金屬層上方，其中該光阻層定義用以形成該複數個凸塊結構的開口；鍍複數個金屬層於該些開口中，其中該些金屬層為該複數個凸塊結構的部份；及在該些金屬層被鍍到距離該基板表面一目標高度之後，平坦化該複數個凸塊結構。
  8. 一種晶片封裝的形成方法，包括：提供一第一晶片，其具有一第一複數個凸塊結構，其中該第一複數個凸塊結構被平坦化至第一高度；提供一具有一第二複數個凸塊結構的基板，其中平坦化該第二複數個凸塊結構至第二高度；及接合該第一及第二複數個凸塊結構，其中該第一晶片與該基板之間的間距為一數值。
  9. 如申請專利範圍第8項所述之晶片封裝的形成方法，更包括：以底膠填入該第一晶片與該基板之間的一空間，其中該填入並不形成一空隙或一填角料。
  10. 如申請專利範圍第8項所述之晶片封裝的形成方法，更包括：提供一第二晶片，其具有一第三複數個凸塊結構，其中平坦化該第三複數個凸塊結構至第三高度；及 接合該第三複數個凸塊結構與該基板上第二複數個凸塊結構，其中該第二晶片與該基板之間的間距大抵等於該數值。
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TWI540694B (zh) 2016-07-01
US20130134581A1 (en) 2013-05-30
US8653658B2 (en) 2014-02-18
CN103137587A (zh) 2013-06-05
CN103137587B (zh) 2016-01-27
US20140127863A1 (en) 2014-05-08

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