TWI375284B - Chip packaging structure and manufacturing process thereof - Google Patents

Description

1375284 IX. Description of the Invention: The present invention relates to a chip package structure, and more particularly to a semiconductor bonding process and a structure for making a wafer contact denser and a package structure smaller in size. [Prior Art]

With the advancement of semiconductor process technology, the density of integrated circuits has been increasing, making the processing unit and work more and more, and the speed requirements are getting faster and faster, making the production volume small, fast and high density. The components of the assembly have become a trend.

Φ〇Ά The conventional multi-chip flip chip packaging process, please refer to the first figure, 'first join the wafers 14, 16 through the plurality of bumps 12' and then fill the underfill 18 process, the process is borrowed The viscous primer 8 8 is flown into the gap between the two wafers 14 and 16 by the capillary phenomenon, and the bump i 2 is coated, and then the curing process is performed to harden the primer 18 . . However, when the process is filled with the low-viscosity primer 8, the external adhesive pad 20' which pollutes the periphery of the wafer 14 is high due to the high fluidity of the primer 18. Therefore, in order to prevent the pad 20 from being contaminated, it is connected. The pad 20 is disposed at a position away from the periphery of the wafer 14, and the design of the wafer 14 is extremely limited, and the volume of the package cannot be reduced. The shortcomings of the above-mentioned prior art have been improved in the "wafer bonding process" of the Chinese Patent No. 1 230989. However, there are still many problems in the "wafer bonding process". First, the repairing bumps used in this technology system are used. Bonding 'and such solder bumps are made by the prior art to a spherical body having a diameter of about 300 microns, and the spacing between each fresh bump is also between 300 microns, so that When the wafer is bonded (high temperature), there is sufficient structural strength support. Therefore, the distance between each joint of the package structure cannot be shortened during design, and the package volume cannot be greatly reduced. In view of the above, the present invention addresses the above problems, and proposes a wafer packaging process and its structure to effectively solve the problems of the above-mentioned prior art. SUMMARY OF THE INVENTION The main object of the present invention is to provide a chip packaging process and a structure thereof, in which a gold bump or a metal pillar is substituted for a conventional solder bump to reduce the pitch between each bump. Further, the volume of the entire flip-chip structure is greatly reduced. Another object of the present invention is to provide a wafer packaging process and a structure thereof, in which a gold bump or a metal pillar is used instead of a conventional solder bump to be mounted on a wafer. The contacts are denser and the wafers are more versatile in design, making the overall semiconductor junction structure more economical. According to the present invention, a chip packaging process includes providing a semiconductor device and a plurality of bumps, the bumps being on a semiconductor component, each bump including a gold layer; providing a circuit component; forming a rounded polymer A layer on the line component, a plurality of openings in the patterned polymer layer exposing the circuit component; bonding the patterned polymer layer and the semiconductor component, and bonding the bumps and circuit components. A chip packaging process including providing a semiconductor component and a majority of gold

a column, the metal pillar system is located on the semiconductor component, each metal pillar comprises a copper layer; a circuit component is provided; a patterned polymer layer is formed on the circuit component, and the patterned polymer layer is A plurality of openings expose the circuit components; bonding the patterned polymer layer and the semiconductor components, and bonding the metal pillars and the wiring components. The structure of the present invention comprises a semiconductor component and a circuit component. A plurality of metal pillars are disposed between the semiconductor component and the circuit component, and a polymer layer is disposed between the wafer and the circuit component to bond to the wafer and the circuit component. surface. The structure of the present invention includes a semiconductor component and a circuit component. A plurality of metal pillars are disposed between the semiconductor component and the circuit component, and the distance between the adjacent bumps is between 5 micrometers and 100 micrometers. A polymer layer is disposed between the wafer and the line component to bond to the surface of the wafer and the line component. The purpose, technical contents, features, and effects achieved by the present invention will become more apparent from the detailed description of the embodiments and the accompanying drawings. [Embodiment] The present invention is a wafer packaging process and a structure thereof, which replaces solder bumps in the prior art by using gold bumps or metal pillars, thereby greatly improving the disadvantages of excessive joint pitch in the prior art. The following are two different embodiments, one is a semiconductor junction structure and a process mainly composed of a bump containing a gold metal layer, and the other is a semiconductor junction structure and a process mainly composed of a metal pillar. 1. 1 • . 1 First Embodiment Supplement First, the first embodiment of the gold bump-based embodiment will be described. Referring to the second and third figures, the chip package structure includes a semiconductor component and a line. In this embodiment, the semiconductor device is exemplified by the semiconductor wafer 22, and the semiconductor wafer 22 is cut by a semiconductor wafer 23 to generate 'and the gold bumps are first set when the semiconductor wafer 23 is not cut. The step of cutting the semiconductor wafer 23 is performed when the gold bump is disposed on the semiconductor wafer 23, and the semiconductor wafer 22 includes the semiconductor substrate at the bottom. The substrate is in the form of a germanium substrate or a gallium arsenide substrate. (GAAS), a germanium telluride substrate, and a substrate having an epitaxial germanium on a silicon-on-insulator (SOI). In addition, the type of the line component 24 can be one of a semiconductor wafer or a substrate. If the circuit component 24 is a substrate, the circuit component is, for example, a glass substrate, a printed circuit board, a ceramic substrate, a soft board, or a glass fiber. One of the substrates. When the circuit component 24 is of a semiconductor wafer type, the material of the circuit component 24 also includes a germanium substrate, a gallium arsenide (GAAS) substrate, a germanium telluride substrate, and an epitaxial germanium on the insulating layer (silic〇n-on- The substrate of insulat〇r, s〇I), and the circuit component μ can be subjected to the step of cutting the wiring component 24 after bonding the semiconductor wafer 22. In this embodiment, the type of the wiring component 24 is a semiconductor wafer. Explain the target. The semiconductor wafer 23 as the line component 24 has a similar structure to the semiconductor wafer 23 from which the semiconductor wafer 22 can be cut, as described below, having the semiconductor wafer 23, 23 having an active surface 'on the semiconductor wafer 1375284

23, 23, the active surface is formed by doping a pentavalent or trivalent ion (such as boron ion or phosphorus ion, etc.) to form a plurality of electronic components 26, such as a metal oxide semiconductor or a transistor 'metal oxide semiconductor MOS devices, P-channel MOS devices, n-channel MOS devices, biCMOS devices, dual-load Bipolar Junction Transistor (BJT), diffusion area, resistor, capacitor, and complementary metal oxide semiconductor (CMOS). On the active surface of the semiconductor wafer 23, 23', a plurality of thin film insulating layers 28, 30, 32 and circuit layers 34, 36 are respectively disposed, wherein the thin film insulating layers 28, 30, 32 are also called dielectric layers, generally It is formed by means of chemical vapor deposition. The thin film insulating layer 28, 30, 32 is, for example, yttrium oxide, chemical vapor deposited tetraethoxy decane (TEOS) oxide, SiwCxOyHz, arsenide or oxynitride compound, or formed by spin coating. Glass (S0G), fluorinated glass (FSG), silk screen layer (SiLK), black diamond film (Black Diamond), polyarylene ether, polybenzoxazole (PBO), porous oxidized stone The thin film insulating layers 28, 30, and 32 are made of a low dielectric constant value (FPI of less than 3). In the process of forming the plurality of circuit layers 34, 36, in the damascene process, a diffusion barrier layer is first sputtered on the bottom and sidewalls of the opening of the thin film insulating layers 28, 30, 32 and the thin film insulating layer. 28, 30, 32 above Table 9 1375284

On the surface, a layer of copper, for example, a seed of copper is deposited on the diffusion barrier layer, and then a copper layer is electroplated on the seed layer, followed by chemical mechanical polishing (CMP). The copper layer, the seed layer and the diffusion barrier layer outside the openings of the thin film insulating layers 28, 30, 32 are exposed until the upper surfaces of the thin film insulating layers 28, 30, 32 are exposed. Alternatively, the carbon layer or the alloy layer may be patterned on a thin film insulating layer 28, 30, 32, followed by photolithographic etching of the aluminum or aluminum alloy layer. The wiring layer 34 and the wiring layer 36 may be connected to each other through the via holes 38 in the thin film insulating layers 28, 30, 32, or to the electronic component 26.

The thickness of the wiring layer 34 and the wiring layer 36 is generally between 0.1 micrometers and 3 micrometers. In the lithography process, the thin metal lines of the wiring layer 34 and the wiring layer 36 are fabricated using five times (5X) steppers or scanners or using a better instrument, and coated. The thickness of the photoresist layer is generally less than 5 microns. And the uppermost layer regions of the circuit layer 34 and the circuit layer 36 are respectively defined as a first pad 40 and a second pad 42, which can be used for connecting wi rebonded wires, gold bumps, tin slab bumps or films. Components such as Tape-Automated-Bonded (TAB). The maximum lateral dimension of the first pad 40 and the second pad 42 can be reduced to between 5 and 40 micrometers, and in the preferred case, for example, between 20 and 35 micrometers, thereby reducing the first pad 40. The parasitic capacitance between the second pad 42 and the underlying metal line. The first pads 40 and the second pads 42 can be electrically connected to the transistors or other electronic components 26 located on or in the surface of the semiconductor wafers 23, 23', and pass through the first pads 10 1375284 Γ * , the surface 40, the second pad 42 can electrically connect the first pad 40 and the second pad 42 to the external circuit. In this embodiment, the portion of the second pad 42 of the line component 24 will Pre-defined as an external pad 44, the external pad 44 is connected to the outside for the overall structure. A protective layer 46' is then disposed on the surface of the semiconductor wafer 23, 23' by chemical vapor deposition (CVD). The protective layer 46 has a plurality of gaps exposing the first pad 40 and the second pad 42. The protective layer 46 can protect the electronic components 26 within the semiconductor wafers 23, 23' from damage from moisture and foreign ion contamination, that is, the protective layer 46 can prevent moving ions (m〇bi le ions ) (such as sodium ions), moisture (moisture), transition metal (such as gold, silver, copper) and other impurities penetrate, and damage the transistor under the protective layer 46, polysilicon resistance Element or polycrystalline germanium - electronic component 26 of polycrystalline tantalum capacitive element or thin metal trace. In order to achieve the purpose of protection, the δ vine layer 46 is protected by osmium oxide (s丨1 ic〇n 〇χ丨 heart), oxygen oxysulfide compound, silicon nitride, and bismuth oxynitride ( SiUc〇n oxy-nitride) and so on. The first method of the protective layer 46 may be to first form a layer of germanium oxide having a thickness between 〇2 and 12 μm by a chemical vapor deposition step, and then use a chemical vapor deposition step to form a thickness between 〇. A layer of tantalum nitride between 2 and 1 μm is on the layer of oxidized stone. The second protective layer 46 can be formed by first forming a thickness by using a chemical vapor deposition step to form a germanium having a thickness between 〇2 and 12 μm and then using a plasma-enhanced chemical gas 11 phase deposition step. Interpretation, 3 氦, 〇 5 to 0.15 micron inter-study phase - on the eve layer, then re-use between the 〜 ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ On the floor. The method of making the third protective layer 46 can be a step of using the first step of the deposition of the phase deposition, and using a gas mixture between the rice and the rice; 0.05 to 0.15 micro-u of arsenic oxynitride. Layer, rinsing + then using the chemical vapor deposition step to form a layer of ruthenium oxide between the 〇匕 々 々 I I I I I I 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在Then, a step of chemical vapor deposition is used to form a tantalum nitride layer having a thickness between 至2 and 1.2 μm on the yttrium oxide layer. The nitrogen_fourth protective layer 4" can be formed by first utilizing the steps of the pre-emulsion deposition to form a thickness between. .21 a first yttria layer between 0.5 micrometers ' ', a then using a spin coating method (SPin_C〇ating) to form a first yttria layer having a thickness between 0.5 and 丨 micron on the first ruthenium oxide layer And then using a chemical vapor deposition step to form a third oxygen cut layer having a thickness between 0.2 and 〇5 μm on the second oxygen cut layer, followed by a step of chemical vapor deposition. A tantalum nitride layer between 〇2 and 1.2 μm is on the third ruthenium oxide layer. The fifth protective layer 46 can be formed by first performing a high-density plasma chemical vapor deposition (HDP-CVD) step to form a layer of germanium oxide between 0 and 5 micrometers, and then using a sprinkle j 1375284. The step of chemical vapor deposition forms a tantalum nitride layer having a thickness of between 0 and 2 micrometers on the tantalum oxide layer. The sixth protective layer 46 may be formed by a high-density plasma chemical vapor deposition (HDP-CVD) step to form a layer of oxidized stone between 0.5 and 2 microns, followed by chemical gas. The phase deposition step forms a tantalum nitride layer having a thickness between 〇2 and 12 μm on the ruthenium oxide layer.

The seventh protective layer 46 may be formed by first forming an undoped silicate glass (USG) having a thickness between 0 and 2 micrometers, followed by formation of, for example, tetraethoxy decane (TE0S). , borophosphosilicate giass (BpSG) or phosphosilicate glass (PSG), etc.

And a layer of tantalum nitride between the layers of 0. 2 to 1.2 μm is formed in the insulating layer, and an insulating layer is formed on the undoped bismuth glass layer. on. The eighth protective layer 46 can be formed by selectively using a chemical vapor deposition step to form a first-prepared & ,, 氮 氮 氮 layer layer having a thickness between 〇〇5 and 0.15 μm, and then Reusing a chemical vapor deposition step to form a ruthenium oxide layer having a thickness between 〇2 and micron on the first ruthenium oxynitride layer, and then selectively utilizing chemical pain, ... > The step of the product is to form a second layer of bismuth oxynitride between 0.05 and 0.15 micro-half of the door, on the oxidized stone layer, and then go to the amp amp & Vapor deposition step shape 13

a thickness of between 〇.2 and 12 cats^2: 沁------------------------------------------------------------------------------------------ Upper, then 〇〇5 ? η 1, the price of the step to form a thickness between υ. Μ to 0. 15 microns on a layer of ,, &; — 氮 氮 氮 在 在 : : : : : : Reuse chemical vapority between. Between .2 and U micron: a step "thickness ^ g: r. a lithographic layer on the third yttria layer or on the tantalum nitride layer. The ninth protective layer 46 is made ^ ^, pretending The method may be first to use a step of chemical rolling phase deposition (PECVD) to form a first cerium oxide layer with a thickness between 0.2 and 1.2 micrometers, and then to use a spin coating method. SPln—C〇ating) forming a second yttrium oxide layer having a thickness between 〇.5 and i μm on the first ruthenium oxide layer, followed by a step of chemical vapor deposition to form a thickness of 〇2 to 】 2 Between the third and the third yttrium oxide layer on the second yttrium oxide layer. Then, the step of chemical vapor deposition is used to form a tantalum nitride layer having a thickness between 〇·2 and 1.2 μm. The third ruthenium oxide layer is then subjected to chemical vapor deposition step (4) to a thickness of # 〇. 2 i 1. A layer of a fourth ruthenium oxide layer between 2 microns is on the layer of nitriding. The first layer is formed by a high-density plasma chemical vapor deposition (HDP_CVD) step to form a first thickness between 0.5 and 2 microns. a layer of ruthenium oxide, followed by a step of chemical vapor deposition to form a layer of tantalum nitride having a thickness between 〇2 and 1.2 μm on the first layer of ruthenium oxide, followed by Litian ancient s'-^ Supplementation ^Density Plasma Chemical Vapor Deposition (HDP-CVD) is formed by a thickness of ..... between a micrometer and a second oxide on the nitrogen layer. The thickness of the protective layer is generally large. 35 Micron, in preferred cases, the thickness of the nitride layer is typically greater than 0.3 microns. A bump can be formed on the semiconductor wafer 23, the bump containing a metal layer having a thickness greater than 5 microns, 1G micron < 20 microns, and a smear point greater than 185 degrees Celsius or greater than 350 degrees Celsius, in this embodiment The metal layer is, for example, gold' as described below; in other embodiments, the material of the metal layer may also be copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel. Please refer to the fourth A to fourth (four), the fifth A to the u and the sixth to the eighth. First, please refer to the fourth B, the first pad 40 of the semiconductor wafer 23. And a diffusion barrier layer 48 having a thickness between 〇1 and 1 μm formed by electroless plating, chemical vapor deposition (CVD), sputtering or evaporation on the protective layer 46, the diffusion barrier layer The 48 series is at least one of a group consisting of titanium metal, titanium nitride, titanium alloy layer, group metal, and nitride group, and the diffusion barrier layer 48 contributes to improving the adhesion ability of the subsequently deposited metal. And can be used to prevent the diffusion of the connection metal into the adjacent dielectric layer. Next, please refer to the fourth C diagram, using sputtering, evaporation or electroless plating to form, for example, gold and the thickness is between 〇 A sub-layer 50 between 05 and 1 micron is formed on the diffusion barrier layer 48, and the seed layer 50 can be formed using a sputtering metal reaction chamber or an Ion Metal Plasma metal reaction chamber. The process temperature range is from 1375284 to 0 to 300 degrees. C, the pressure range is from 1 to 100 mT 〇rr. Then, the photoresist layer 52 is formed on the seed layer 50 by a spin_on_coating method. The thickness of the photoresist layer 52 is between 5 micrometers and 400 micrometers, and the thickness is preferably 5 micrometers. Between 1 〇〇 micron. Through the steps of exposure (eXpQsing), (d) (develQping), etc., the photoresist layer 52 forms a plurality of patterned openings, and exposes the seed layer 5' on the first pad 40 via the patterned openings. Show. The distance between the patterned openings is between 5 microns and 4 microns, which is the distance between the centers of the two openings, wherein the preferred spacing of the patterned openings is between 5 microns and 50 microns. Next, referring to the fourth D figure, a gold layer 54' having a thickness (Ha) between 5 micrometers and 4 micrometers is formed on the seed layer 50 exposed by the patterned opening by electroplating. The preferred thickness (five) of 54 is between 5 micrometers and 100 micrometers, and the lateral maximum dimension (10) of the gold layer 54 is between 3 micrometers and 500 micrometers. In the preferred case, the lateral maximum dimension ( Hb) is between 3 microns and 50 microns. Next, referring to FIG. 4E, the photoresist layer 52 is removed, and then the seed layer 50 not under the gold layer 54 is removed by a surname, and then the diffusion barrier not under the gold layer 54 is removed by etching. The insulating layer 46 is not exposed under the gold layer 54 and then the semiconductor wafer 23 is diced to cut the semiconductor wafer 23 into a plurality of semiconductor wafers 22 (shown in the sixth figure). Each of the semiconductor wafers 22 has a plurality of bumps including a gold-containing layer 54. In addition, when the seed layer 5 暴露 exposed on the patterned opening is formed with a thickness of 16 μ between 5 μm and 働 ^, and the material of the seed bank 5 以 is preferably copper; When the silver layer between 5 micrometers and the side is on the seed layer 5G, the material of the seed layer 50 is preferably silver, and when the thickness of the electrode is between 5 micrometers and the weight micron, the layer is on the seed layer 50. When the material of the seed layer 5 is palladium, when the thickness of the shovel is between 5 μm and 400 μm on the seed layer 5: the material of the seed layer 50 is preferred; When the recording layer with a thickness of between 5 micrometers and _micrometers is on the seed layer, the material of the seed layer μ is preferably money; when the thickness of the clock is between 5 micrometers and micrometers When the layer is on the seed layer 50, the material of the seed layer 5G is preferred; when the layer of the layer between 5 micrometers and 4 micrometers is to be plated on the seed layer 5, the material of the seed layer 50 is Preferably, when a nickel layer having a thickness of between 5 micrometers and 400 micrometers is to be plated on the seed layer 5, the material of the seed layer 5 is preferably nickel. Referring to FIG. 5A, a metal layer 55 may be formed on the second pad 42 before the semiconductor wafer 22 is bonded to the semiconductor wafer 23', thereby increasing the reliability of the bonding bump and the second pad 42. The material of the metal layer must match the material of the bump; in this embodiment, the metal layer includes, for example, a gold layer having a thickness between 0.05 micrometers and 1 micrometer, or a thickness between 5 micrometers and 50 micrometers. Tin-containing solder layer. Then, referring to FIG. 5B, a patterned polymer layer 56 is disposed on the protective layer 46 of the semiconductor wafer 23. The patterned polymer layer 56 is made of a thermoplastic plastic, a thermosetting plastic, or a polyimide. (polyimide 'Pi), phenylcyclobutylene (b.enzo-Cycl〇-butene, 17 Ί1^ supplement 丨BCB), polyurethane or epoxy resin, the patterned polymer layer 56 has a lateral maximum The distance (He) is, for example, a plurality of openings 58 between 5 microns and 500 microns, the openings 58 exposing the metal layer 55 on the second pads 42, preferably in the lateral maximum distance of the openings 58 (He) is between 5 micrometers and 50 micrometers; the distance between each adjacent two openings 58 (Hd) is, for example, between 5 micrometers and 400 micrometers, and the distance between 5 micrometers and 400 micrometers (Hd) It is the distance between the centers of the two openings 58. In the preferred case, the distance between adjacent two openings 58 (Hd) is between 5 micro and 100 micrometers, and the thickness of the patterned polymer layer 56 ( The He) system is between 5 microns and 400 microns, and in the preferred case, the patterned polymer layer 56 Degree (He) line is between 5 to 50 microns. The thickness (Ha) of the gold layer 54 may be greater or less than the thickness (He) of the patterned polymer layer 56, wherein the thickness difference must depend on the material properties of the patterned polymer layer 56. The thickness of the patterned polymer layer 56 is greater than the thickness (Ha) of the gold layer 54. If the volume of the patterned polymer layer 56 is hardened, then the volume is increased. The thickness (He) of the patterned polymer layer 56 must be less than the thickness (Ha) of the gold layer 54. The thickness (Ha) of the gold layer 54 and the thickness (He) of the patterned polymer layer 56 are, for example, within 1 μm. In addition, the patterned polymer layer 56 is doped with a flux to facilitate bonding of the semiconductor wafer 22 to the line component 24; in addition, the patterned polymer layer 56 may also contain a filler, or It may also contain no filler. The patterned polymer layer 56 can be fabricated in a number of ways. The first way is to have a pre-patterned dry film 1375284

The photo-adhesive film is hot-pressed on the semiconductor wafer 23', and the photosensitive film is patterned by lithography. In the third method, a non-photosensitive adhesive film is thermocompression-bonded onto the semiconductor wafer 23', and the photosensitive adhesive film is patterned by a lithography method; the fourth method uses a spin The coating method applies a photosensitive colloid to the semiconductor wafer 23, and the photosensitive colloid is patterned by a lithography method, and the viscosity of the photosensitive body is greater than 90,000 cP; the fifth mode is also A non-photosensitive colloid is applied to the semiconductor wafer 23' by a spin coating method, and the non-photosensitive colloid is patterned by a photolithographic etching method, and the viscosity of the non-photosensitive colloid is also greater than 9〇〇〇. 〇 cp; The sixth mode is set on the semiconductor wafer 23 by screen printing. The patterned polymer layer 56 is made of a material that does not flow at a normal temperature and has high viscosity before being heated, so that the patterned polymer layer 56 can be prevented from flowing arbitrarily to the semiconductor wafer 23, thereby avoiding The metal layer 55 is stained to the semiconductor wafer 23, wherein the viscosity of the patterned polymer layer is, for example, greater than 90,000 cP (lcP = 1 〇 -2 g / cm * s) at normal temperature. In addition, the patterned polymer layer 56, if heated, decreases its viscosity as the temperature increases. Next, referring to the sixth and seventh figures, each semiconductor wafer 22 is disposed on the semiconductor wafer 23, so that a gold layer 54 (bump) of the semiconductor wafer is placed in each opening 58 and Each of the gold layers is abutted on the metal layer 55. At this time, a 19 electrical inspection step can be performed by two external wirings 44, and it is checked whether each gold layer 54 is positively associated with each of the second pads 42. Electrical connection, if some of the gold layers are not electrically connected, the repairing step can be performed, and the next step is performed when the detection result is good, so that the yield of the packaging process can be greatly increased'. Further, if the patterned polymer layer 56 is used. When the thickness (He) is greater than the thickness (Ha) of the gold layer 54, the electrical inspection step is to perform a light dust action under each of the semiconductor wafers 22 to cause each of the gold layers 54 to abut against the metal layer 55. Complete the electrical test. When the electrical test is completed, please refer to the eighth figure for the heat treatment process. The heat treatment is carried out by heating, microwave heating or infrared heating. The processing temperature is 8 degrees Celsius to 4 (10) Celsius. The flux flows out of the patterned polymer layer 56 during the heat treatment process to facilitate bonding of the gold layer 54 to the gold or 3 tin metal layer 55 located on the second (four) 42 and to promote the patterned polymer layer. The bonding of 56 to the protective layer 46 allows the patterned polymer layer 56 to be securely attached. On the surface of the protective layer of the semiconductor wafer 22 and the line component 24. Next, the (fourth) step of the semiconductor wafer 23 is performed to cut the semiconductor wafer 23' into a plurality of independent circuit elements (semiconductor wafers), and each of the circuit elements 24 is provided with a corresponding semiconductor wafer 22, It is an explanation of the first semiconductor junction structure and its process. Second Embodiment %=Continued to introduce the structure of the second embodiment and the structure of the first embodiment, as shown in the first and third figures, 'the semiconductor wafer 23 is also included. 23 The semiconductor wafer 23 can be cut into a plurality of semiconductors. The wafer 22, 20 1^75284 and the semiconductor wafer 23' can be cut into the element f24, and the line element 24 can be selected from the substrate type except for the semiconductor wafer 23', and the substrate type can be selected. One of the glass substrate, the printed circuit board, the ceramic substrate, the soft board, or the glass fiber-containing substrate, and the circuit element 24 of the second embodiment is also labeled with a semiconductor wafer, in the semiconductor wafer. The active surface of 23, 23 also forms a plurality of electronic π members 26, and the steps and patterns for forming the electronic components 26 are the same as those of the first embodiment described above, and will not be described in detail herein. Thin film insulating layers 28, 30, 32 are respectively disposed on the active surfaces of the semiconductor wafers 23, 23 by chemical deposition, and are embedded in copper on the thin film insulating layers 28, 30, 32 of the semiconductor wafers 23, 23'. The process or the aluminum sputtering process respectively forms a plurality of thin film metal layers 34, 36, a plurality of first pads 4A and a plurality of second pads 42, and among the formed second pads 42, the first pads of the blade 42 is pre-existing as an external pad 44, and the external connection is for the whole structure to be connected to the outside world. Next, a protective layer 46 is disposed on the surface of the semiconductor wafer 22 and the line component 24 by chemical vapor deposition (CVD). The protective layer 46 has a plurality of notches, and the notches expose the first pad 40 and the second pad 42. The protective layer 46 is fabricated in the same manner as the ten embodiments described in the first embodiment. In the present embodiment and the first embodiment, the same reference numerals denote the same components. Then, a bump can be formed on the semiconductor wafer 23. The bump has a metal layer having a thickness greater than 5 micrometers, 10 micrometers, or 2 micrometers and a bright point greater than 185 degrees Celsius or greater than 35 degrees Celsius, in this embodiment. In this metal layer, such as copper, as follows 21 1375284 Yuecheng Supplement 1

Said. Please refer to the ninth to fifth ninth, tenth to tenth, and eleventh to thirteenth. First, please refer to the ninth B, in the semiconductor wafer 23 A diffusion barrier layer 60 having a thickness between 〇1 and i micrometers is formed on a pad 40 and a protective layer 46 by means of SpUttering or evaporating, and the diffusion barrier layer 6〇 It is formed by a titanium metal layer, a titanium nitride layer, a titanium tungsten alloy layer, a button metal layer, a nitrided layer, a metal layer, a copper alloy layer, or a composite layer composed of at least one of the above materials.

Then, please refer to the ninth C diagram, using a sputtering, steaming or electroless plating method to form a seed layer 62 having a thickness of between 0.05 and 1 micron and a material of copper metal in the diffusion barrier layer. At 60, the process for setting the seed layer 62 uses copper or a copper alloy as a coffin, uses argon gas and controls its flow rate of 10 to 40 0 sccm 'and when copper metal is used as the seed layer 62, it is located under the copper metal. The choice of the diffusion barrier layer 6 变得 material becomes quite important 'because copper has a relatively large diffusion coefficient for yttrium oxide and shi shi, 'when the steel diffuses to the yttrium oxide layer, it will cause the dielectric material layer to change. To conduct electricity, reduce its dielectric strength or dielectric strength. Then, by spin-on-c- ing, a layer 64 is formed on the seed layer 62. The thickness of the photoresist layer 64 is between 5 micrometers and 400 micrometers. A preferred thickness is between 5 microns and 100 microns. Through the steps of exposing 22" coffee" (8), developing wevekpind, etc., the photoresist layer I4 forms a plurality of patterned openings, and through these patterned openings, the seed layer 62 on the first interface 40 is violently exited, as shown in FIG. Do not. The distance between the patterned openings is between 5 microns and 4 〇〇 micro + H _ (4), and the preferred spacing of the patterned openings is between 5 microns and 5 microns. Next, referring to FIG. 9D, a metal bump 66 is formed on the seed layer 62 exposed by the patterned opening by electroplating. The metal bump 66 is a composite metal layer which is first in the photoresist layer 64. The seed layer 62 exposed by the patterned opening is plated to form a columnar copper metal layer 68 having a thickness (Hg) between 1 μm and 15 μm, and then electroplated on the copper metal layer 68 to form a thickness (Hi). The nickel metal layer 7〇 between 1 micrometer and 2 micrometers is finally plated on the nickel metal layer 70 to form a gold layer 72 or thickness (Hj·) having a thickness (Hj) of between 300 angstroms (A) and 5 micrometers. a tin-containing solder layer between 5 micrometers and 1 micrometer, wherein the solder layer 72 is, for example, a tin-lead alloy layer, a tin-silver alloy layer, a tin-silver-copper alloy layer, or a lead-free solder layer. The lateral maximum dimension (Hf) of the columnar copper metal layer 68 of the metal bump 66 is, for example, between 3 micrometers and 5 micrometers micron. In the preferred case, the lateral maximum dimension (Hf) is Between 3 microns and 50 microns. The maximum cross-sectional area of the columnar copper metal layer 68 is, for example, within 1% of the smallest cross-sectional area. 23 1375284

Next, referring to FIG. 9E, the photoresist layer 64 is removed, and then the seed layer 62' not under the copper metal layer 68 is removed by etching, and then the diffusion under the copper metal layer 68 is removed by etching. The barrier layer 60 is exposed such that the protective layer 46 that is not under the metal bumps 66 is exposed. When the metal layer 72 located at the top end of the metal bump 66 is composed of a solder layer, 'a heating process can be selectively performed next'. When the heating reaches the melting of the solder layer 72

When this is done, the solder layer 72 is deformed into a spherical pattern. Next, the dicing of the semiconductor wafer 23 is performed to cut the semiconductor wafer 23 into a plurality of semiconductor wafers 22 (shown in FIG. 11), and each of the semiconductor wafers 22 is provided with a plurality of metal bumps 66. . Referring to FIGS. 10A and 10B, before the semiconductor wafer 22 is bonded to the semiconductor wafer 23, the second pad on the semiconductor wafer 23 is used.

42 and the protective layer 46 are formed by a non-electrolytic plating chemical vapor deposition (cvd), sputtering or a steaming clock to form a diffusion barrier layer 60 having a thickness between 〇1 and W meters, and the diffusion barrier layer 6〇 is at least one of a group consisting of titanium metal, titanium nitride, titanium-tungsten alloy layer, neon metal, nitrided metal, road metal and chrome-copper alloy layer. The diffusion barrier layer helps to improve Connect: the bonding ability of the deposited metal, and can be used to avoid the diffusion of the adjacent metal diffusion layer, and then form a seed layer having a thickness of ^(10) to 丨micron: and the material is gold or copper (not shown) On the diffusion barrier layer 60, 0 is then formed on the seed layer. Please refer to the photo resist layer 64 shown in the tenth C and tenth d, and the photoresist layer 6 is formed in the majority of the opening. a seed layer on the second pad 42; then, a metal layer 65 is formed by electroplating on the seed layer exposed by the opening, thereby increasing the reliability of bonding the metal bump 66 and the second pad 42, the metal The material of the layer must be matched with the material of the metal bump 66; in this embodiment, the gold The layer 65 includes, for example, a gold layer having a thickness of between 〇〇5 μm and 1 μm. The material of the seed layer is, for example, gold; or, in other embodiments, the metal layer 65 is formed by electroplating. a copper layer having a thickness between 丨 micrometers and 1 〇 micrometer is deposited on the seed layer exposed by the opening of the photoresist layer 64, and then a nickel layer having a thickness of between 1 micrometer and 5 micrometers is plated in the copper layer. The upper layer is then plated with a tin-containing solder layer having a thickness between 5 micrometers and 5 micrometers. The material of the seed layer is, for example, copper. Next, referring to the tenth and tenth F, the patterned photoresist layer 64 is removed and the seed layer and the diffusion barrier layer 60 not under the metal layer 65 are removed to expose the protective layer 46, such as The patterned polymer layer 56 is then disposed on the protective layer 46 of the semiconductor wafer 23'. The patterned polymer layer 56 is patterned using the six types described in the first embodiment. The layer 56 is made by the same method. The material of the patterned polymer layer 56 is also thermoplastic, thermosetting plastic, polyimide, and phenylcyclobutene (BCB). Polyurethane (p〇iyUrethane) or epoxy resin, the patterned polymer layer 56 having a lateral maximum distance (Hk) such as a plurality of openings 58' between 5 microns and 5 microns. These openings 58 are exposed Out of the metal layer 65 on the second pad 42, in the preferred case, the lateral maximum distance 25 (Hk) of the openings 58 is between 5 microns and 50 microns; the distance between each adjacent two openings 58 (H1) is between 5 microns and 400 microns, this distance between 5 microns and 400 microns (H1) is the distance between the centers of the two openings 58. In the preferred case, the distance between the adjacent two openings 58 (H1) is between 5 micrometers and 100 micrometers; the patterned polymer layer 56 The thickness (Hn) is, for example, between 5 micrometers and 400 micrometers. In the preferred case, the thickness (Hn) of the patterned polymer layer 56 is between 5 micrometers and 50 micrometers; the metal bumps 66 The thickness (Hg+Hi+Hj) may be greater or less than the thickness (Hn) of the patterned polymer layer 56, wherein the thickness difference must depend on the material properties of the patterned polymer layer 56 if the patterned polymer layer 56 is hardened. After the volume is reduced, the thickness (Hn) of the patterned polymer layer 56 must be greater than the thickness of the metal bumps 66 (Hg+Hi+Hj). If the patterned polymer layer 56 is hardened, the volume is presented. In the case of increase, the thickness (Hn) of the patterned polymer layer 56 must be smaller than the thickness of the metal bumps 66 (Hg+Hi+Hj), and the thickness of the metal bumps 66 (Hg+Hi+Hj) and the patterned polymerization. The thickness (Hn) of the layer 56 is within 10 micrometers, for example, and the patterned polymer layer 56 is doped with a flux (f 1 ux ), In order to facilitate the bonding of the semiconductor wafer 22 to the line component 24; in addition, the patterned polymer layer 56 may also contain a filler or may not contain a filler. The patterned polymer layer 56 is made of a material that does not flow at a normal temperature and has high viscosity before being heated, so that the patterned polymer layer 56 can be prevented from flowing arbitrarily to the semiconductor wafer 23, and other places thereon. In order to avoid contamination to the metal layer 65 of the semiconductor wafer 23', the viscosity of the patterned polymer layer at room temperature is greater than 90,000 cp (lcp = ΙΟ·2 g/cm*s). In addition, when heated, the patterned polymer layer 56 may, for example, decrease its viscosity as the temperature increases. Then, please refer to FIG. 1 and FIG. 1 and FIG. 1 to place each semiconductor wafer 22 on the semiconductor wafer 23' so that the metal bumps 66 on the semiconductor wafer 22 are respectively placed in each opening 58' And each metal bump 66 is abutted against the metal layer 65,

At this time, an electrical inspection step can be performed by the two external pads 44 to check whether each of the metal bumps 66 is electrically connected to each of the second pads 42 if some of the metal bumps 66 are not The electrical connection can be repaired, and the next step is performed when the detection result is good, so that the yield of the packaging process can be greatly increased; and if the thickness (Hn) of the patterned polymer layer 56 is larger than that of the metal bump 66 In the case of thickness (Hg + Hi + H j), this electrical inspection step must be lightly pressed under each semiconductor wafer 22.

The action 'resistes each metal bump 66 against the metal layer 65 to complete the electrical inspection. Next, referring to the thirteenth diagram, the heat treatment is performed by a baking heating method or a microwave heating method, and the processing temperature is performed between Celsius and 400 degrees Celsius, and the flux is patterned from the heat treatment process. The polymer layer 56 flows out to facilitate bonding of the gold or solder layer 72 to the gold or metal containing layer 65 on the second pad 42 and to facilitate bonding of the patterned polymer layer 27 1375284 to the protective layer 46, The patterned polymer layer 56 can be securely bonded to the surface of the protective layer 46 of the semiconductor wafer 22 and the line component 24. Next, the dicing step of the semiconductor wafer 23' is performed to cut the semiconductor wafer 23' into a plurality of line elements 24 (semiconductor wafers), and the corresponding semiconductor wafers 2 2 are bonded to each of the line elements 24. The above is a description of the second semiconductor junction structure and its process. Therefore, the present invention replaces the conventional disintegration bumps with gold bumps or metal pillars, so that the spacing between each bumps is reduced, thereby greatly reducing the volume of the entire flip-chip structure' and because of gold bumps or metals. The replacement of the conventional solder bumps by the pillars makes the junctions on the crystal moon denser and makes the wafer more versatile in design, thereby making the overall semiconductor junction structure more economical. The above description of the embodiments of the present invention is intended to be understood by those skilled in the art, and the invention may be practiced without departing from the scope of the invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described below. BRIEF DESCRIPTION OF THE DRAWINGS: The first figure is a schematic cross-sectional view of a semiconductor junction structure of the prior art. The second figure is a partially enlarged cross-sectional view of a semiconductor device of the present invention. The second figure is a partially enlarged cross-sectional view of the circuit component of the present invention. 4 to 4 are schematic cross-sectional views showing a process of fabricating a semiconductor device according to a first embodiment of the present invention. 28 1375284

Figs. 5A to 5B are schematic cross-sectional views showing the process of the circuit element structure according to the first embodiment of the present invention. 6 to 8 are schematic cross-sectional views showing a process of a semiconductor device in combination with a line member according to a first embodiment of the present invention. 9A to IXE are schematic cross-sectional views showing a process of fabricating a semiconductor device in accordance with a second embodiment of the present invention. 10A to +F are schematic cross-sectional views showing the structure of a circuit component according to a second embodiment of the present invention. 11 to 13 are schematic cross-sectional views showing the process of the semiconductor component surname circuit component of the first embodiment of the present invention. °°[Main component symbol description] 12 bump 14 wafer 16 wafer 18 underfill 20 external pad 22 semiconductor wafer 23 semiconductor wafer 23, semiconductor wafer 24 circuit component 26 electronic component 28 thin film insulating layer 30 thin film insulating layer 32 Thin film insulating layer 34 Circuit layer 36 Circuit layer 38 Via 40 First pad 42 Second pad 44 External pad 46 Protective layer 48 Diffusion barrier 50 Seed layer 52 Photoresist layer 54 Gold layer 55 Metal layer 56 w Case polymer layer 29 1375284

58 Opening 60 62 Seed layer 64 65 Metal layer 66 68 Copper metal layer 70 72 Bonding layer β ...丨 V 4 ! —·· Diffusion barrier layer Photoresist layer Metal bump Recording metal layer

30

Claims (1)

1375284 '· 095115973 Patent Application I Skillful Furnace·Small Chinese Application Patent Range Replacement (9f year H0 Consumer/Cf 'Application Patent Range·1 H 1 , a wafer-connected wafer process, including the following steps: Provide one a semiconductor wafer and a semiconductor wafer, wherein the semiconductor wafer includes a sub-layer and a first metal bump, the seed layer is between the first metal bump and a pad of the semiconductor wafer, and the first metal The ingot includes a nickel layer and a tin-containing metal between the seed layer and the tin-containing metal, the nickel layer having a thickness between i microns and 20 microns; forming a polymer layer in the semiconductor a -first opening on the wafer and located within the polymer layer exposing the metal I of the semiconductor wafer, the polymer layer having a thickness between 5 microns and 4 microns; and forming the polymerization After the step of the layer of burdock + & A. _ A (3), bonding the tin-containing metal to the metal M ^ Sx X , I genus layer exposed by the first opening, and constituting the chelating layer Contacting the semiconductor wafer and contacting the first metal bump The process of wafer-connecting wafers described in the first paragraph of Shenyue Patent, in which the material of the metal layer comprises gold or tin. ', 3. The wafer-connected wafer as described in the first paragraph of the patent application diagram. The process of the first metal layer of the metal layer in the pot before joining the metal containing the tin and the first opening. The thickness of the bump is greater than the polymer. The thickness of the layer 4, as in the patent application, in the process of bonding the wafer-connected wafer described in the tin-containing metal article, before the step, the difference of the metal layer exposed by the first opening is 10 Within the micron. The cut-in 7-degree phase 5, as in the wafer-attached wafer process described in claim 1, the 143023-991027.doc is bonded to the tin-containing metal and exposed to the first opening The step of the step of extracting the metal layer is further included in the process of the wafer-attached wafer according to claim 1, wherein the semiconductor wafer further comprises the pad and the seed layer. A layer of titanium containing metal. 7. If applied The process for wafer-bonding wafers according to item 6, wherein the metal layer of the 5H is a titanium nitride layer or a titanium-tungsten alloy layer. 8. The wafer connection as described in claim 1 The process of the wafer, wherein the semiconductor wafer further comprises a group of metal layers between the pad and the seed layer. 9. The process of wafer bonding wafers according to claim 8 of the patent application, wherein the The metal layer of the button is a tantalum nitride layer. The process of wafer-bonding wafers according to claim 1, wherein the tin-containing metal has a thickness of between 5 micrometers and 1 micrometer. 11. The process of wafer-attached wafers as described in the scope of the patent application, wherein the formation of the seed layer comprises a sputtering process. 12. The process of wafer bonding a wafer according to claim 4, wherein in the step of forming the polymer layer, a second opening in the polymer layer exposes a connection of the semiconductor wafer And the distance between the first opening and the second opening is between 5 micrometers and 100 micrometers, and in the step of bonding the tin-containing metal and the metal layer exposed by the first opening, A second metal bump of the semiconductor wafer engages the contact exposed by the second opening. ^13. The process of wafer-attached wafers as described in the scope of the patent application, 143023-99J027.doc 1375284, includes forming a step containing a flux (the step of forming the polymer layer in Πιιχϋ^ in the semiconductor crystal The process of forming the polymer layer in the process of wafer-bonding wafers as described in claim 1 includes forming a viscous layer greater than 90 _ a polymeric layer. The scope of the second item W Μ ^ 炙 0 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接The maximum lateral distance of the first opening is between 5 micrometers and 5 micrometers. 17. The process of wafer-connecting wafers as described in claim i, wherein the step of forming the polymer layer comprises thermocompression bonding - a dry film (4) on the semiconductor wafer 18. The process of forming a wafer-bonded wafer as described in the scope of the patent application, wherein the step of forming a polymer layer comprises a screen printing step. The process of connecting a wafer to a wafer according to the item i, wherein the pad is formed by using a damascene process or a sputtering process. 20. The process of wafer bonding wafers as described in claim 1 The material of the seed layer comprises copper metal. 21. The process of connecting a wafer to a wafer according to the above-mentioned claim, wherein the nickel layer is formed by electroplating. The process of connecting a wafer to a wafer, wherein the tin-containing metal is formed by electroplating. 23. The process of wafer bonding a wafer according to claim i, wherein the tin-containing metal and the first opening are bonded The step of exposing the metal layer is 143023-991027.doc 1375284 I '·· _ m is performed at a temperature between 80 ° C and 400 ° C for f ' T- - 1 - 24, a wafer The process of connecting a wafer includes the steps of: providing a semiconductor wafer and a semiconductor wafer, wherein the semiconductor wafer comprises a metal layer, the semiconductor wafer includes a first metal bump, and the semiconductor wafer a metal bump includes a copper layer and a tin-containing metal, the steel layer being between the tin-containing metal and a pad of the semiconductor wafer, the steel layer having a thickness of between 10 micrometers and 150 micrometers; forming a a polymer layer on the semiconductor wafer, and a first opening in the polymer layer exposing the metal layer, the polymer layer having a thickness between 5 microns and 400 microns; and forming the polymer After the step of bonding, the tin-containing metal and the metal layer exposed by the first opening are bonded, and the polymer layer contacts the semiconductor wafer and the first metal bump. 25. The process of wafer bonding a wafer according to claim 24, wherein the thickness of the first metal bump is prior to the step of bonding the tin-containing metal and the metal layer exposed by the first opening. Greater than the thickness of the polymer layer. 26. The process of wafer-attaching a wafer according to claim 24, wherein the thickness of the first metal bump is prior to the step of bonding the tin-containing metal and the metal layer exposed by the first opening The difference from the thickness of the polymer layer is within 10 microns. 27. The process of wafer bonding wafers of claim 24, wherein the step of forming the polymer layer comprises forming a polymer containing a flux on the semiconductor wafer. 143023-991027.doc 1375284 28. The wafer connection of claim 24, wherein the step of forming the polymer layer comprises forming a viscous polymer layer. The fabrication of a wafer, the process of wafer-bonding wafers as described in claim 24, wherein the bonding of the tin-containing metal to the first opening is performed The step of the metal layer further includes an electrical inspection step. The process of wafer-bonding wafers according to claim 24, wherein the maximum lateral distance of the first opening is between 5 micrometers and The process of wafer-bonding wafers according to claim 24, wherein the lateral maximum dimension of the copper layer is between 3 micrometers and 5 micrometers. 32. The process of connecting the wafer to the wafer according to the above, wherein the lateral maximum dimension of the copper layer is between 3 micrometers and 5 micrometers. 33. The wafer bonding wafer process according to claim 24 of the patent application scope, Wherein the first metal bump further comprises a nickel layer, and the recording layer is located between the copper layer and the tin-containing metal. 34. The wafer bonding wafer process according to claim 24, wherein The thickness of tin-containing metals ranges from 5 microns to 1 35. The process of wafer bonding wafers of claim 24, wherein the step of forming the polymer layer comprises thermally pressing a dry film (dry (1)) onto the semiconductor wafer. The process of wafer-bonding wafers as described in claim 24, wherein the step of opening the polymer layer comprises a screen printing step. 37. The wafer connection as described in claim 24 The process of the wafer, 143023-99I027.doc 1375284, wherein the material of the tin-containing metal does not contain the process of the wafer-attached wafer according to claim 24, wherein the semiconductor wafer further includes the A process for bonding a wafer to a wafer as described in claim 38, wherein the group-containing metal layer is a nitride layer. 40. The process of wafer-connecting a wafer according to claim 24, wherein the semiconductor wafer further comprises a titanium-containing metal layer between the first metal bump and the interface. Patent scope The process of connecting a wafer to a wafer according to the above, wherein the titanium-containing metal layer is a titanium-tungsten alloy layer or a titanium nitride layer. 42. The process of wafer-connecting wafers according to claim 24 The pad is formed by using a damascene process or a sputtered aluminum process. 4'3. The process of wafer-connecting a wafer according to claim 24, wherein the material of the s-metal layer comprises gold. The process of wafer-connecting a wafer according to claim 24, wherein the semiconductor wafer further comprises a sub-layer between the first metal bump and the pad and the seed layer A process for wafer-bonding wafers as described in claim 24, wherein the copper layer is formed by electroplating. 46. The process of wafer bonding wafers according to claim 24, wherein the tin-containing metal is formed by electroplating. 47. The process of connecting a wafer to a wafer according to claim 24, 143023-99I027.doc 1375284 * · wherein the tin-containing metal is bonded The V-thread of the metal layer exposed by the first opening is performed at an /IHL degree between 8 degrees Celsius and 4 degrees Celsius. 48. The process of wafer-attached wafers according to claim 24, wherein in the step of forming the polymer layer, a portion of the polymer layer is exposed, and the opening exposes a connection of the semiconductor wafer And the distance between the first opening and the first opening is between 5 micrometers and 100 micrometers, and in the step of bonding the metal metal layer exposed by the metal and the first opening, A second metal bump of the semiconductor wafer engages the contact exposed by the second opening. 49. A chip package structure comprising: a circuit component comprising a first dielectric layer, a first circuit layer and an insulating layer, wherein the first circuit layer is above the first dielectric layer, the first The material of the circuit layer comprises electroplated copper, the insulating layer is located above the first dielectric layer and above the first circuit layer, a first gap is located in the insulating layer Inside and on a first contact of the first circuit layer, the first contact is located at a bottom end of the first notch; a cattle conductor chip, the circuit component comprises a substrate, a plurality of transistors, and a a second dielectric layer, a second circuit layer and a protective layer, wherein the second dielectric layer is located under the plurality of dielectric layers, the second circuit layer is located under the second dielectric layer, the protective layer is located Under the second circuit layer and under the second dielectric layer, the material of the second line: layer comprises electroplated copper, and the protective layer comprises a nitriding layer having a thickness between 〇2 μm and ^μm. (silicon nitride) layer, - 筮 - from the first gap in the protective layer and below a second junction of the second circuit layer, the second 143023-991027.doc 1375284 a contact is located at a top end of the second notch; a copper cylinder between the first contact and the second contact, and the height of the steel cylinder is between 10 micrometers and 15 micrometers, the copper The lateral maximum dimension of the cylinder is between 3 micrometers and 5 micrometers, the copper pillar is connected to the first joint via the first gap and the second joint is connected via the second gap; 'between the copper pillar and the second joint; a tin-containing metal between the copper pillar and the first joint; a gold layer 'located between the tin-containing metal and the first joint And the first contact connects the second contact via the nickel layer, the tin-containing metal, the copper pillar and the titanium-containing metal; and a polymer layer between the insulating layer and the protective layer And the polymer layer contacts the copper pillar and contacts the insulating layer. 50. The wafer package structure of claim 49, wherein a distance between a pair of opposite sides of the semiconductor wafer is less than a distance between a pair of opposite sides of the line component. The wafer sealing structure according to claim 49, wherein the material of the insulating layer comprises Shi Xi. 52. The chip package structure of claim 49, wherein the protective layer further comprises a silicon germanium xide layer. 53. The wafer package structure of claim 49, further comprising a nickel-containing metal between the tin-containing metal and the copper pillar. 54. The wafer package structure of claim 49, wherein the titanium-containing metal material comprises titanium nitride. 55. The wafer package structure of claim 49, wherein the material of the titanium-containing metal comprises a titanium-tungsten alloy. 56. The wafer seal of claim 49, wherein the titanium-containing metal has a thickness of between 0.1 micrometers and 1 micrometer. 57. The chip package structure of claim 49, wherein the tin-containing metal material comprises a tin-lead alloy. 58. The wafer package structure of claim 49, wherein the material of the gamma-containing metal comprises a tin-silver alloy. 59. The chip package structure of claim 49, wherein the tin-containing metal material comprises a tin-silver-copper alloy. 60. The chip package structure of claim 49, wherein the tin-containing metal material does not include lead. The wafer package structure of claim 49, wherein the material of the polymer layer comprises an epoxy resin. The wafer package structure of claim 49, wherein the recording layer has a thickness of between 1 micrometer and 5 micrometers. The chip package structure of claim 49, wherein the circuit component further comprises a capacitor element. 64. The chip package structure of claim 49, wherein the circuit component further comprises a resistive component. 65. A chip package structure comprising: a circuit component comprising a first dielectric layer, a first circuit layer and an insulating layer 'where the first circuit layer is above the first dielectric layer' The material of the circuit layer comprises galvanized steel, the insulating layer is located above the first dielectric layer and above the first circuit layer, and the first notch is located in the insulating layer 143023-991027.doc and is located at the first The circuit layer L.-^ is above the first contact, the first connection is located at the bottom end of the first gap, and the contact is located in the factory edge layer of the second contact of the first circuit layer and the second gap a bottom end; the first contact is located on the semiconductor wafer above the line element including - a stone substrate, a plurality of transistors, - #conductor - sheet β rice 徂 徂 &< a second line 2: a protective layer 'where the second dielectric layer is under the plurality of dielectric layers, and the circuit layer is under the second dielectric layer, the protective layer is located under the second layer and Located under the second dielectric layer, the material of the second circuit layer includes electroplated copper. Protecting the nitriding (four) between the sound meters, a first between 0.2 micrometers and the second layer of the microlayer is located in the protective layer and below a third junction of the second circuit layer, the third a contact is located at a top end of the second notch, a fourth notch is located in the protective layer and under a fourth contact of the second circuit layer, the fourth contact is located at a top end of the fourth notch; a copper pillar between the first junction and the third junction and the height of the first copper pillar is between 10 micrometers and 15 micrometers, and the lateral maximum dimension of the first copper pillar is between Between 3 micrometers and 5 micrometers, the first copper pillar is connected to the first joint via the first gap and the third joint is connected via the third gap; a first copper pillar is located at the second Between the junction and the fourth junction, and the height of the second copper pillar is between 10 micrometers and 15 micrometers, and the lateral maximum dimension of the second copper pillar is between 3 micrometers and 500 micrometers. The second copper pillar is connected to the second joint via the second gap and via the fourth gap 143023-991027. Doc •10· U/5284 «· · connect the fourth joint; a metal layer between the first copper pillar and the third joint; - tin-containing metal, located in the first copper pillar Between the first contacts; a nickel layer between the tin-containing metal and the first contact, and the first contact is via the layer, the tin-containing winter 3 tin metal, the first copper a pillar and the metal layer connecting the third joint; a polymer layer Between the insulating layer and the protective layer and between the first copper pillar and the second copper pillar, and the polymer layer contacts the second copper pillar and contacts the second copper a cylinder and contacting the insulating layer. 66. The wafer chipping structure of claim 65, wherein the distance between the pair of sides of the semiconductor wafer is less than the distance between a pair of opposite sides of the line component. The wafer package structure of claim 65, wherein the material of the insulating layer comprises Shi Xi. Wherein, wherein the protective layer of the chip package structure as described in claim 65 further comprises a layer of oxidized stone. 69. The chip package structure as claimed in claim 65, wherein the metal layer comprises titanium metal. 70. The wafer sealing structure according to claim 65, wherein the material of the metal layer comprises a tungsten alloy. The wafer package structure of claim 65, wherein the metal layer has a thickness of between 1 μm and 丨 micron. 72. The chip package structure according to claim 65, wherein the 143023-991027.doc 1375284 The structure 'where the structure' is the structure' wherein the material of the tin-containing metal comprises a tin-lead alloy. 73. The wafer package of claim 65, wherein the tin-containing metal material comprises a tin-silver alloy. 74. The wafer package of claim 65, wherein the tin-containing metal material comprises a tin-silver-copper alloy. 75. The wafer encapsulation as described in claim 65 of the patent scope r material containing tin metal does not include lead package structure, package structure, package structure, 76, the wafer polymer layer as described in claim 65 The material includes epoxy. 77. The material of the metal layer of the wafer according to claim 65 of the patent application includes tantalum nitride. 78. The material of the metal layer of the wafer as described in claim 65, comprising a button metal. 79. The material of the wafer package structure as described in claim 65 of the patent scope includes the material of the metal layer including tantalum nitride. 80. The material of the wafer seal structure metal layer as described in claim 65 of the patent scope includes chrome metal. 81. The wafer package structure as described in claim 65, wherein the material of the metal layer comprises a chrome-copper alloy. Further, the method further comprises: wherein the wafer sealing material according to claim 65, wherein the nickel layer has a thickness of between 1 μm and 5 μm. 83. The wafer package of claim 65, wherein the wafer package is between the tin-containing metal and the first copper pillar. 84 'The wafer J structure as described in claim 65, 143023-991027.doc 12 -LJ/JZ04 • 'Factory----------~ II. Horizontal of the second copper cylinder The maximum size ranges from 3 microns to one g. "The center point of the first copper pillar of the chip package structure as described in claim 65 to the second copper pillar 2 is between 5 micrometers and 400 micrometers." "%, as claimed in the patent scope The chip package structure of claim 65, wherein a distance from a center point of the first copper pillar to a center point of the second copper pillar is between 5 micrometers and 1 micrometer; a package structure, wherein the package is Structure, where 87. The wafer circuit component of claim 65, further comprising a capacitor component. 88. The wafer circuit component of claim 65, further comprising a resistive component. 143023-991027.doc 13