TW200723416A - Chip packaging structure and manufacturing process thereof - Google Patents

Chip packaging structure and manufacturing process thereof

Info

Publication number
TW200723416A
TW200723416A TW095115973A TW95115973A TW200723416A TW 200723416 A TW200723416 A TW 200723416A TW 095115973 A TW095115973 A TW 095115973A TW 95115973 A TW95115973 A TW 95115973A TW 200723416 A TW200723416 A TW 200723416A
Authority
TW
Taiwan
Prior art keywords
metal
underfilling
wafer
bump
flow
Prior art date
Application number
TW095115973A
Other languages
Chinese (zh)
Other versions
TWI375284B (en
Inventor
Mou-Shiung Lin
Shih-Hsiung Lin
Hsin-Jung Lo
Original Assignee
Megica Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/124,493 external-priority patent/US8232192B2/en
Application filed by Megica Corp filed Critical Megica Corp
Publication of TW200723416A publication Critical patent/TW200723416A/en
Application granted granted Critical
Publication of TWI375284B publication Critical patent/TWI375284B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention is: deposit a non-flowing underfilling (highly viscous) material and pattern it before the bump jointing process takes place. Such a material does not flow after it is deposited on the wafer. Thus, when it is paved on the wafer, it is typically patterned by printing mask to open up the metal pads. The wafer is then ready for the metal bump attaching process. Note that since no underfilling material is to slime over the metal pad, there is no concern on metal pad contamination. Besides, due to the non-flowing nature of the filling material, the subsequent metal reflowing process does not cause the underfilling material to flow, either. Wire bonding pad thus can be kept clean throughout the reflowing process. As to the tiny space and corners lying between the underfilling material and the body of the metal bump, they are to be filled by the molten metal material during the refllowing process.
TW95115973A 2005-05-05 2006-05-05 Chip packaging structure and manufacturing process thereof TWI375284B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/124,493 US8232192B2 (en) 2004-05-05 2005-05-05 Process of bonding circuitry components

Publications (2)

Publication Number Publication Date
TW200723416A true TW200723416A (en) 2007-06-16
TWI375284B TWI375284B (en) 2012-10-21

Family

ID=48094536

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95115973A TWI375284B (en) 2005-05-05 2006-05-05 Chip packaging structure and manufacturing process thereof

Country Status (1)

Country Link
TW (1) TWI375284B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137587A (en) * 2011-11-30 2013-06-05 台湾积体电路制造股份有限公司 Planarized bumps for underfill control
CN109791921A (en) * 2016-10-06 2019-05-21 金柏科技有限公司 For flip connect on solid-state diffusion engagement the conducting wire with fine spacing processing procedure and structure
US11594509B2 (en) 2016-10-06 2023-02-28 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
US11749595B2 (en) 2016-10-06 2023-09-05 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137587A (en) * 2011-11-30 2013-06-05 台湾积体电路制造股份有限公司 Planarized bumps for underfill control
CN103137587B (en) * 2011-11-30 2016-01-27 台湾积体电路制造股份有限公司 For the planarization projection that underfill controls
US9318455B2 (en) 2011-11-30 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a plurality of bumps on a substrate and method of forming a chip package
CN109791921A (en) * 2016-10-06 2019-05-21 金柏科技有限公司 For flip connect on solid-state diffusion engagement the conducting wire with fine spacing processing procedure and structure
US11594509B2 (en) 2016-10-06 2023-02-28 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
CN109791921B (en) * 2016-10-06 2023-07-25 金柏科技有限公司 Process and structure for solid state diffusion bonding on flip chip interconnects
US11749595B2 (en) 2016-10-06 2023-09-05 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect

Also Published As

Publication number Publication date
TWI375284B (en) 2012-10-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees