CN108022871B - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN108022871B
CN108022871B CN201710081917.2A CN201710081917A CN108022871B CN 108022871 B CN108022871 B CN 108022871B CN 201710081917 A CN201710081917 A CN 201710081917A CN 108022871 B CN108022871 B CN 108022871B
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substrate
passivation layer
metal
forming
layer
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CN108022871A (zh
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施信益
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明公开了一种制造半导体封装的方法。首先，提供一衬底；接着于衬底上形成一第一钝化层；再形成多个沟槽，延伸进入衬底；然后于沟槽中形成金属介层结构；随后于第一钝化层上形成一重分布层结构；于重分布层结构上形成一第二钝化层；之后，于第二钝化层中形成开孔，显露出凸块接垫；接着于凸块接垫上形成第一金属柱；然后于金属柱上安置半导体芯片；再形成一模塑料，覆盖半导体芯片；之后移除衬底，从而显露出第一钝化层及各金属介层结构的突出部分(第二金属柱)；最后，分别于各第二金属柱上直接形成C4凸块。

Description

半导体封装及其制造方法
技术领域
本发明涉及半导体封装技术领域，特别是涉及一种制造具有重分布中介层结构的半导体封装的方法。
背景技术
集成电路(IC)芯片通常先经过封装，再焊接到印刷电路板(PCB)上。集成电路芯片可通过控制崩塌芯片连接(C4)工艺借由多个焊锡凸块连接到封装衬底。
如本领域所已知的，在半导体封装中通常使用具有穿硅通孔(TSV)的中介层衬底(例如硅中介层)来“扇出”集成电路芯片的接点。然而，TSV硅中介层较为昂贵，因此，本领域仍期望提供一种具有中介层的改良半导体封装，其不使用TSV和硅衬底(无TSV的中介层)，而中介层仍然能够提供非常细密的互连间距。
然而，没有TSV的重分布中介层结构厚度较薄，在封装过程中不易处理。例如，中介层上用来进一步连接的接垫开孔通常是利用光刻工艺定义，而厚度较薄的重分布中介层结构容易翘曲，可能导致光刻工艺对不准问题，并因此造成良率降低。由此可知，本领域仍期望提供一种利用这种薄重分布中介层结构来制造半导体封装的方法，同时能够克服上述的困难。
发明内容
本发明的目的在提供一种改良的方法，用于制造具有薄重分布中介层结构的半导体封装，能解决上述背景技术的不足与缺点。
本发明一方面，提出一种制造重分布中介层结构的方法。首先，提供一衬底，包含相对的一第一表面及一第二表面；接着于衬底的第一表面上形成一第一钝化层；再形成多个沟槽，贯通第一钝化层，并延伸进入衬底；然后于沟槽中形成金属介层结构；随后于第一钝化层上形成一重分布层结构；最后，在重分布层结构上形成用于进一步连接到半导体芯片的第一金属柱。于重分布层结构上形成第一金属柱。
本发明一方面，提出一种制造半导体封装的方法。首先，提供一衬底，包含相对的一第一表面及一第二表面；接着于衬底的第一表面上形成一第一钝化层；再形成多个沟槽，贯通第一钝化层，并延伸进入衬底；然后于多个沟槽中形成凸块下金属(UBM)材料，以形成金属介层结构；随后于第一钝化层上形成一重分布层结构；于重分布层结构上形成一第二钝化层；之后，于第二钝化层中形成开孔，显露出重分布层结构的凸块接垫；接着于凸块接垫上分别形成第一金属柱；然后进行一芯片贴合工艺，于第一金属柱上安置半导体芯片；再形成一模塑料，覆盖半导体芯片及第一钝化层；之后通过抛光移除部分衬底；随后进行一湿式蚀刻工艺，移除衬底的剩余部分，以显露出第一钝化层及各金属介层结构的突出部分，从而形成第二金属柱；最后，分别于各第二金属柱上直接形成一连接件(例如焊锡凸块)。
本发明另一方面，提出一种制造半导体封装的方法。首先，提供一衬底，包含相对的一第一表面及一第二表面；接着于衬底的第一表面上形成一第一钝化层；再形成多个沟槽，贯通第一钝化层，并延伸进入衬底；然后于多个沟槽中填入导电材料以形成金属介层结构；随后于第一钝化层上形成一重分布层结构；再于重分布层结构上形成一第二钝化层；之后，于第二钝化层中形成开孔，显露出重分布层结构的凸块接垫；接着于凸块接垫上分别形成第一金属柱；然后将重分布层结构贴合一载板；接着对衬底进行一衬底薄化工艺，移除部分衬底；随后进行一湿式回蚀刻工艺，移除衬底的剩余部分，以显露出第一钝化层及各金属介层结构的突出部分，以及形成第二金属柱；之后于第二金属柱上接合一半导体芯片；再形成一模塑料，覆盖半导体芯片及第一钝化层；接着移除载板，显露出第一金属柱及第二钝化层；最后，分别于各第一金属柱上直接形成一连接件(例如焊锡凸块)。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
附图包括对本发明的实施例提供进一步的理解，及被并入且构成说明书中的一部份。附图说明一些本发明的实施例，并与说明书一起用于解释其原理。
图1至图9是根据本发明的一实施例所绘示的制造半导体封装的示例性方法的剖面图；以及
图10至图20是根据本发明的另一实施例所绘示的制造半导体封装的示例性方法的剖面图。
其中，附图标记说明如下：
10 衬底
10a 第一表面
10b 第二表面
11 第一钝化层
110 沟槽
112 金属介层结构
20 重分布层(RDL)结构
201 介电层
202 绕线层
204 凸块接垫
21 第二钝化层
210 开孔
320 第一金属柱
320a 凸块下金属结构
320b 导电凸块
101 第一半导体芯片
102 第二半导体芯片
400 模塑料
400a 表面
112a 第二金属柱
620 连接件
122 金属介层结构
322 第一金属柱
40 载板
42 黏着层
122a 第二金属柱
622 连接件
具体实施方式
在下文中，加以陈述本发明的具体实施方式，该些具体实施方式可参考相对应的附图，使该些附图构成实施方式的一部分。同时也借由说明，揭露本发明可据以施行的方式。该等实施例已被清楚地描述足够的细节，使本领域技术人员可据以实施本发明。其他实施例亦可被加以施行，且对于其结构上所做的改变仍属本发明所涵盖的范畴。
因此，下文的细节描述将不被视为一种限定，且本发明所涵盖的范畴仅被所附的权利要求书以及其同意义的涵盖范围。
本发明的一或多个实施例将参照附图描述，其中，相同元件符号始终用以表示相同元件，且其中阐述的结构未必按比例所绘制。术语“晶粒”、“芯片”“半导体芯片”及“半导体晶粒”于本说明书中可互换使用。
文中所使用的用语“晶圆”及“衬底”包括任何具有暴露表面的结构，根据本发明，于所述表面上可沉积有一至少层材料，例如，形成例如重分布层的电路结构。用语“衬底”被理解为包括半导体晶圆，但不限于此。用语“衬底”亦可用以指加工过程中的半导体结构，且可包括已被制造在其上的其它层。
请参考图1至图9。图1至图9是根据本发明的一实施例所绘示的制造半导体封装的示例性方法的剖面图，其中，图1至图4说明制造薄重分布中介层结构的示例性方法。
如图1所示，首先，提供一衬底10。根据本发明一实施例，衬底10可以包含硅或III-V半导体，但不限于此。例如，根据本发明一实施例，衬底10可以是晶圆形状的硅衬底。衬底10具有相对的第一表面10a和第二表面10b。第一钝化层11沉积在衬底10的第一表面10a上。第一钝化层11可以包含介电层。例如，第一钝化层11可以包含氮化硅、氧化硅、氮氧化硅、聚酰亚胺或其任何组合。
如图2所示，利用光刻、机械钻孔、激光钻孔、反应离子蚀刻(RIE)或其组合，形成完全贯通第一钝化层11的多个沟槽110，各沟槽110并延伸进入衬底10。各沟槽110从第一表面10a深入部分衬底10的厚度，但各沟槽110不贯穿衬底10。根据本发明一实施例，例如，各沟槽110的深度不超过50微米。
根据本发明一实施例，沟槽110可以具有相同的宽度。根据本发明另一实施例，沟槽110可以具有不同的宽度。
随后，如图3所示，于沟槽110中填入一导电材料，从而形成金属介层结构112。导电材料可包含铜、铬、镍、铝、金、银、钨、钛或氮化钛，但不限于此。导电材料可通过使用电解电镀、无电电镀、蒸镀、溅射、印刷或其他合适的金属沉积工艺来形成。
根据本发明一实施例，导电材料完全填满沟槽110。导电材料可具有包含例如黏着层、一阻挡层、一晶种层、一湿润层或以上组合的多层结构。根据本发明一实施例，在衬底10和填入到沟槽110中的导电材料之间不形成介电衬层。
应理解的是，在沉积导电材料之后，可以通过化学机械抛光(CMP)方法去除或平坦化第一钝化层11上多余的导电材料。在CMP之后，显露第一钝化层11的上表面。
随后，如图4所示，于第一钝化层11上形成重分布层(RDL)结构20。根据本发明的实施例，RDL结构20可以包含至少一个介电层201和至少一个绕线层202。应理解的是，RDL结构20可以包含多层介电材料和多层绕线层，如图所示。
根据本发明一实施例，介电层201可包含聚酰亚胺、苯环丁烯(BCB)等。根据本发明另一实施例，介电层201可包含氧化硅、氮化硅、氮氧化硅，但不限于此。绕线层202可以包含铜、铝或合适的金属合金，但不限于此。绕线层202可以具有细间距镶嵌分布结构，例如铜镶嵌结构。
根据本发明一实施例，多个凸块接垫204可形成在RDL结构20中并电连接至绕线层202。根据本发明一实施例，金属介层结构112电连接至绕线层202。
根据本发明一实施例，于重分布层结构20上形成一第二钝化层21。分别通过于第二钝化层21中的开孔210显露出凸块接垫204。根据本发明一实施例，第二钝化层21可以包含介电层，但不限于此。例如，第二钝化层21可以包含氮化硅、氧化硅、氮氧化硅、聚酰亚胺或以上组合。根据本发明另一实施例，第二钝化层21可以包含防焊层，但不限于此。
在各凸块接垫204上形成多个第一金属柱320，例如微凸块等。根据本发明一实施例，各第一金属柱320可包含凸块下金属结构320a和覆盖在凸块下金属结构320a上的导电凸块320b。导电凸块320b可以包含一焊锡凸块或一金属凸块。例如，第一金属柱320可具有一凸块间距，其与半导体芯片的有源面上的输入/输出(I/O)垫间距相匹配。例如，第一金属柱320可以包含铜、金或任何合适的金属。可理解的是，第一金属柱320可另包含金属处理层和形成在第一金属柱320上的焊料盖(未明确示出)。
如图5所示，进行一芯片贴合工艺，于第一金属柱320上安置至少一第一半导体芯片101及至少一第二半导体芯片102。第一半导体芯片101和第二半导体芯片102可以是覆晶芯片，其有源面面向下朝向第一金属柱320。第一半导体芯片101和第二半导体芯片102通过第一金属柱320电连接至RDL结构20。
尽管在附图中未绘示，但是应当理解，在第一半导体芯片101和第二半导体芯片102上的对应接合焊垫上已形成有微凸块。当第一半导体芯片101和第二半导体芯片102与RDL结构20接合时，使第一半导体芯片101和第二半导体芯片102上对应接合焊垫上的微凸块与多个第一金属柱320对准。
第一半导体芯片101和第二半导体芯片102是具有一些功能的有源集成电路芯片，例如GPU(图形处理单元)、CPU(中央处理单元)、内存芯片等。根据本发明一实施例，第一半导体芯片101和第二半导体芯片102可以一起设置在同一封装中，并且可以是具有特定功能的不同芯片。另外，可以选择在各芯片下方使用底胶(图未示)。
如图6所示，形成一模塑料400覆盖第一半导体芯片101、第二半导体芯片102和第二钝化层21的上表面。随后，可以对模塑料400进行一固化处理。根据本发明一实施例，模塑料400可以包含环氧树脂和二氧化硅填料的混合物，但不限于此。
后续，可选择抛光模塑料400的上部，使第一半导体芯片101及第二半导体芯片102的无源面被显露出来，且与模塑料400的一表面400a共平面。
如图7所示，在形成模塑料400之后，对衬底10进行一衬底薄化工艺，移除部分厚度的所述衬底。例如，可以对衬底10的第二表面10b进行抛光工艺以移除衬底10的大部分厚度。在抛光工艺完成之后，衬底10的剩余部分仍然覆盖金属介层结构112且金属介层结构112在此时不会被显露出来。
如图8所示，在衬底薄化工艺之后，进行一硅湿式回蚀刻工艺，移除衬底10的剩余部分，以显露出第一钝化层11及各金属介层结构112的突出部分。在RDL结构20的底侧(或PCB侧)，金属介层结构112的突出部分构成第二金属柱112a。根据本发明一实施例，第二金属柱112a可以为凸块下金属(UBM)凸块。
或者，可在完成衬底薄化工艺之后暴露出金属介层结构112。在这种情况下，可以省略前述的硅湿式回蚀刻工艺。
如图9所示，多个连接件620分别直接形成在各第二金属柱112a上。多个连接件620可包含焊锡凸块或C4凸块。连接件620可包含金、银、铜、镍、钨、锡或以上组合。连接件620可具有与封装衬底或印刷电路板(PCB)的垫间距相匹配的凸块间距。随后，进行一切割工艺以将各半导体封装彼此分离。
根据本发明一实施例，连接件620可以通过电镀或落球法形成在第二金属柱112a上，但不限于此。根据本发明另一实施例，连接件620可以仅形成在各第二金属柱112a的上表面上。
本发明的方法的优点在于，连接件620的形成不涉及光刻工艺，因此可以避免晶圆级元件翘曲而导致的开口对不准的问题，如此改善封装工艺余裕及封装工艺良率。
此外，本发明的一个技术特征在于，用于在PCB侧上形成焊锡凸块或C4凸块的第二金属柱112a及第一金属柱320是在去除衬底10之前就已经制造完成。
请参考图10至图20。图10至图20是根据本发明的另一实施例所绘示的制造半导体封装的示例性方法的剖面图，其中相同的元件符号表示相同的元件、层或区域。图10至图13说明制造薄重分布中介层结构的示例性方法。
首先，同样地，如图10所示，提供一衬底10。根据本发明一实施例，衬底10可以包含硅或III-V半导体，但不限于此。例如，根据本发明一实施例，衬底10可以是晶圆形状的硅衬底。衬底10具有相对的第一表面10a和第二表面10b。第一钝化层11沉积在衬底10的第一表面10a上。第一钝化层11可以包含介电层。例如，第一钝化层11可以包含氮化硅、氧化硅、氮氧化硅、聚酰亚胺或其任何组合。
如图11所示，利用光刻、机械钻孔、激光钻孔、反应离子蚀刻(RIE)或其组合，形成完全贯通第一钝化层11的多个沟槽110，各沟槽110并延伸进入衬底10。各沟槽110从第一表面10a深入部分衬底10的厚度，但各沟槽110不贯穿衬底10。根据本发明一实施例，例如，各沟槽110的深度不超过50微米。根据本发明另一实施例，沟槽110可以具有不同的宽度。
随后，如图12所示，于沟槽110中填入一导电材料，从而形成金属介层结构122。导电材料可包含铜、铬、镍、铝、金、银、钨、钛或氮化钛，但不限于此。导电材料可通过使用电解电镀、无电电镀、蒸镀、溅射、印刷或其他合适的金属沉积工艺来形成。根据本发明一实施例，导电材料完全填满沟槽110。
应理解的是，在沉积导电材料之后，可以通过化学机械抛光(CMP)方法去除或平坦化第一钝化层11上多余的导电材料。在CMP之后，显露第一钝化层11的上表面。
随后，如图13所示，于第一钝化层11上形成重分布层(RDL)结构20。根据本发明的实施例，RDL结构20可以包含至少一个介电层201和至少一个绕线层202。应理解的是，RDL结构20可以包含多层介电材料和多层绕线层，如图所示。
根据本发明一实施例，介电层201可包含聚酰亚胺、苯环丁烯(BCB)等。根据本发明另一实施例，介电层201可包含氧化硅、氮化硅、氮氧化硅，但不限于此。绕线层202可以包含铜、铝或合适的金属合金，但不限于此。绕线层202可以具有细间距镶嵌布线结构，例如铜镶嵌结构。
根据本发明一实施例，多个凸块接垫204可形成在RDL结构20中并电连接至绕线层202。根据本发明一实施例，金属介层结构122电连接至绕线层202。
根据本发明一实施例，于重分布层结构20上形成一第二钝化层21。分别通过于第二钝化层21中的开孔210显露出凸块接垫204。根据本发明一实施例，第二钝化层21可以包含介电层，但不限于此。例如，第二钝化层21可以包含氮化硅、氧化硅、氮氧化硅、聚酰亚胺或以上组合。根据本发明另一实施例，第二钝化层21可以包含防焊层，但不限于此。
在各凸块接垫204上形成多个第一金属柱322。例如，第一金属柱322可以作为用于着陆焊锡凸块或锡球的UBM凸块，且可具有与封装衬底或印刷电路板(PCB)的垫间距相匹配的凸块间距。例如，第一金属柱322可以包含铜、铬、镍、铝、金、银、钨、钛或氮化钛，或任何合适的金属。
根据本发明一实施例，第一金属柱322可以从第二钝化层21的上表面突出。
如图14所示，进行一载板接合工艺。载板40可以通过使用黏着层42接合到RDL结构20上。载板40可以是玻璃衬底、金属片或硅衬底，但不限于此。
如图15所示，在进行一载板接合工艺之后，对衬底10进行一衬底薄化工艺，移除部分厚度的所述衬底。例如，可以对衬底10的第二表面10b进行抛光工艺以移除衬底10的大部分厚度。在抛光工艺完成之后，衬底10的剩余部分仍然覆盖金属介层结构122且金属介层结构122在此时不会被显露出来。
如图16所示，在衬底薄化工艺之后，进行一硅湿式回蚀刻工艺，移除衬底10的剩余部分，以显露出第一钝化层11及各金属介层结构122的突出部分。在RDL结构20的底侧(或芯片侧)，金属介层结构122的突出部分构成第二金属柱122a。根据本发明一实施例，第二金属柱122a可以用于连接到芯片的微凸块。
或者，可在完成衬底薄化工艺之后暴露出金属介层结构122。在这种情况下，可以省略前述的硅湿式回蚀刻工艺。
如图17所示，随后，进行一芯片贴合工艺，于第二金属柱122a上安置至少一第一半导体芯片101及至少一第二半导体芯片102。第一半导体芯片101和第二半导体芯片102可以是覆晶芯片，其有源面面向下朝向第二金属柱122a。第一半导体芯片101和第二半导体芯片102通过第二金属柱122a电连接至RDL结构20。
第一半导体芯片101和第二半导体芯片102是具有一些功能的有源集成电路芯片，例如GPU(图形处理单元)、CPU(中央处理单元)、内存芯片等。根据本发明一实施例，第一半导体芯片101和第二半导体芯片102可以一起设置在同一封装中，并且可以是具有特定功能的不同芯片。另外，可以选择在各芯片下方使用底胶(图未示)。
如图18所示，形成一模塑料400覆盖第一半导体芯片101、第二半导体芯片102和第一钝化层11的上表面。随后，可以对模塑料400进行一固化处理。根据本发明一实施例，模塑料400可以包含环氧树脂和二氧化硅填料的混合物，但不限于此。
后续，可选择抛光模塑料400的上部，使第一半导体芯片101及第二半导体芯片102的无源面被显露出来，且与模塑料400的一表面400a共平面。
如图19所示，在形成模塑料400之后，去除载板40和黏着层42，从来显露出第一金属柱322和第二钝化层21。
如图20所示，多个连接件622分别直接形成在各第一金属柱322上。多个连接件622可包含焊锡凸块或C4凸块。连接件622可包含金、银、铜、镍、钨、锡或以上组合。随后，进行一切割工艺以将各半导体封装彼此分离。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (19)

1.一种用于制造半导体装置封装的方法，所述方法包含：
提供一衬底，所述衬底包含相对的一第一表面及一第二表面；
形成延伸进入所述衬底的所述第一表面的金属通孔结构，其包含：
于所述衬底的所述第一表面上形成一第一钝化层；
形成贯通所述第一钝化层并部分地延伸进入所述衬底的多个沟槽；以及
于所述多个沟槽中填入一导电材料；
于所述衬底上形成一重分布层(RDL)结构以电连接所述金属通孔结构；
于所述重分布层结构上形成第一金属柱；
执行一芯片贴合工艺，以于所述第一金属柱上安置半导体芯片；
去除所述衬底，显露出所述金属通孔结构超出所述第一钝化层的突出部分，以形成第二金属柱，其包含：
对所述衬底执行一衬底薄化工艺，以去除所述衬底的一部分；以及
执行一湿式回蚀刻工艺，去除所述衬底的剩余部分，以显露出所述第一钝化层和各所述金属通孔结构的所述突出部分；以及
于所述第二金属柱上形成连接件。
2.根据权利要求1所述的方法，其进一步包含将各所述沟槽形成为不大于50微米的深度。
3.根据权利要求1所述的方法，其进一步包含将所述沟槽形成为大体相同的直径。
4.根据权利要求1所述的方法，其进一步包含将所述沟槽形成为不同的直径。
5.根据权利要求1所述的方法，其中于所述沟槽填入导电材料包含于所述沟槽填入铜、铬、镍、铝、金、银、钨、钛或氮化钛。
6.根据权利要求1所述的方法，其中于所述沟槽填入导电材料包含于所述沟槽中形成一多层结构，所述多层结构包含一黏着层、一阻挡层、一晶种层、一湿润层或其组合。
7.根据权利要求1所述的方法，其中于所述重分布层结构上形成第一金属柱包含以下步骤：
于所述重分布层结构上形成一第二钝化层；
于所述第二钝化层中形成接垫开孔，以显露出所述重分布层结构的凸块接垫；以及
分别于所述凸块接垫上形成所述第一金属柱。
8.根据权利要求7所述的方法，其中形成所述第一钝化层及所述第二钝化层包含由氮化硅、氧化硅、氮氧化硅、聚酰亚胺或其组合形成。
9.根据权利要求1所述的方法，其中提供衬底包含提供硅衬底。
10.根据权利要求1所述的方法，其进一步包含：
形成一模塑料，以覆盖所述半导体芯片及所述第一钝化层；以及
抛光所述模塑料，以显露出所述半导体芯片的无源面，且所述模塑料的表面与所述无源面共平面。
11.根据权利要求1所述的方法，其中所述第一金属柱形成为微凸块且所述第二金属柱形成为凸块下金属(UBM)凸块。
12.根据权利要求11所述的方法，其中形成所述第一金属柱包含形成一凸块下金属结构及形成一盖在所述凸块下金属结构上的导电凸块。
13.根据权利要求12所述的方法，其中形成所述导电凸块包含形成一焊锡凸块或一金属凸块。
14.根据权利要求1所述的方法，其中形成所述连接件包含形成焊锡凸块或控制崩塌芯片连接凸块。
15.一种用于制造半导体封装的方法，其包含：
提供一衬底，其具有相对的一第一表面和一第二表面；
于所述衬底的所述第一表面上形成第一钝化层；
形成金属通孔结构，其贯通所述第一钝化层并延伸进入所述衬底的所述第一表面；
于所述衬底上形成一重分布层(RDL)结构以电连接所述金属通孔结构；
于所述重分布层结构上形成第一金属柱；
将所述重分布层结构贴合一载板；
去除所述衬底，显露出所述金属通孔结构超出所述第一钝化层的突出部分，以形成第二金属柱；
于所述第二金属柱上安置一半导体芯片；
移除所述载板，以显露出所述第一金属柱；以及
于所述第一金属柱上直接形成一连接件。
16.根据权利要求15所述的方法，其中去除所述衬底，显露出各所述金属通孔结构的突出部分包含以下步骤：
对所述衬底执行一衬底薄化工艺，移除部分所述衬底；以及
执行一湿式回蚀刻工艺，移除所述衬底的剩余部分，以显露出所述第一钝化层及各所述金属通孔结构的所述突出部分。
17.根据权利要求16所述的方法，其进一步包含：
形成一模塑料，覆盖所述半导体芯片及所述第一钝化层；以及
抛光所述模塑料，以显露出所述半导体芯片的无源面，且所述模塑料的表面与所述无源面共平面。
18.根据权利要求15所述的制造半导体封装的方法，其中所述第一金属柱形成为凸块下金属凸块且所述第二金属柱形成为微凸块。
19.根据权利要求15所述的方法，其中于所述重分布层结构上形成第一金属柱包含以下步骤：
于所述重分布层结构上形成一第二钝化层；
于所述第二钝化层中形成接垫开孔，以显露出所述重分布层结构的凸块接垫；以及
分别于所述凸块接垫上形成所述第一金属柱。
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