TWI587463B - 半導體封裝結構及其製法 - Google Patents

半導體封裝結構及其製法 Download PDF

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Publication number
TWI587463B
TWI587463B TW103139186A TW103139186A TWI587463B TW I587463 B TWI587463 B TW I587463B TW 103139186 A TW103139186 A TW 103139186A TW 103139186 A TW103139186 A TW 103139186A TW I587463 B TWI587463 B TW I587463B
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Taiwan
Prior art keywords
layer
semiconductor package
package structure
dielectric layer
circuit layer
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TW103139186A
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English (en)
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TW201618256A (zh
Inventor
蕭惟中
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103139186A priority Critical patent/TWI587463B/zh
Priority to CN201410673881.3A priority patent/CN105633055B/zh
Priority to US14/695,125 priority patent/US9564390B2/en
Publication of TW201618256A publication Critical patent/TW201618256A/zh
Priority to US15/383,362 priority patent/US10109572B2/en
Application granted granted Critical
Publication of TWI587463B publication Critical patent/TWI587463B/zh

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Description

半導體封裝結構及其製法
本發明係關於一種半導體封裝結構及其製法，特別是指一種形成突出構件於線路層上之半導體封裝結構及其製法。
隨著電子產業的蓬勃發展，電子產品亦逐漸邁向多功能及高性能之發展趨勢。為滿足半導體封裝結構朝向高積集度(integration)及微型化(miniaturization)之封裝需求，該半導體封裝結構內之線路層之電性接觸墊之寬度也愈來愈小。
但是，當透過複數導電凸塊將晶片接置於該線路層之電性接觸墊上，並對該些導電凸塊進行迴銲(reflow)製程時，該些導電凸塊會形成軟塌狀態與外溢而影響電性連接，亦導致相鄰之兩導電凸塊容易互相電性連接而造成短路。再者，該電性接觸墊之接觸面係為平面，使得該電性接觸墊與該導電凸塊之接觸面積較小，故易導致彼此之間的接合強度不足而降低產品之信賴性。
第1A圖至第1D圖係繪示習知技術之半導體封裝結構 1及其製法之剖視示意圖。
如第1A圖所示，先提供一承載板10，並形成具有複數電性接觸墊111之線路層11於該承載板10上。
如第1B圖所示，形成具有相對之第一表面12a與第二表面12b之第一封裝膠體12於該承載板10上以包覆該線路層11，且該第一封裝膠體12之第二表面12b係面向該承載板10。
如第1C圖所示，將第1B圖之整體結構上下倒置，並移除該承載板10，再將晶片13透過複數導電凸塊14接置於該線路層11之電性接觸墊111上。
如第1D圖所示，形成第二封裝膠體15於該第一封裝膠體12之第二表面12b上，以包覆該第二表面12b之線路層11、晶片13及導電凸塊14。同時，自該第一封裝膠體12之第一表面12a形成複數開孔121以分別外露出部分該線路層11，並植接複數銲球16於該些開孔121內以電性連接該線路層11。
惟，上述半導體封裝結構1之缺點在於：將第1C圖之晶片13透過複數導電凸塊14接置於線路層11之複數電性接觸墊111上，並對該些導電凸塊14進行迴銲製程時，該些導電凸塊14會形成軟塌狀態，使得該些導電凸塊14之導電材料(如銲錫)往外溢出而影響電性連接，亦導致相鄰之兩導電凸塊14容易互相電性連接而造成短路。再者，該電性接觸墊111之接觸面112係為平面，故該電性接觸墊111與該導電凸塊14之接觸面積較小，使得該導電凸塊 14與該線路層11之間容易產生接合強度不足之問題，進而降低後續產品之信賴性。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
本發明係提供一種半導體封裝結構，其包括：介電層，係具有相對之第一表面與第二表面；第一線路層，係嵌埋於該介電層內並令該第一線路層之一表面外露於該介電層之第一表面；複數導電柱，係嵌埋於該介電層內並令該導電柱一端外露於該介電層之第二表面，且該些導電柱係分別電性連接該第一線路層；第二線路層，係形成於該介電層之第二表面上，並電性連接外露於該介電層之第二表面之該些導電柱；以及複數突出構件，係分別形成於該介電層之第一表面之第一線路層上。
該介電層係為封裝膠體或預浸體。該第一線路層係具有複數第一電性接觸墊，供該些突出構件分別形成於該些第一電性接觸墊上。
該突出構件與該第一電性接觸墊可為相同材質所形成者或一體成形者，而該突出構件之寬度可小於或等於該第一電性接觸墊之寬度，且該突出構件可為另一導電柱或一導電跡線之銲墊。
該第二線路層係具有複數第二電性接觸墊，供該導電柱之相對第一端部與第二端部分別電性連接該第一線路層及該第二電性接觸墊。
該半導體封裝結構可包括絕緣保護層，係形成於該介電層之第二表面上以包覆該第二線路層，並外露部分該第二線路層。
本發明復提供一種半導體封裝結構之製法，其包括：提供一具有相對之第一表面與第二表面之介電層，該介電層內係嵌埋有一表面外露於該介電層之第一表面之第一線路層、及複數一端外露於該介電層之第二表面並電性連接該第一線路層之導電柱，且外露於該介電層之第一表面之第一線路層上係形成有複數突出構件；以及形成第二線路層於該介電層之第二表面上以電性連接外露於該介電層之第二表面之該些導電柱。
該半導體封裝結構之製法復包括下列步驟以提供該介電層：準備一具有相對之第一表面與第二表面之承載板；形成複數凹部於該承載板之第二表面；形成該些突出構件於該些凹部；形成該第一線路層於該承載板之第二表面；形成該些導電柱於該第一線路層上；以及形成該介電層。該些突出構件之下表面可齊平於該承載板之第二表面。
該第一線路層之製程可包括：形成一第一阻層於該承承載板之第二表面及該突出構件之下表面上；形成複數第一溝槽於該第一阻層；以及形成該第一線路層於該些第一溝槽內，且該第一線路層具有複數第一電性接觸墊，以分別電性連接該些突出構件之下表面。
該些導電柱之製程可包括：形成一具有複數開孔之第二阻層於該第一阻層與該第一線路層上，且該些開孔係分 別外露出部分該第一線路層；以及形成該些導電柱於該些開孔內，且該些導電柱之第一端部係分別電性連接外露於該些開孔之第一線路層。
該介電層之製程可包括：移除該第一阻層與該第二阻層以外露出該第一線路層及導電柱；以及形成該介電層於該承載板上，以包覆該第一線路層及導電柱並外露出該些導電柱之第二端部。
該第二線路層之製程可包括：形成一具有複數第二溝槽之第三阻層於該介電層之第二表面上，且該些第二溝槽係外露出該些導電柱之第二端部及部分該介電層之第二表面；以及形成該第二線路層於該些第二溝槽內，且該第二線路層之複數第二電性接觸墊係分別電性連接該些導電柱之第二端部。
該半導體封裝結構之製法可包括：移除該第三阻層，以外露出該介電層之第二表面及該第二線路層；以及形成絕緣保護層於該介電層之第二表面上，以包覆該第二線路層並外露部分該第二線路層。
該半導體封裝結構之製法可包括：形成一具有至少一開口之框體於該承載板之第一表面上；依據該框體之開口移除部分該承載板；以及進行切單作業。
該半導體封裝結構及其製法可包括：形成第一表面處理層於該第一線路層與該些突出構件之接觸面上，或者形成第二表面處理層於該第二線路層上。
該半導體封裝結構及其製法可包括：將半導體元件透 過複數第一導電元件接置於該些突出構件上，且該些第一導電元件係分別包覆該些突出構件之接觸面，該第一導電元件可為凸塊。
該半導體封裝結構及其製法可包括：形成絕緣材於該介電層之第一表面與該半導體元件之間，以包覆該第一線路層及該些第一導電元件，且該絕緣材可為底膠或封裝膠體。
該半導體封裝結構及其製法可包括：形成複數第二導電元件於該第二表面處理層上以分別電性連接該第二線路層。
由上可知，本發明之半導體封裝結構及其製法中，主要係在第一線路層之複數第一電性接觸墊上形成複數具有立體之接觸面(如上表面和側表面)之突出構件，以透過複數第一導電元件將半導體元件(如晶片)接置於該些突出構件上並包覆該些接觸面。
藉此，該些突出構件不會於迴銲製程中形成軟塌狀態，故可避免該些第一導電元件之導電材料(如銲錫)往外溢出而影響電性連接之狀況，亦可免除相鄰之兩第一導電元件互相電性連接而形成短路之情形。同時，該些突出構件具有較大的接觸面積，故可提升該第一導電元件與該第一線路層之第一電性接觸墊間之接合強度，從而提高後續產品之信賴性。
1、2‧‧‧半導體封裝結構
10、20‧‧‧承載板
11‧‧‧線路層
111‧‧‧電性接觸墊
112、221‧‧‧接觸面
12‧‧‧第一封裝膠體
12a、27a‧‧‧第一表面
12b、27b‧‧‧第二表面
121、251‧‧‧開孔
13‧‧‧晶片
14‧‧‧導電凸塊
15‧‧‧第二封裝膠體
16‧‧‧銲球
20a‧‧‧第一表面
20b‧‧‧第二表面
201‧‧‧凹部
21‧‧‧晶種層
22‧‧‧突出構件
220‧‧‧下表面
23‧‧‧第一阻層
231‧‧‧第一溝槽
24‧‧‧第一線路層
241‧‧‧第一電性接觸墊
25‧‧‧第二阻層
26‧‧‧導電柱
26a‧‧‧第一端部
26b‧‧‧第二端部
27‧‧‧介電層
28‧‧‧第三阻層
281‧‧‧第二溝槽
29‧‧‧第二線路層
291‧‧‧第二電性接觸墊
292‧‧‧側表面
30‧‧‧絕緣保護層
31‧‧‧框體
311‧‧‧開口
32‧‧‧第一表面處理層
33‧‧‧第二表面處理層
34‧‧‧半導體元件
35‧‧‧第一導電元件
36‧‧‧第二導電元件
37‧‧‧絕緣材
S1‧‧‧移除線
S2‧‧‧切割線
第1A圖至第1D圖係繪示習知技術之半導體封裝結構 及其製法之剖視示意圖；以及第2A圖至第2Q圖係繪示本發明之半導體封裝結構及其製法之剖視示意圖，其中，第2L'圖為第2L圖之另一態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。
同時，本說明書中所引用之如「上」、「一」、「第一」、「第二」、「表面」、「接觸面」或「端部」等用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A圖至第2Q圖係繪示本發明之半導體封裝結構2及其製法之剖視示意圖，其中，第2L'圖為第2L圖之另一態樣。
如第2A圖所示，先準備一具有相對之第一表面20a 與第二表面20b之承載板20。該承載板20可為基板、中介板、金屬板或不鏽鋼板等。
如第2B圖所示，以蝕刻或雷射鑽孔等方式，形成複數凹部201於該承載板20之第二表面20b。
如第2C圖所示，以濺鍍或其他方式，形成晶種層(seed layer)21於該承載板20之第二表面20b及該些凹部201之壁面(如內壁和底面)上。該晶種層21可為導電層等。
如第2D圖所示，形成複數突出構件22於該些凹部201之晶種層21上，且該些突出構件22之下表面220係齊平於該晶種層21或該承載板20之第二表面20b。該突出構件22可為導電柱(如銅柱)或導電跡線之銲墊等。
如第2E圖所示，形成一第一阻層23於該第二表面20b之晶種層21及該突出構件22之下表面220上，並於該第一阻層23形成複數第一溝槽231。
接著，形成具有複數第一電性接觸墊241之第一線路層24於該些第一溝槽231內，且該些第一電性接觸墊241係分別電性連接該些突出構件22之下表面220，俾使該第一線路層24上形成有該些突出構件22。
在本實施例中，該些突出構件22與該第一線路層24係先後形成或分別成形，並可為相同材質或不同材質。但在其他實施例中，該些突出構件22與該第一線路層24亦可同時形成或一體成形，並可為相同材質。
如第2F圖所示，形成一具有複數開孔251之第二阻層25於該第一阻層23與該第一線路層24上，且該些開孔251 係分別外露出部分該第一線路層24。
接著，形成複數具有第一端部26a與第二端部26b之導電柱26於該些開孔251內，且該些導電柱26之第一端部26a係分別電性連接外露於該些開孔251之第一線路層24。該導電柱26可為金屬柱(如銅柱)等，且該導電柱26可為嵌埋或填充導電材料或金屬材料於該第二阻層25之開孔251內所形成之。
如第2G圖所示，移除第2F圖之第一阻層23與第二阻層25，以外露出該晶種層21、第一線路層24及導電柱26。
如第2H圖所示，形成一具有相對之第一表面27a與第二表面27b之介電層27於該該承載板20之第二表面20b上，以包覆該第一線路層24及該些導電柱26並外露出該些導電柱26之第二端部26b，且該介電層27可為封裝膠體或預浸體(prepreg)。藉此，可使該介電層27內嵌埋有該第一線路層24及該些導電柱26，並使該第一線路層24與該些導電柱26之第二端部26b分別外露於該介電層27之第一表面27a及第二表面27b。
如第2I圖所示，形成一具有複數第二溝槽281之第三阻層28於該介電層27之第二表面27b上，且該些第二溝槽281係外露出該些導電柱26之第二端部26b及部分該介電層27之第二表面27b。
接著，形成一具有複數第二電性接觸墊291之第二線路層29於該些第二溝槽281所外露之介電層27之第二表 面27b上，且該些第二電性接觸墊291係分別電性連接該些導電柱26之第二端部26b。
如第2J圖所示，移除第21圖之第三阻層28，以外露出該介電層27之第二表面27b及該第二線路層29之側表面292。
接著，形成絕緣保護層30(如防銲層)於該介電層27之第二表面27b上，以包覆該第二線路層29並外露出部分該第二線路層29。
在本實施例中，該絕緣保護層30之高度係高於該第二線路層29之高度。但在其他實施例中，該絕緣保護層30之高度亦可等於該第二線路層29之高度，以使該絕緣保護層30齊平於該第二線路層29。
如第2K圖所示，可對應於例如該第一線路層24之外側或周圍，設置一具有至少一開口311之框體31於該承載板20之第一表面20a上。該框體31之形狀可依據該開口311之數量而構成口字形、田字形或網狀等，且該框體31之材質可為金屬材料或防蝕材料以防止蝕刻。
如第2L圖所示，藉由蝕刻或其他方式，並依據第2K圖之開口311與移除線S1，自該框體31之開口311移除部分該承載板20，以外露出該晶種層21。
在其他實施例中，本發明亦可不必形成有該晶種層21，從而直接外露出該介電層27之第一表面27a、第一線路層24、及突出構件22之接觸面221(如上表面和側表面)。
如第2L'圖所示，係為第2L圖之另一態樣。在第2L' 圖中，本發明可不必設置有第2K圖之框體31，從而直接移除該承載板20以外露出該晶種層21。除此之外，第2L'圖之後續製程均可類似於下列第2M圖至第2Q圖所述之技術內容，故不再重覆敘述。
如第2M圖所示，係接續上述第2L圖，並移除該開口311內之晶種層21，以外露出該開口311內之介電層27之第一表面27a、第一線路層24與突出構件22之接觸面221。
如第2N圖所示，形成第一表面處理層32(如抗氧化層)於該第一線路層24與該些突出構件22之接觸面221上，亦可形成第二表面處理層33(如抗氧化層)於該第二線路層29上。
如第2O圖所示，依據第2N圖之切割線S2，自該框體31之開口311對第2N圖之整體結構進行切單(singulation)作業，以形成複數個如第2O圖所示之半導體封裝結構2。
如第2P圖所示，以覆晶(filp chip)方式將半導體元件34(如晶片)透過複數第一導電元件35(如凸塊)接置於該些突出構件22上，且該些第一導電元件35係分別包覆該些突出構件22之接觸面221(如上表面和側表面)上之第一表面處理層32，或再包覆該些第一電性接觸墊241上之第一表面處理層32。同時，可形成複數第二導電元件36(如銲球)於該第二表面處理層33上，以分別電性連接該第二線路層29之複數第二電性接觸墊291。
在其他實施例中，本發明亦可先接置該半導體元件34於該些突出構件22上，再對該半導體封裝結構2進行切單 作業。而且，本發明也可不必形成有該第一表面處理層32與該第二表面處理層33，從而直接將該些第一導電元件35包覆該些突出構件22之接觸面221或再包覆該些第一電性接觸墊241，並直接將該些第二導電元件36形成於該些第二電性接觸墊291上。
如第2Q圖所示，形成絕緣材37於該介電層27之第一表面27a與該半導體元件34之間，以包覆該第一表面處理層32及該些第一導電元件35。在其他實施例中，當未形成有該第一表面處理層32時，該絕緣材37可直接包覆該第一線路層24。該絕緣材37可為底膠或封裝膠體。
本發明復提供一種半導體封裝結構2，如第2O圖至第2Q圖所示。該半導體封裝結構2主要包括介電層27、第一線路層24、複數導電柱26、第二線路層29以及複數突出構件22。
該介電層27係具有相對之第一表面27a與第二表面27b，且該介電層27可為封裝膠體或預浸體。該第一線路層24係嵌埋於該介電層27內並令該第一線路層24之一表面外露於該介電層27之第一表面27a，且該第一線路層24係具有複數第一電性接觸墊241。
該些導電柱26係嵌埋於該介電層27內並令該導電柱26之一端外露於該介電層27之第二表面27b，各該導電柱26係具有相對之第一端部26a與第二端部26b，而該第一端部26a係電性連接該第一線路層24，且該導電柱26可為金屬柱(如銅柱)等。
該第二線路層29係形成於該介電層27之第二表面27b上，並電性連接外露於該第二表面27b之該些導電柱26，且該第二線路層29係具有複數第二電性接觸墊291，該導電柱26之第二端部26b係電性連接該第二電性接觸墊291。
該些突出構件22係分別形成於該介電層外27之第一表面27a之第一線路層24之該些第一電性接觸墊241上，各該突出構件22係具有接觸面221，該接觸面221可包括該突出構件22上表面和側表面，且該突出構件22之寬度可小於或等於該第一電性接觸墊241之寬度。同時，該突出構件22與該第一電性接觸墊241可為相同材質或不同材質所形成者，並可為一體成形或分別成形者，且該突出構件22可為導電柱(如銅柱)或導電跡線之銲墊等。
該半導體封裝結構2可包括半導體元件34(如晶片)，係以覆晶方式並透過複數第一導電元件35接置於該些突出構件22上，且該些第一導電元件35係分別包覆該些突出構件22之接觸面221。該第一導電元件35係為凸塊。
該半導體封裝結構2可包括第一表面處理層32(如抗氧化層)，係形成於該第一線路層24及該些突出構件22之接觸面221上。
該些第一導電元件35係分別包覆該些突出構件22之接觸面221(如上表面和側表面)之第一表面處理層32，或再包覆該些第一電性接觸墊241之第一表面處理層32。
在其他實施例中，本發明亦可不必形成有該第一表面處理層32，從而直接將該些第一導電元件35包覆該些突 出構件22之接觸面221、或再包覆該些第一電性接觸墊241。
該半導體封裝結構2可包括第二表面處理層33(如抗氧化層)，係形成於該第二線路層29上。
該半導體封裝結構2可包括絕緣保護層30，係形成於該介電層27之第二表面27b上以包覆該第二線路層29。
該半導體封裝結構2可包括複數第二導電元件36，係形成於該第二表面處理層33上，以分別電性連接該第二線路層29之該些第二電性接觸墊291上。在其他實施例中，本發明亦可不必形成有該第二表面處理層33，從而直接將該些第二導電元件36形成於該些第二電性接觸墊291上。
該半導體封裝結構2可包括絕緣材37，係形成於該介電層27之第一表面27a與該半導體元件34之間，以包覆該第一線路層24上之第一表面處理層32及該些第一導電元件35，且該絕緣材37可為底膠或封裝膠體。
由上可知，本發明之半導體封裝結構及其製法中，主要係在第一線路層之複數第一電性接觸墊上形成複數具有立體之接觸面(如上表面和側表面)之突出構件，以透過複數第一導電元件將半導體元件接置於該些突出構件上並包覆該些接觸面。
藉此，該些突出構件不會於迴銲製程中形成軟塌狀態，故可避免該些第一導電元件之導電材料(如銲錫)往外溢出而影響電性連接之狀況，亦可免除相鄰之兩第一導電元件互相電性連接而形成短路之情形。同時，該些突出構 件具有較大的接觸面積，故可提升該第一導電元件與該第一線路層之第一電性接觸墊間之接合強度，從而提高後續產品之信賴性。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如申請專利範圍所列。
2‧‧‧半導體封裝結構
22‧‧‧突出構件
220‧‧‧下表面
221‧‧‧接觸面
24‧‧‧第一線路層
241‧‧‧第一電性接觸墊
26‧‧‧導電柱
26a‧‧‧第一端部
26b‧‧‧第二端部
27‧‧‧介電層
27a‧‧‧第一表面
27b‧‧‧第二表面
29‧‧‧第二線路層
291‧‧‧第二電性接觸墊
292‧‧‧側表面
30‧‧‧絕緣保護層
32‧‧‧第一表面處理層
33‧‧‧第二表面處理層
34‧‧‧半導體元件
35‧‧‧第一導電元件
36‧‧‧第二導電元件
37‧‧‧絕緣材

Claims (29)

  1. 一種半導體封裝結構，其包括：介電層，係具有相對之第一表面與第二表面；第一線路層，係嵌埋於該介電層內並令該第一線路層之一表面外露於該介電層之第一表面；複數垂直之導電柱，係嵌埋於該介電層內並令該垂直之導電柱一端外露於該介電層之第二表面，且該些導電柱係分別電性連接該第一線路層；第二線路層，係外凸形成於該介電層之第二表面上，並電性連接外露於該介電層之第二表面之該些導電柱；以及複數突出構件，係分別形成於外露該介電層之第一表面之第一線路層上；其中，該些垂直之導電柱係垂直連接嵌埋於該介電層內之該第一線路層與外凸形成於該介電層之第二表面上之該第二線路層。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中，該介電層係為封裝膠體或預浸體。
  3. 如申請專利範圍第1項所述之半導體封裝結構，其中，該第一線路層係具有複數第一電性接觸墊，供該些突出構件分別形成於該些第一電性接觸墊上。
  4. 如申請專利範圍第3項所述之半導體封裝結構，其中，該突出構件與該第一電性接觸墊係為相同材質所形成者或一體成形者。
  5. 如申請專利範圍第3項所述之半導體封裝結構，其中，該突出構件之寬度係小於或等於該第一電性接觸墊之寬度。
  6. 如申請專利範圍第1項所述之半導體封裝結構，其中，該突出構件係為另一導電柱或一導電跡線之銲墊。
  7. 如申請專利範圍第1項所述之半導體封裝結構，其中，該第二線路層係具有複數第二電性接觸墊，供該垂直之導電柱之相對第一端部與第二端部分別電性連接該第一線路層及該第二電性接觸墊。
  8. 如申請專利範圍第1項所述之半導體封裝結構，復包括絕緣保護層，係形成於該介電層之第二表面上以包覆該第二線路層，並外露部分該第二線路層。
  9. 如申請專利範圍第1項所述之半導體封裝結構，復包括第一表面處理層，係形成於該第一線路層及該些突出構件之接觸面上。
  10. 如申請專利範圍第1項所述之半導體封裝結構，復包括半導體元件，係透過複數第一導電元件接置於該些突出構件上，且該些第一導電元件係分別包覆該些突出構件之接觸面。
  11. 如申請專利範圍第10項所述之半導體封裝結構，復包括絕緣材，係形成於該介電層之第一表面與該半導體元件之間，以包覆該第一線路層及該些第一導電元件。
  12. 如申請專利範圍第11項所述之半導體封裝結構，其中，該絕緣材係為底膠或封裝膠體。
  13. 如申請專利範圍第10項所述之半導體封裝結構，其中，該第一導電元件係為凸塊。
  14. 如申請專利範圍第1項所述之半導體封裝結構，復包括第二表面處理層，係形成於該第二線路層上。
  15. 如申請專利範圍第14項所述之半導體封裝結構，復包括複數第二導電元件，係形成於該第二表面處理層上以分別電性連接該第二線路層。
  16. 一種半導體封裝結構之製法，其包括：提供一具有相對之第一表面與第二表面之介電層，該介電層內係嵌埋有一表面外露於該介電層之第一表面之第一線路層、及複數一端外露於該介電層之第二表面並電性連接該第一線路層之垂直之導電柱，且外露於該介電層之第一表面之第一線路層上係形成有複數突出構件；以及於該介電層之第二表面上形成外凸之第二線路層，以電性連接外露於該介電層之第二表面之該些導電柱；其中，該些垂直之導電柱係垂直連接嵌埋於該介電層內之該第一線路層與外凸形成於該介電層之第二表面上之該第二線路層。
  17. 如申請專利範圍第16項所述之半導體封裝結構之製法，復包括下列步驟以提供該介電層：準備一具有相對之第一表面與第二表面之承載板； 形成複數凹部於該承載板之第二表面；形成該些突出構件於該些凹部；形成該第一線路層於該承載板之第二表面；形成該些垂直之導電柱於該第一線路層上；以及形成該介電層。
  18. 如申請專利範圍第17項所述之半導體封裝結構之製法，其中，該些突出構件之下表面係齊平於該承載板之第二表面。
  19. 如申請專利範圍第17項所述之半導體封裝結構之製法，其中，該第一線路層之製程係包括：形成一第一阻層於該承載板之第二表面及該突出構件之下表面上；形成複數第一溝槽於該第一阻層；以及形成該第一線路層於該些第一溝槽內，且該些第一線路層具有複數第一電性接觸墊，以分別電性連接該些突出構件之下表面。
  20. 如申請專利範圍第19項所述之半導體封裝結構之製法，其中，該些垂直之導電柱之製程係包括：形成一具有複數開孔之第二阻層於該第一阻層與該第一線路層上，且該些開孔係分別外露出部分該第一線路層；以及形成該些垂直之導電柱於該些開孔內，且該些垂直之導電柱之第一端部係分別電性連接外露於該些開孔之第一線路層。
  21. 如申請專利範圍第20項所述之半導體封裝結構之製法，其中，該介電層之製程係包括：移除該第一阻層與該第二阻層，以外露出該第一線路層及該些垂直之導電柱；以及形成該介電層於該承載板上，以包覆該第一線路層及該些垂直之導電柱並外露出該些垂直之導電柱之第二端部。
  22. 如申請專利範圍第21項所述之半導體封裝結構之製法，其中，該第二線路層之製程係包括：形成一具有複數第二溝槽之第三阻層於該介電層之第二表面上，且該些第二溝槽係外露出該些垂直之導電柱之第二端部及部分該介電層之第二表面；以及形成該第二線路層於該些第二溝槽內，且該第二線路層之複數第二電性接觸墊係分別電性連接該些垂直之導電柱之第二端部。
  23. 如申請專利範圍第22項所述之半導體封裝結構之製法，復包括：移除該第三阻層，以外露出該介電層之第二表面及該第二線路層；以及形成絕緣保護層於該介電層之第二表面上，以包覆該第二線路層並外露出部分該第二線路層。
  24. 如申請專利範圍第23項所述之半導體封裝結構之製法，復包括：形成一具有至少一開口之框體於該承載板之第一 表面上；依據該框體之開口移除部分該承載板；以及進行切單作業。
  25. 如申請專利範圍第16項所述之半導體封裝結構之製法，復包括形成第一表面處理層於該第一線路層與該些突出構件之接觸面上。
  26. 如申請專利範圍第16項所述之半導體封裝結構之製法，復包括將半導體元件透過複數第一導電元件接置於該些突出構件上，且該些第一導電元件係分別包覆該些突出構件之接觸面。
  27. 如申請專利範圍第26項所述之半導體封裝結構之製法，復包括形成絕緣材於該介電層之第一表面與該半導體元件之間，以包覆該第一線路層及該些第一導電元件。
  28. 如申請專利範圍第16項所述之半導體封裝結構之製法，復包括形成第二表面處理層於該第二線路層上。
  29. 如申請專利範圍第28項所述之半導體封裝結構之製法，復包括形成複數第二導電元件於該第二表面處理層上以分別電性連接該第二線路層。
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