JP5221315B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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- JP5221315B2 JP5221315B2 JP2008321037A JP2008321037A JP5221315B2 JP 5221315 B2 JP5221315 B2 JP 5221315B2 JP 2008321037 A JP2008321037 A JP 2008321037A JP 2008321037 A JP2008321037 A JP 2008321037A JP 5221315 B2 JP5221315 B2 JP 5221315B2
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- layer
- pad
- resist layer
- support base
- wiring board
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- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path
Description
図1は本発明の第1の実施形態に係る配線基板(半導体パッケージ)の構成を断面図の形態で示したものである。
図8は本発明の第2の実施形態に係る配線基板(半導体パッケージ)の構成を断面図の形態で示したものである。
図10は本発明の第3の実施形態に係る配線基板(半導体パッケージ)の構成を断面図の形態で示したものである。
上述した第1の実施形態(図1)では、各パッドP1,P2を構成する金属層の組成として、Cu層11a上にSn層11bが積層された2層構造とした場合を例にとって説明したが、露出する側のSn層11bについては必ずしも形成されている必要はない。一般的な半導体パッケージに設けられているようなパッドと同様に、Cu層が露出している形態のものでもよい。
11a,11b,73,74,83,84,87,88,89…金属層、
14,17,20…配線層、
12,12a,12b,15,18…樹脂層(絶縁層)、
13a,13b,16,19…ビア、
21…ソルダレジスト層(絶縁層)、
30,30a…半導体装置、
31,31a,36,41…半導体素子(チップ/電子部品)、
32,32a,34,37,42…はんだ(バンプ)、
33,33a,43…アンダーフィル樹脂、
60,60a,60b,70,80…支持基材、
61,62,71,81,85…レジスト層、
CM…チップ搭載エリア、
DP,DP1,DP2,DP3…凹部、
P1,P2,P3,P4,P5,P6,P7,P8…パッド、
VH1,VH2,VH3,VH4…ビアホール。
Claims (8)
- 複数の配線層が絶縁層を介在させて積層され、各絶縁層に形成されたビアを介して層間接続された構造を有した配線基板であって、
前記配線基板の一方の面側の最外層の絶縁層の、電子部品の搭載エリアの周囲の領域に配置され、対応するビアに接続され、当該絶縁層の一部分を突出させて成形された当該部分の表面を覆ってバンプ状に形成された第1のパッドと、
前記電子部品の搭載エリア内に配置され、対応するビアに接続され、その表面が当該絶縁層から露出する第2のパッドとを備え、
前記第2のパッドは、前記最外層の絶縁層の一部分を突出させて成形された当該部分の表面を覆ってバンプ状に形成され、かつ、その表面の頂部が前記第1のパッドの表面の頂部の位置よりも低い位置となるように形成されており、
第1のパッドに接続されるビアは、ビアホールの内壁面を被覆し、該ビアホール内に絶縁層が充填され、第2のパッドに接続されるビアは、ビアホールを充填しており、
前記第1のパッド及び前記第2のパッドと、前記パッドとそれぞれ電気的に接続される前記ビアとは、前記配線基板の最外層の絶縁層に形成されており、
前記第1のパッドは他のパッケージに接続されるパッドであり、前記第2のパッドは半導体素子に接続されるパッドであることを特徴とする配線基板。 - 前記第2のパッドは、その表面が当該絶縁層の表面から基板内側に後退した位置に露出するよう設けられていることを特徴とする請求項1に記載の配線基板。
- 前記第2のパッドは、その表面が当該絶縁層の表面と同一面に露出するよう設けられていることを特徴とする請求項1に記載の配線基板。
- 前記第1、第2の各パッドは、複数の金属層が積層された構造を有していることを特徴とする請求項1に記載の配線基板。
- 支持基材上に、電子部品の搭載エリアに対応する部分が残存し、かつ、その周囲に対応する部分において形成すべき第1のパッドの形状に応じた開口部を有するようパターン形成された第1のレジスト層を形成する工程と、
前記第1のレジスト層の開口部から露出している前記支持基材の部分を所要量だけ除去し、凹部を有した支持基材を形成する工程と、
前記第1のレジスト層を除去後、前記支持基材の前記凹部が形成されている側の面に、前記電子部品の搭載エリアに対応する部分において形成すべき第2のパッドの形状に応じた第1の開口部と、前記凹部に対応する部分に第2の開口部とを有するようパターン形成された第2のレジスト層を形成する工程と、
前記第2のレジスト層の第1、第2の各開口部から露出している前記支持基材上及びその凹部の内壁面上に、複数の金属層を形成する工程と、
前記第2のレジスト層を除去後、前記支持基材の金属層が形成されている側の面に、各金属層の部分を露出させて絶縁層を形成する工程と、
前記絶縁層上に、前記各金属層にそれぞれ接続されるビアを含む配線層を形成する工程と、
以降、所要の層数となるまで絶縁層と配線層を交互に積層した後、前記支持基材を除去する工程とを含むことを特徴とする配線基板の製造方法。 - 前記第2のレジスト層を形成した後、更にエッチング工程を含むことを特徴とする請求項5に記載の配線基板の製造方法。
- 支持基材上に、電子部品の搭載エリアに対応する部分が残存し、かつ、その周囲に対応する部分において形成すべき第1のパッドの形状に応じた開口部を有するようパターン形成された第1のレジスト層を形成する工程と、
前記第1のレジスト層の開口部から露出している前記支持基材の部分を所要量だけ除去し、凹部を有した支持基材を形成する工程と、
前記第1のレジスト層を除去後、前記支持基材の前記凹部が形成されている側の面に、該凹部に対応する部分に開口部を有するようパターン形成された第2のレジスト層を形成する工程と、
前記第2のレジスト層の開口部から露出している前記支持基材の凹部の内壁面上に、複数の金属層を形成する工程と、
前記第2のレジスト層を除去後、前記支持基材の金属層が形成されている側の面に、前記電子部品の搭載エリアに対応する部分において形成すべき第2のパッドの形状に応じた開口部を有するようパターン形成された第3のレジスト層を形成する工程と、
前記第3のレジスト層の開口部から露出している前記支持基材上に、前記第2のパッドを構成する複数層の金属膜を積層する工程と、
前記第3のレジスト層を除去後、前記支持基材の各金属層が形成されている側の面に、各金属層の部分を露出させて絶縁層を形成する工程と、
前記絶縁層上に、前記各金属層にそれぞれ接続されるビアを含む配線層を形成する工程と、
以降、所要の層数となるまで絶縁層と配線層を交互に積層した後、前記支持基材を除去する工程とを含むことを特徴とする配線基板の製造方法。 - 前記複数の金属層の最外層を除去する工程を更に含むことを特徴とする請求項5から7のいずれか一項に記載の配線基板の製造方法。
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