JP5649490B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
- Publication number
- JP5649490B2 JP5649490B2 JP2011058265A JP2011058265A JP5649490B2 JP 5649490 B2 JP5649490 B2 JP 5649490B2 JP 2011058265 A JP2011058265 A JP 2011058265A JP 2011058265 A JP2011058265 A JP 2011058265A JP 5649490 B2 JP5649490 B2 JP 5649490B2
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- insulating layer
- interposer
- wiring
- wiring board
- surface side
- Prior art date
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Description
図1は第1の実施形態に係る配線基板(半導体パッケージ)の構成を断面図の形態で示したものである。
図13は第2の実施形態に係る配線基板(半導体パッケージ)の構成を断面図の形態で示したものである。
13,15,17,21…配線層、
12,12a,14,16,18,20…絶縁層、
13a,15a,17a,21a…ビア、
22…ソルダレジスト層(保護膜)、
30…インターポーザ、
32,35…インターポーザの電極パッド、
40…(高い弾性率及び低いCTEを有する)シート状部材、
50,60…半導体装置、
51…半導体素子、
52,64…はんだバンプ(導電性材料)、
55…チップキャパシタ(受動素子)、
58…はんだボール(外部接続端子)、
P1,P2…(第1、第2)外部接続用パッド。
Claims (8)
- 複数の配線層が絶縁層を介在させて積層され、半導体素子が搭載される第1面側と、該第1面側と反対側に位置する第2面側とを有する配線基板であって、
前記第1面側に位置する最外層の絶縁層に埋設され、搭載される半導体素子と電気的に接続されるインターポーザと、
前記第2面側に位置する最外層の絶縁層に埋設されたシート状部材とを有し、
前記インターポーザと前記シート状部材は、互いに対称となる位置に配設されており、
前記シート状部材は、その厚さ方向に貫通する開口部を有し、
前記開口部を通して基板内部の配線層と前記配線基板の第2面側に位置する最外層の絶縁層上に形成された第2外部接続用パッドとが電気的に接続されていることを特徴とする配線基板。 - 前記インターポーザは、前記配線基板の第1面側に位置する最外層の絶縁層の中央部分に埋設されており、
前記インターポーザが埋設されている部分の周囲の領域には、前記配線基板の第1面側に位置する最外層の絶縁層から露出する第1外部接続用パッドが設けられていることを特徴とする請求項1に記載の配線基板。 - 前記第1外部接続用パッドは、前記配線基板の第1面側に位置する最外層の絶縁層の表面が凹部状に基板内部に後退した位置に設けられていることを特徴とする請求項1又は2に記載の配線基板。
- 前記インターポーザの第1面側には、前記配線基板の第1面側に露出して、搭載される半導体素子と電気的に接続されるパッドが設けられ、
前記インターポーザの第1面側と反対側に位置する第2面側には、前記配線基板の第1面側に位置する最外層の絶縁層に形成された導体ビアと直接接続されるパッドが設けられていることを特徴とする請求項1から3のいずれか一項に記載の配線基板。 - 前記シート状部材の側壁部は、前記配線基板の第2面側に位置する最外層の絶縁層によって覆われていることを特徴とする請求項1から4のいずれか一項に記載の配線基板。
- 支持基材上にインターポーザを搭載する工程と、
前記支持基材上に、前記インターポーザを被覆するように絶縁層を形成する工程と、
前記絶縁層にビアホールを形成し、該絶縁層上に、該ビアホールを介して前記インターポーザと電気的に接続される配線層を形成する工程と、
絶縁層と配線層を交互に積層する工程と、
前記積層した絶縁層上に、開口部を有するシート状部材を積層する工程と、
前記開口部を有するシート状部材を被覆するように絶縁層を形成して、該シート状部材を埋設する工程と、
前記埋設した絶縁層上に、前記シート状部材の開口部の位置に対応させてビアホールを形成し、該ビアホールを介して下層の配線層と電気的に接続される最外層の配線層を形成する工程と、
前記支持基材を除去する工程と、を含むことを特徴とする配線基板の製造方法。 - 前記支持基材上にインターポーザを搭載する工程の前に、前記支持基材上の前記インターポーザが搭載される部分の周囲の領域に第1外部接続用パッドを形成する工程を含み、
前記支持基材上に前記絶縁層を形成する工程において、前記支持基材上に、前記インターポーザと共に前記第1外部接続用パッドを被覆するように当該絶縁層を形成し、
前記絶縁層上に前記配線層を形成する工程において、前記絶縁層に複数のビアホールを形成し、該絶縁層上に、該複数のビアホールを介してそれぞれ前記インターポーザと前記第1外部接続用パッドとに電気的に接続される当該配線層を形成する、ことを特徴とする請求項6に記載の配線基板の製造方法。 - 前記シート状部材を絶縁層で被覆して埋設する工程において、前記シート状部材の側壁部も被覆するように当該絶縁層を形成することを特徴とする請求項6又は7に記載の配線基板の製造方法。
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