TWI587412B - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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Publication number
TWI587412B
TWI587412B TW103116365A TW103116365A TWI587412B TW I587412 B TWI587412 B TW I587412B TW 103116365 A TW103116365 A TW 103116365A TW 103116365 A TW103116365 A TW 103116365A TW I587412 B TWI587412 B TW I587412B
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Taiwan
Prior art keywords
package structure
substrate
electronic component
cladding layer
layer
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TW103116365A
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English (en)
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TW201543586A (zh
Inventor
賴杰隆
陳賢文
張宏達
葉懋華
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103116365A priority Critical patent/TWI587412B/zh
Priority to CN201410219030.1A priority patent/CN105097750A/zh
Priority to US14/487,548 priority patent/US9502335B2/en
Publication of TW201543586A publication Critical patent/TW201543586A/zh
Application granted granted Critical
Publication of TWI587412B publication Critical patent/TWI587412B/zh

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    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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Description

封裝結構及其製法
本發明係有關一種封裝製程，特別是關於一種應用打線技術之封裝結構及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂堆加複數封裝結構以形成封裝外堆疊結構(Package on Package,POP)或封裝內堆疊結構(Package in package,PiP)，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。請參閱第3圖，其係為習知封裝外堆疊結構(Package on Package,POP)之剖面示意圖。
如第3圖所示，習知封裝外堆疊結構3係將第二封裝件3b疊設於第一封裝件3a上。
該第一封裝件3a係包含具有相對之第一及第二表面31a,31b之第一基板31、及設於該第一表面31a上且電性連 接該第一基板31之第一電子元件30。該第二封裝件3b係包含具有相對之第三及第四表面32a,32b之第二基板32、設於該第三表面32a上且電性連接該第二基板32之第二電子元件35、及包覆該第二電子元件35之封裝膠體36。再者，係於該第一基板31之第一表面31a上形成焊錫球310，以令該第二基板32之第四表面32b藉由該焊錫球310疊設且電性連接於該第一基板31上。又，該第一基板31之第二表面31b上具有植球墊312以供結合焊球34，且該第一及第二電子元件30,35係為主動元件及/或被動元件，並以覆晶方式電性連接基板，且藉由底膠33充填於第一及第二電子元件30,35與第一基板31與第二基板32間，以形成覆晶接合。
然而，習知封裝外堆疊結構3之體積過大，無法滿足微小化之需求，例如，為了避免橋接發生，各該焊錫球310之間需保有一定距離，故難以縮小第一基板31之尺寸。
另一方面，目前亦發展出將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊之技術，例如，於封裝基板與半導體晶片之間增設一具有導電矽穿孔(Through-silicon via,TSV)之矽中介板(Through Silicon interposer,TSI)。由於該矽中介板可採用半導體製程做出3/3μm以下之線寬/線距，故當該半導體晶片具高I/O數時，該矽中介板之長寬方向之面積足以連接高I/O數之半導體晶片，故不需增加該封裝基板之面積，以滿足微小化需求。
惟，於製作習知矽中介板時，該導電矽穿孔之製程係 需於該矽板上挖孔(即經由曝光顯影蝕刻等圖案化製程而形成該些穿孔)及金屬填孔，致使該導電矽穿孔之整體製程占整個該矽中介板之製作成本達約40~50%(以12吋晶圓為例，不含人工成本)，且製作時間耗時(因前述步驟流程冗長，特別是蝕刻該矽板以形成該些穿孔)，以致於最終產品之成本及價格難以降低。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明提供一種封裝結構，係包括：基材，係具有複數電性連接部；至少一電子元件，係設於該基材上；複數導線，係立設於各該電性連接部上，且各該導線具有相對之第一端及第二端，並以其第一端結合至各該電性連接部；包覆層，係形成於該基材上並包覆該些導線與該電子元件，該包覆層具有相對之第一表面及第二表面，使該包覆層之第一表面結合至該基材與該些電性連接部上，且至少部分該導線之第二端外露於該包覆層之第二表面；以及線路層，係設於該包覆層之第二表面上並電性連接各該導線之第二端。
本發明復提供一種封裝結構之製法，係包括：提供一具有複數電性連接部之基材，且該基材上設有至少一電子元件；立設複數具有相對之第一端及第二端之導線於該電性連接部上，且各該導線以其第一端結合至各該電性連接部；形成具有相對之第一表面及第二表面之包覆層於該基 材上，以令該包覆層包覆該些導線與該電子元件，且該包覆層之第一表面係結合至該基材與該些電性連接部上，而至少部分該導線之第二端係外露於該包覆層之第二表面；以及形成線路層於該包覆層之第二表面上，且該線路層係電性連接各該導線之第二端。
前述之製法中，該導線係以打線接合法形成者。
前述之封裝結構及其製法中，該基材復具有線路構造，該線路構造具有相對之第一側及第二側，且該電性連接部設於該第一側上。再者，該線路構造之第二側形成有複數導電元件，且各該導電元件電性連接該線路構造。又，該基材亦可具有載板，且該載板設於該線路構造之第二側上並電性連接該線路構造，例如，該載板係為半導體材、介電材、陶瓷材或金屬材，且該載板具有複數導電穿孔，以令該線路構造電性連接該些導電穿孔；或者，於形成該線路層之後，移除該載板。
前述之封裝結構及其製法中，該電子元件係電性連接該基材。
前述之封裝結構及其製法中，該電子元件外露於該包覆層之第二表面。
前述之封裝結構及其製法中，該導線之線徑係為0.01至0.15毫米。
前述之封裝結構及其製法中，至少兩相鄰的該導線之間的距離係為0.03至0.3毫米。
前述之封裝結構及其製法中，復包括堆疊至少一電子 裝置於該包覆層之第二表面上，使該電子裝置電性連接該線路層。例如，該電子裝置係以複數導電元件疊設於該線路層上。
另外，該包覆層復具有與該第一及第二表面相鄰之側面，且部分該導線之第二端外露於該側面。
由上可知，本發明封裝結構及其製法中，藉由藉由該導線作為導電路徑，其線徑可小於0.15mm，因而使各該導線之間的距離能小於0.3mm，故相較於習知技術受限於焊錫球之規格，本發明之封裝結構能使各該電性連接部之間距或各該線路層之間距縮小，以增加接點密度，因而能縮小該封裝結構之體積，且能增加該電子元件之電性I/O密度。
再者，該導線係以簡易的現有打線接合方式製作，故相較於習知矽中介板之製程，本發明之製法能大幅降低成本。
1,1’,2,2’,4,4’,4”‧‧‧封裝結構
10,10’,20‧‧‧基材
101,201‧‧‧載板
102‧‧‧離形層
11‧‧‧線路構造
11a‧‧‧第一側
11b‧‧‧第二側
12‧‧‧電性連接部
13‧‧‧銲墊
14,24‧‧‧導線
14a,24a‧‧‧第一端
14b,24b‧‧‧第二端
15,15’,15”‧‧‧電子元件
16‧‧‧包覆層
16a,31a‧‧‧第一表面
16b,31b‧‧‧第二表面
16c‧‧‧側面
160‧‧‧開口
17,17’‧‧‧線路層
18,190,28,290‧‧‧導電元件
19,19’‧‧‧電子裝置
190’‧‧‧銅凸塊
191,291‧‧‧晶片
200‧‧‧導電穿孔
202‧‧‧電性接觸墊
203‧‧‧絕緣材
240‧‧‧RDL
27‧‧‧外接墊
3‧‧‧封裝外堆疊結構
3a‧‧‧第一封裝件
3b‧‧‧第二封裝件
30‧‧‧第一電子元件
31‧‧‧第一基板
310‧‧‧焊錫球
312‧‧‧植球墊
32‧‧‧第二基板
32a‧‧‧第三表面
32b‧‧‧第四表面
33‧‧‧底膠
34‧‧‧焊球
35‧‧‧第二電子元件
36‧‧‧封裝膠體
5‧‧‧封裝模組
A‧‧‧非佈線區
w‧‧‧線徑
d‧‧‧間距
第1A至1G圖係為本發明封裝結構之製法之第一實施例之剖視示意圖；其中，第1D’圖係為第1D圖之另一態樣，第1F’及1F”圖係為第1F圖之其它態樣；第2A至2C圖係為本發明封裝結構之製法之第二實施例之剖視示意圖；第2D至2F圖係為本發明封裝結構之製法之第三實施例之剖視示意圖；其中，第2F’圖係為第2F圖之另一態樣；以及 第3圖係為習知封裝外堆疊結構之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、”第三”、”第四”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第1A至1G圖係為本發明封裝結構之製法之第一實施例之剖視示意圖。
如第1A圖所示，提供一具有複數電性連接部12及複數銲墊13之基材10，且該銲墊13上覆晶設有複數電子元件15，使該電子元件15電性連接該基材10。
於本實施例中，該電性連接部12係為墊狀，且該基材10包含一載板101、一離形層102及線路構造11。具體地，該載板101為半導體材、介電材、陶瓷材、玻璃或金屬材， 但不限於此，且以塗佈或貼合方式形成具黏性之離形層102於該載板101上，並製作一層或多層線路重佈層(redistribution layer,RDL)之線路構造11於該離形層102上。
再者，該線路構造11具有相對之第一側11a及第二側11b，且該些電性連接部12與銲墊13係設於該線路構造11之第一側11a上並電性連接該線路構造11，而該銲墊13上形成有凸塊底下金屬層(Under Bump Metallurgy,UBM)(圖略)以覆晶結合該電子元件15。
又，該載板101係利用該離形層102設於該線路構造11之第二側11b上。
另外，各該電子元件15係平面相鄰排設，且該電子元件15係為主動元件(如半導體晶片)或被動元件(如電容)；於其它實施例中，該電子元件15亦可利用晶片接合膜(die attach film,DAF)或導電膠之方式固設於該基材10上；或者，該電子元件15亦可利用打線方式電性連接該基材10。
如第1B圖所示，立設複數具有相對之第一端14a及第二端14b的導線14於各該電性連接部12上，且該導線14以其第一端14a結合至該電性連接部12。
於本實施例中，單一該電性連接部12僅結合一條導線14。再者，該導線14係以打線接合(Wire Bonding,WB)方式形成複數直立線狀，以作為內連線路結構。
又，各該導線14之線徑w可小於0.15毫米(mm)， 且兩相鄰的該導線14之間的距離d可小於0.3毫米。
如第1C圖所示，形成具有相對之第一表面16a及第二表面16b之包覆層16於該基材10上，以令該包覆層16包覆各該導線14與該電子元件15，且該包覆層16之第一表面16a係結合至該基材10與該電性連接部12上，而全部該導線14之第二端14b係外露於該包覆層16之第二表面16b。
於本實施例中，該包覆層16之製程可選擇液態封膠(liquid compound)、噴塗(injection)或模壓(compression molding)，且於模具內貼有離型膜，以確保移除模具後，該導線14之第二端14b能外露於該包覆層16之第二表面16b。再者，該電子元件15之上表面係埋設於該包覆層16中。
如第1D圖所示，形成一線路層17於該包覆層16之第二表面16b上，且該線路層17之線路部分或接觸墊部分係電性連接各該導線14之第二端14b，使該線路層17經由該導線14電性連接該電性連接部12。
於本實施例中，該線路層17係為一層線路重佈層(redistribution layer,RDL)；於其它實施例中，可依實際需求選擇製作多層線路重佈層(RDL)於該包覆層16之第二表面16b上。
或者，塗佈一有機保銲膜(organic solderability preservatives,OSP，圖略)於該線路層17上，以防止該線路層17之金屬表面發生氧化反應而影響訊號傳遞。
另外，該電子元件15上方之該包覆層16之第二表面16b處可設計為非佈線區A，即該非佈線區A上不會形成線路(如該線路層17)。因此，可依需求形成複數開口160於該非佈線區A上，如第1D’圖所示，以令各該電子元件15之上表面外露於該包覆層16之第二表面16b，俾供散熱或外接元件之用。
如第1E圖所示，移除該離形層102及該載板101，以形成新的基材10’。
如第1F圖所示，進行切單製程，且形成複數如銲球之導電元件18於該線路構造11之第二側11b，且該導電元件18電性連接該線路構造11，以藉由該些導電元件18接置如電路板之電子裝置(圖略)。
本發明之製法中，藉由該導線14作為導電路徑，其線寬小於0.15mm，因而使各該導線14之間的距離d能小於0.3mm，故相較於習知技術受限於焊錫球之規格，本發明之封裝結構1能符合微小化之需求。
再者，利用該導線14取代習知焊錫球，可使接點(如各該電性連接部12或各該線路層17)之間距密度增加，故不僅能縮小該封裝結構1之體積，且能增加電性I/O之密度。
又，該導線14係以簡易的現有打線接合方式製作，故相較於習知矽中介板，本發明之製法能大幅降低成本。
另外，如第1F’圖所示，該電子元件15’之上表面可齊平該包覆層16之第二表面16b，使該電子元件15’之上表 面外露於該包覆層16之第二表面16b；或者，如第1F”圖所示，各該電子元件15”可相互堆疊於該線路構造11之第一側11a上，且位於上方之電子元件15”之上表面亦可選擇性外露於該包覆層16之第二表面16b。
如第1G圖所示，接續第1F圖之製程，堆疊一電子裝置19於該包覆層16之第二表面16b上，使該電子裝置19電性連接該線路層17，以成為堆疊式封裝結構1’。
於本實施例中，該電子裝置19係為封裝件、晶片或基板等，並無特別限制。
再者，該電子裝置19係以如銲錫凸塊、銅凸塊之導電元件190電性連接該線路層17。於其它實施例中，該導電元件亦可設於該電子元件15之上方。
又，由於能縮小該封裝結構1之體積，故該堆疊式封裝結構1’能隨之符合微小化之需求。
另外，該電子裝置19係具有打線式晶片191；於其它實施例中，該電子裝置亦可具有覆晶式晶片，但晶片之設置方式不限於上述。
第2A至2C圖係為本發明之封裝結構之製法之第二實施例之剖視示意圖。本實施例與第一實施例之差異在於載板之設計，其它相同之元件爰用相同圖號，且相同元件之製程亦不另覆述。
如第2A圖所示，提供一基材20，該基材包含一載板201及該線路構造11。
於本實施例中，該載板201係為半導體材、介電材、 陶瓷材或金屬材，且該載板201具有複數導電穿孔200。例如，該載板201係為半導體材，如矽，以成為具有導電矽穿孔(Through-silicon via,TSV)之矽中介板(Through Silicon interposer,TSI)，且該線路構造11電性連接該些導電穿孔200，而該導電穿孔200之側壁周圍可選擇性形成絕緣材203。
再者，該載板201之下側具有複數電性連接該導電穿孔200之電性接觸墊202。
另外，有關該載板201之種類繁多，且可依需求設計，並不限於此。
如第2B圖所示，進行如第1B至1D圖所述之製程，再形成複數導電元件18於該載板201之電性接觸墊202上，以形成封裝結構2，使該導電元件18電性連接該些導電穿孔200。
如第2C圖所示，進行如第1G圖所述之製程，以形成堆疊式封裝結構2’。
於本實施例中，該電子裝置19’係具有覆晶式晶片291，且該導電元件290復設於該電子元件15之上方，以強化支撐該電子裝置19’。具體地，該電子元件15上方之該包覆層16之第二表面16b處可設計至少一外接墊27，以結合該導電元件290，且該外接墊27可電性連接或不電性連接該線路層17。
第2D至2F圖係為本發明之封裝結構之製法之第三實施例之剖視示意圖。本實施例與上述實施例之差異在於導 線之設計，其它相同之元件爰用相同圖號，且相同元件之製程亦不另覆述。
如第2D圖所示，以改良第二實施例之製程為例，立設複數具有相對之第一端14a,24a及第二端14b,24b的導線14,24於各該電性連接部12上，且各該導線14,24以其第一端14a,24a結合至該電性連接部12。
於本實施例中，部分該導線14係為直立線狀，而另一部分該導線24係為弧形線狀。
如第2E圖所示，進行如第1C至1F圖所述之製程，以形成封裝結構4，且該包覆層16復具有與該第一及第二表面16a,16b相鄰之側面16c，使弧形線狀之導線24之第二端24b外露於該側面16c，以作為電性接點，俾供後續製程電性連接電子器材。
於本實施例中，可形成至少一層RDL 240於該包覆層16之側面16c與該導線24之第二端24b上；亦可形成UBM(圖略)於該導線24之第二端24b上；或者形成異方性導電膠(Anisotropic Conductive Film,ACF，圖略)於該導線24之第二端24b上，以作為電性連接墊。
再者，該電子元件15’之上表面可齊平該包覆層16之第二表面16b，使該電子元件15’之上表面外露於該包覆層16之第二表面16b。
又，該線路層17’亦可選擇性地形成於該電子元件15’之上表面，且該線路層17’可選擇性電性連接該電子元件15’。
如第2F圖所示，進行如第1G圖所述之製程，以形成堆疊式封裝結構4’。因此，藉由該導線24之第二端24b之設計，該測測裝置可將線路牽引至該封裝結構4’之側面，以進行該電子元件15之測試，故能提升測試之便利性。
於本實施例中，該導電元件290復接觸地設於該電子元件15’上之線路層17’，以供該電子元件15’散熱或電性連接至該電子裝置19。當然地，該導電元件290亦可直接地接觸該電子元件15’之上表面上。
於其它實施例中，如第2F’圖所示，於該包覆層16之側面16c製作RDL(圖略)、UBM(圖略)、ACF(圖略)或OSP(圖略)後，可形成用以電性連接該導線24之第二端24b的複數如銲錫材之導電元件28，以利用該些導電元件28並排連接複數封裝結構4”，而形成具有水平與垂直電性連接路徑的封裝模組5。之後，再利用表面貼裝技術(Surface Mount Technology,SMT)將該封裝模組5設於電路板(圖略)上。
於本實施例中，銲錫材之導電元件190內部係包覆有銅凸塊190’，以減少銲錫材之使用量，故可避免各該導電元件190之間發生橋接現象，而提升產品之良率，且能滿足細間距(fine pitch)之需求。
本發明提供一種封裝結構1,1’,2,2’,4,4’,4”，係包括：一基材10’,20、設於該基材上10’,20之至少一電子元件15,15’,15”、複數導線14,24、一包覆層16、以及一線路層17。
所述之基材10’,20係具有複數電性連接部12與一線路構造11，該線路構造11具有相對之第一側11a及第二側11b，且該電性連接部12係設於該第一側11a上。
所述之電子元件15,15’,15”係電性連接該基材10’,20。
所述之導線14,24係立設於各該電性連接部12上，且該導線14,24具有相對之第一端14a,24a及第二端14b,24b，並以其第一端14a,24a結合至該電性連接部12。具體地，該導線14,24之線徑w係為0.01至0.15毫米，且兩相鄰的導線14,24之間的距離d係為0.03至0.3毫米。
所述之包覆層16係設於該基材10’,20上並包覆該些導線14,24與該電子元件15,15’,15”，該包覆層16具有相對之第一表面16a及第二表面16b，使該包覆層16之第一表面16a結合至該基材10’,20與該電性連接部12上，且至少部分該導線14之第二端14b外露於該包覆層16之第二表面16b。
所述之線路層17係設於該包覆層16之第二表面16b上並電性連接該導線14之第二端14b。
於一實施例中，該線路構造11之第二側11b形成有複數導電元件18，且各該導電元件18電性連接該線路構造11。
於一實施例中，該基材20更具有一載板201，且該載板201設於該線路構造11之第二側11b上並電性連接該線路構造11。例如，該載板201係為半導體材、介電材、陶瓷材或金屬材，且該載板201具有複數導電穿孔200，以 令該線路構造11電性連接該些導電穿孔200。
於一實施例中，該電子元件15’係外露於該包覆層16之第二表面16b。
於一實施例中，該封裝結構1’,2’復包括至少一電子裝置19,19’，係堆疊於該包覆層16之第二表面16b上並電性連接該線路層17，其中，該電子裝置19,19’係以複數導電元件190疊設於該線路層17上。
於一實施例中，該包覆層16復具有與該第一及第二表面16a,16b相鄰之側面16c，且部分該導線24之第二端24b外露於該側面16c。
綜上所述，本發明封裝結構及其製法，主要藉由該導線作為導電路徑，因其線寬小而使各該導線之間的距離能極小化，故不僅能符合微小化之需求，且能大幅降低成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1‧‧‧封裝結構
10’‧‧‧基材
11‧‧‧線路構造
12‧‧‧電性連接部
14‧‧‧導線
14a‧‧‧第一端
14b‧‧‧第二端
15‧‧‧電子元件
16‧‧‧包覆層
16a‧‧‧第一表面
16b‧‧‧第二表面
17‧‧‧線路層

Claims (22)

  1. 一種封裝結構，係包括：基材，係具有複數電性連接部；至少一電子元件，係具有相對之主動面及非主動面，且以該主動面設於該基材上；複數導線，係立設於各該電性連接部上，且各該導線具有相對之第一端及第二端，並以其第一端結合至各該電性連接部；包覆層，係形成於該基材上並包覆該些導線與該電子元件，該包覆層具有相對之第一表面及第二表面，使該包覆層之第一表面結合至該基材與該些電性連接部上，且至少部分該導線之第二端外露於該包覆層之第二表面，該電子元件之非主動面外露於該包覆層之第二表面；線路層，係設於該包覆層之第二表面上並電性連接各該導線之第二端，且該電子元件之非主動面上設有該線路層；以及至少一電子裝置，係堆疊於該包覆層之第二表面及該電子元件上，並透過複數導電元件電性連接至該線路層及該電子元件。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該基材復具有線路構造，該線路構造具有相對之第一側及第二側，且該電性連接部係設於該第一側上。
  3. 如申請專利範圍第2項所述之封裝結構，其中，該線 路構造之第二側形成有複數導電元件，且各該導電元件電性連接該線路構造。
  4. 如申請專利範圍第2項所述之封裝結構，其中，該基材更具有載板，且該載板設於該線路構造之第二側上並電性連接該線路構造。
  5. 如申請專利範圍第4項所述之封裝結構，其中，該載板具有複數導電穿孔，以令該線路構造電性連接該些導電穿孔。
  6. 如申請專利範圍第4項所述之封裝結構，其中，該載板係為半導體材、介電材、陶瓷材或金屬材。
  7. 如申請專利範圍第1項所述之封裝結構，其中，該電子元件係電性連接該基材。
  8. 如申請專利範圍第1項所述之封裝結構，其中，該導線之線徑係為0.01至0.15毫米。
  9. 如申請專利範圍第1項所述之封裝結構，其中，至少兩相鄰的該導線之間的距離係為0.03至0.3毫米。
  10. 如申請專利範圍第1項所述之封裝結構，其中，該包覆層復具有與該第一及第二表面相鄰之側面，且部分該導線之第二端外露於該側面。
  11. 一種封裝結構之製法，係包括：提供一具有複數電性連接部之基材，且該基材上設有至少一電子元件，其中，該電子元件具有相對之主動面及非主動面，且以該主動面設於該基材上；立設複數具有相對之第一端及第二端之導線於該 電性連接部上，且各該導線以其第一端結合至各該電性連接部；形成具有相對之第一表面及第二表面之包覆層於該基材上，以令該包覆層包覆該些導線與該電子元件，且該包覆層之第一表面係結合至該基材與該些電性連接部上，而至少部分該導線之第二端係外露於該包覆層之第二表面，該電子元件之非主動面外露於該包覆層之第二表面；以及形成線路層於該包覆層之第二表面上，該線路層係電性連接各該導線之第二端，且該電子元件之非主動面上設有該線路層；以及堆疊至少一電子裝置於該包覆層之第二表面及該電子元件上，使該電子裝置以複數導電元件疊設於該線路層及該電子元件上，且該電子裝置電性連接該線路層及該電子元件。
  12. 如申請專利範圍第11項所述之封裝結構之製法，其中，該基材復具有線路構造，該線路構造具有相對之第一側及第二側，且該電性連接部設於該第一側上。
  13. 如申請專利範圍第12項所述之封裝結構之製法，其中，該線路構造之第二側形成有複數導電元件，且各該導電元件電性連接該線路構造。
  14. 如申請專利範圍第12項所述之封裝結構之製法，其中，該基材更具有載板，且該載板設於該線路構造之第二側上並電性連接該線路構造。
  15. 如申請專利範圍第14項所述之封裝結構之製法，復包括於形成該線路層之後，移除該載板。
  16. 如申請專利範圍第14項所述之封裝結構之製法，其中，該載板具有複數導電穿孔，以令該線路構造電性連接該些導電穿孔。
  17. 如申請專利範圍第14項所述之封裝結構之製法，其中，該載板係為半導體材、介電材、陶瓷材或金屬材。
  18. 如申請專利範圍第11項所述之封裝結構之製法，其中，該電子元件係電性連接該基材。
  19. 如申請專利範圍第11項所述之封裝結構之製法，其中，該導線係以打線接合法形成者。
  20. 如申請專利範圍第11項所述之封裝結構之製法，其中，該導線之線徑係為0.01至0.15毫米。
  21. 如申請專利範圍第11項所述之封裝結構之製法，其中，至少兩相鄰的該導線之間的距離係為0.03至0.3毫米。
  22. 如申請專利範圍第11項所述之封裝結構之製法，其中，該包覆層復具有與該第一及第二表面相鄰之側面，且部分該導線之第二端外露於該側面。
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