TW201517240A - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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TW201517240A
TW201517240A TW102137271A TW102137271A TW201517240A TW 201517240 A TW201517240 A TW 201517240A TW 102137271 A TW102137271 A TW 102137271A TW 102137271 A TW102137271 A TW 102137271A TW 201517240 A TW201517240 A TW 201517240A
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substrate
package structure
stack
structure according
build
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TW102137271A
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陳嘉成
孫銘成
沈子傑
洪良易
蕭惟中
白裕呈
邱士超
江東昇
張翊峰
王隆源
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矽品精密工業股份有限公司
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Priority to TW102137271A priority Critical patent/TW201517240A/zh
Priority to CN201310526773.9A priority patent/CN104576593A/zh
Priority to US14/136,238 priority patent/US20150102484A1/en
Publication of TW201517240A publication Critical patent/TW201517240A/zh

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Abstract

一種封裝結構，係包括第一基板、設於該第一基板上且具有開口之增層部、設於該開口中且電性連接該第一基板之電子元件、設於該增層部上之堆疊件、以及設於該增層部與該堆疊件之間的封裝膠體。藉由該增層部之設計，以增加隔離效果及避免橋接現象。

Description

封裝結構及其製法
本發明係有關一種封裝結構，尤指一種得提升堆疊良率之封裝結構。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂堆加複數封裝件以形成封裝堆疊結構(Package on Package，POP)，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。
一般封裝堆疊結構(PoP)係僅以銲錫球(solder ball)堆疊與電性連接上、下封裝件，但隨著產品尺寸規格與線距越來越小，該些銲錫球之間容易發生橋接(bridge)現象，將影響產品之良率。
於是，遂發展出一種封裝堆疊結構，係以銅柱(Cu pillar)作支撐，以增加隔離(stand off)效果，可避免發生橋接現象。第1A及1B圖係為習知封裝堆疊結構1之製法之剖面示意圖。
如第1A圖所示，先提供一具有相對之第一及第二表面11a,11b 之第一基板11，且於該第一基板11之第一表面11a上形成複數銅柱13。
如第1B圖所示，設置一電子元件15於該第一表面11a上且以覆晶方式電性連接該第一基板11，再疊設一第二基板12於該銅柱13上，之後形成封裝膠體16於該第一基板11之第一表面11a與該第二基板12之間。具體地，該第二基板12藉由複數導電元件17結合該銅柱13，且該導電元件17係由金屬柱170與銲錫材料171構成。
惟，習知封裝堆疊結構1中，該銅柱13係以電鍍形成，致使其尺寸變異不易控制，故容易發生各銅柱13之高度不一致之情況，因而產生接點偏移之問題，致使該些導電元件17與該些銅柱13接觸不良，而造成電性不佳，因而影響產品良率。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種封裝結構，係包括：第一基板；增層部，係設於該第一基板上並電性連接該第一基板，且該增層部具有開口；至少一電子元件，係設於該開口中，且電性連接該第一基板；堆疊件，係設於該增層部上，以令該堆疊件疊設於該第一基板上；以及封裝膠體，係設於該增層部與該堆疊件之間。
本發明復提供一種封裝結構之製法，係包括：提供一第一基板，該第一基板上具有增層部，且該增層部具有開口；設置至少一電子元件於該開口中，且該電子元件電性連接該第一基板；以 及設置堆疊件於該增層部上，以令該堆疊件疊設於該第一基板上。
前述之製法中，該第一基板之製程係包括：提供該第一基板；以及形成該增層部於該第一基板上，且形成該開口於該增層部上，該增層部並電性連接該第一基板。
前述之封裝結構及其製法中，該增層部之製程係包括：形成至少一介電層於該第一基板上，且形成該開口與複數盲孔於該介電層上；形成複數導電體於該些盲孔中，使該些導電體電性連接該第一基板；及設置該電子元件於該開口中。
依前述技術中，形成該介電層之材質係為預浸材，且該介電層係先壓合於該第一基板上，再形成該開口於該介電層上；或者，該介電層係先形成該開口，再壓合該介電層於該第一基板上。
依前述技術中，該開口及該些盲孔係以雷射鑽孔方式形成者，而該導電體係為金屬材且為柱狀或凹槽狀。
依前述技術中，該堆疊件與該導電體係藉由導電元件相結合。
依前述技術中，復包括形成線路層於該介電層上，且該線路層電性連接該些導電體。
前述技術中，復包括形成絕緣保護層於該介電層上，且外露該些導電體，使該封裝膠體設於該絕緣保護層與該堆疊件之間。
前述之封裝結構及其製法中，該第一基板係為線路板。
前述之封裝結構及其製法中，該開口係外露該第一基板之表面，使該電子元件設於該第一基板之表面上。
前述之封裝結構及其製法中，該電子元件係為主動元件或被動元件。
前述之封裝結構及其製法中，該堆疊件與該增層部係藉由複 數導電元件相結合。
前述之封裝結構及其製法中，該堆疊件係為第二基板或封裝件，例如，該第二基板係為線路板。
另外，前述之製法中，復包括形成封裝膠體於該增層部與該堆疊件之間，且前述之封裝結構及其製法中，該堆疊件之寬度小於該第一基板之寬度，使該封裝膠體包覆該堆疊件。又該封裝膠體復設於該第一基板與該堆疊件之間。
由上可知，本發明封裝結構及其製法，主要藉由在該第一基板上形成該增層部，以增加隔離效果及避免橋接現象。
再者，藉由該些盲孔控制各該導電體之尺寸，使各該導電體之高度一致，以避免接點偏移之問題，故相較於習知技術，該些導電元件與該些導電體不會發生接觸不良或短路之問題，因而能有效提高產品良率。
1‧‧‧封裝堆疊結構
11、21‧‧‧第一基板
11a、21a‧‧‧第一表面
11b、21b‧‧‧第二表面
12‧‧‧第二基板
13‧‧‧銅柱
15、25、35‧‧‧電子元件
16、26、26’、36‧‧‧封裝膠體
17、27‧‧‧導電元件
170、270‧‧‧金屬柱
171、271‧‧‧銲錫材料
2、3、4‧‧‧封裝結構
20‧‧‧介電層
200‧‧‧開口
201‧‧‧盲孔
21’‧‧‧芯層
210‧‧‧銲墊
211‧‧‧電性接觸墊
212‧‧‧植球墊
213、223‧‧‧層間線路
22、32‧‧‧堆疊件
22’‧‧‧基板
22a、32a‧‧‧頂面
22b‧‧‧底面
23‧‧‧線路層
230、230’‧‧‧導電體
24、24’‧‧‧絕緣保護層
240、240’‧‧‧開孔
250‧‧‧銲錫凸塊
251‧‧‧底膠
28、48‧‧‧增層部
32c‧‧‧側面
d、r‧‧‧寬度
第1A至1B圖係為習知封裝堆疊結構之製法的剖視示意圖；第2A至2F圖係為本發明封裝結構之製法的剖視示意圖；其中，第2C’圖係為第2C圖之另一實施例；以及第3及4圖係為本發明封裝結構之其它實施例的剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解 與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“頂”、“底”、“側面”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之封裝結構2之製法之剖視示意圖。
如第2A圖所示，提供一具有相對之第一表面21a及第二表面21b之第一基板21。
於本實施例中，該第一基板21係為線路板，其具有一芯層21’及形成於該芯層21’上、下側之複數層間線路213，且該第一表面21a上具有複數銲墊210與複數電性接觸墊211，而該第一基板21之第二表面21b上具有複數植球墊212。
再者，該芯層21’之層間線路213之數量可於上、下側均相同或不相同。
另外，可形成一例如防銲層之絕緣保護層24’於該第一基板21之第二表面21b上，且該絕緣保護層24’之開孔240’外露該些植球墊212。
如第2B圖所示，形成一介電層20於該第一基板21之第一表面21a上，且形成一開口200及複數盲孔201於該介電層20上。
於本實施例中，係先以壓合方式形成該介電層20於該第一基板21之第一表面21a上，再以雷射鑽孔方式形成該開口200及該 些盲孔201。於其它實施例中，亦可先形成該開口200及該些盲孔201於該介電層20上，再壓合該介電層20至該第一基板21之第一表面21a上。
再者，該些盲孔201係分別外露該些電性接觸墊211，且該開口200外露該些銲墊210及其周圍之該第一基板21之第一表面21a。
又，形成該介電層20之材質可為預浸材(Prepreg,PP)。
如第2C圖所示，形成一線路層23於該介電層20上，且形成複數導電體230於該些盲孔201中，以令該介電層20、線路層23與導電體230作為增層部28，且使該些導電體230電性連接該線路層23與該第一基板21之層間線路213與電性接觸墊211。
於本實施例中，於該介電層20與該線路層23上形成有例如防銲層之一絕緣保護層24，且該絕緣保護層24藉由複數開孔240分別外露該些導電體230。
再者，該導電體230係為如銅之金屬材，且該導電體230係為柱狀。
又，於一實施例中，該導電體230’係為凹槽狀，如第2C’圖所示。
如第2D圖所示，藉由複數銲錫凸塊250設置一電子元件25於該開口200中之該些銲墊210上，並藉由底膠251包覆該些銲錫凸塊250，使該電子元件25設於該第一基板21之第一表面21a上，以形成一封裝件，且該電子元件25以覆晶方式電性連接該第一基板21之層間線路213與銲墊210。
於本實施例中，該電子元件25係為主動元件及/或被動元件， 該主動元件係例如晶片，而該被動元件係例如電阻、電容或電感。
於其它實施例中，該電子元件25亦可以打線方式電性連接該第一基板21。
如第2E圖所示，設置一堆疊件22於該導電體230上，以令該堆疊件22疊設於該增層部28上，且覆蓋該電子元件25。
於本實施例中，該堆疊件22係為第二基板，如線路板，其具有複數層間線路223，且該堆疊件22係藉由複數導電元件27電性結合至該導電體230。例如，該堆疊件22之底面22b以如銲錫材料之導電元件27電性連接該導電體230，使該堆疊件22疊設於該增層部28上。或者，該導電體230與該堆疊件22之間亦可形成由金屬柱270(如銅柱)與銲錫材料271構成之導電元件27，以利於堆疊製程。
再者，如第3圖所示，該堆疊件32亦可為封裝件，係包含一基板22’、設於該基板22’之頂面22a的其它電子元件35及包覆該電子元件35之封裝膠體36，且該電子元件35係以覆晶方式或打線方式電性連接該基板22’。
如第2F圖所示，形成封裝膠體26於該第一基板21之第一表面21a與該堆疊件22之間。
於本實施例中，該封裝膠體26係設於該介電層20(或該絕緣保護層24)與該堆疊件22之間，而未設於該開口200中，故該封裝膠體26係包覆該些導電元件27，而未包覆該電子元件25。於其它實施例中，該封裝膠體26亦可填滿該第一基板21之第一表面21a與該堆疊件22之間，以包覆該些導電元件27與該電子元件25。
於另一實施例中，如第3圖所示，該堆疊件32之寬度d係小於該第一基板21之寬度r，使該封裝膠體26’復包覆該堆疊件32之側面32c與頂面32a。
於另一實施例中，本發明之封裝結構4中，如第4圖所示，該增層部48亦可包含複數介電層20與複數線路層23。
本發明之製法係藉由在第一基板21上形成增層部28(即該介電層20、線路層23與導電體230)，使該導電體230嵌入該介電層20中，再於該增層部28上接置該堆疊件22,32(即另一基板或封裝件)，藉以增加隔離(stand off)各該導電體230之效果、及避免各該導電體230之間發生橋接現象。
再者，藉由該些盲孔201控制各該導電體230之尺寸，使各該導電體230之高度一致，以令該些導電元件27之接置處高度一致，因而能避免接點偏移之問題，故該些導電元件27與該些導電體230不會發生接觸不良或短路(short)之問題，因而能有效提高產品良率。
本發明復提供一種封裝結構2,3,4，係包括：一第一基板21、設於該第一基板21上並電性連接該第一基板21之增層部28,48、電性連接該第一基板21之一電子元件25、疊設於該增層部28,48上之一堆疊件22,32、以及設於該增層部28,48(或該絕緣保護層24)與該堆疊件22,32之間的封裝膠體26,26’。
所述之第一基板21係為線路板，其具有相對之第一表面21a與第二表面21b。
所述之增層部28,48係具有一開口200，且該開口200係外露該第一基板21之第一表面21a。
於本實施例中，該增層部28,48係包含：設於該第一基板21上之至少一介電層20、設於該介電層20上之線路層23、及位於該介電層20中且外露於該介電層20之導電體230。
具體地，該開口200穿設該介電層20，且該介電層20具有複數盲孔201，並且形成該介電層20之材質係為預浸材(Prepreg,PP)。該導電體230,230’係設於該盲孔201中並電性連接該線路層23與該第一基板21，又該導電體230,230’係為金屬材，且該導電體230,230’係為柱狀或凹槽狀。再者，所述之封裝結構2,3,4復包括一絕緣保護層24，係設於該增層部28,48上並外露該些導電體230,230’。
所述之電子元件25係為主動元件或被動元件，其設於該開口200中之第一基板21之第一表面21a上。
所述之堆疊件22,32係設於該增層部28,48上。具體地，該堆疊件22,32與該導電體230,230’係藉由複數導電元件27相結合，以令該堆疊件22,32疊設於該第一基板21上。
於一實施例中，所述之封裝膠體26’復設於該第一基板21與該堆疊件32之間。
於一實施例中，該堆疊件22係為如線路板之第二基板；而於另一實施例中，該堆疊件32係為封裝件。
於一實施例中，該堆疊件32之寬度d係小於該第一基板21之寬度r，使該封裝膠體26’復包覆該堆疊件32。
綜上所述，本發明封裝結構及其製法，係藉由在該第一基板上形成介電層，使該導電體嵌入該介電層中，再於該增層部上接置該堆疊件，藉以增加隔離效果及避免橋接現象。
再者，藉由該些盲孔控制各該導電體之尺寸，使各該導電體之高度一致，以避免接點偏移之問題，故該些導電元件與該些導電體不會發生接觸不良或短路之問題，因而能有效提高產品良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保 護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝結構
20‧‧‧介電層
200‧‧‧開口
201‧‧‧盲孔
21‧‧‧第一基板
22‧‧‧堆疊件
23‧‧‧線路層
230‧‧‧導電體
24‧‧‧絕緣保護層
25‧‧‧電子元件
26‧‧‧封裝膠體
27‧‧‧導電元件
28‧‧‧增層部

Claims (41)

  1. 一種封裝結構，係包括：第一基板；增層部，係設於該第一基板上並電性連接該第一基板，且該增層部具有開口；至少一電子元件，係設於該開口中，且電性連接該第一基板；堆疊件，係設於該增層部上，以令該堆疊件疊設於該第一基板上；以及封裝膠體，係設於該增層部與該堆疊件之間。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該第一基板係為線路板。
  3. 如申請專利範圍第1項所述之封裝結構，其中，該開口係外露該第一基板之表面，使該電子元件設於該第一基板之表面上。
  4. 如申請專利範圍第1項所述之封裝結構，其中，該增層部係包含：至少一介電層，係設於該第一基板上，且該開口穿設該介電層；及至少一導電體，係位於該介電層中且外露於該介電層，並電性連接該第一基板。
  5. 如申請專利範圍第4項所述之封裝結構，其中，形成該介電層之材質係為預浸材。
  6. 如申請專利範圍第4項所述之封裝結構，其中，形成該導電體之材質係為金屬材。
  7. 如申請專利範圍第4項所述之封裝結構，其中，該導電體係為柱狀或凹槽狀。
  8. 如申請專利範圍第4項所述之封裝結構，其中，該堆疊件與該導電體係藉由複數導電元件相結合。
  9. 如申請專利範圍第4項所述之封裝結構，復包括線路層，係設於該介電層上，且電性連接該導電體。
  10. 如申請專利範圍第4項所述之封裝結構，復包括絕緣保護層，係設於該增層部上，且外露該導電體。
  11. 如申請專利範圍第10項所述之封裝結構，其中，該封裝膠體係設於該絕緣保護層與該堆疊件之間。
  12. 如申請專利範圍第1項所述之封裝結構，其中，該電子元件係為主動元件或被動元件。
  13. 如申請專利範圍第1項所述之封裝結構，其中，該堆疊件與該增層部係藉由複數導電元件相結合。
  14. 如申請專利範圍第1項所述之封裝結構，其中，該堆疊件係為第二基板或封裝件。
  15. 如申請專利範圍第14項所述之封裝結構，其中，該第二基板係為線路板。
  16. 如申請專利範圍第1項所述之封裝結構，其中，該堆疊件之寬度係小於該第一基板之寬度。
  17. 如申請專利範圍第16項所述之封裝結構，其中，該封裝膠體係包覆該堆疊件。
  18. 如申請專利範圍第1項所述之封裝結構，其中，該封裝膠體復設於該第一基板與該堆疊件之間。
  19. 一種封裝結構之製法，係包括：提供一第一基板，該第一基板上具有增層部，且該增層部具有開口；設置至少一電子元件於該開口中，且該電子元件電性連接該第一基板；以及設置堆疊件於該增層部上，以令該堆疊件疊設於該第一基板上。
  20. 如申請專利範圍第19項所述之封裝結構之製法，其中，該第一基板之製程係包括：提供該第一基板；以及形成該增層部於該第一基板上，且形成該開口於該增層部上，該增層部並電性連接該第一基板。
  21. 如申請專利範圍第19項所述之封裝結構之製法，其中，該第一基板係為線路板。
  22. 如申請專利範圍第19項所述之封裝結構之製法，其中，該開口係外露該第一基板之表面，使該電子元件設於該第一基板之表面上。
  23. 如申請專利範圍第19項所述之封裝結構之製法，其中，該增層部之製程係包括：形成至少一介電層於該第一基板上，且形成該開口與複數盲孔於該介電層上；形成複數導電體於該些盲孔中，使該些導電體電性連接該第一基板；及設置該電子元件於該開口中。
  24. 如申請專利範圍第23項所述之封裝結構之製法，其中，該介電層係先壓合於該第一基板上，再形成該開口於該介電層上。
  25. 如申請專利範圍第23項所述之封裝結構之製法，其中，該介電層係先形成該開口，再壓合該介電層於該第一基板上。
  26. 如申請專利範圍第23項所述之封裝結構之製法，其中，形成該介電層之材質係為預浸材。
  27. 如申請專利範圍第23項所述之封裝結構之製法，其中，該開口及該些盲孔係以雷射鑽孔方式形成者。
  28. 如申請專利範圍第23項所述之封裝結構之製法，其中，形成該導電體之材質係為金屬材。
  29. 如申請專利範圍第23項所述之封裝結構之製法，其中，該導電體係為柱狀或凹槽狀。
  30. 如申請專利範圍第23項所述之封裝結構之製法，其中，該堆疊件與該導電體係藉由複數導電元件相結合。
  31. 如申請專利範圍第23項所述之封裝結構之製法，復包括形成線路層於該介電層上，且該線路層電性連接該些導電體。
  32. 如申請專利範圍第23項所述之封裝結構之製法，復包括形成絕緣保護層於該增層部上，且外露該導電體。
  33. 如申請專利範圍第32項所述之封裝結構之製法，復包括形成封裝膠體於該絕緣保護層與該堆疊件之間。
  34. 如申請專利範圍第19項所述之封裝結構之製法，其中，該電子元件係為主動元件或被動元件。
  35. 如申請專利範圍第19項所述之封裝結構之製法，其中，該堆疊件與該增層部係藉由複數導電元件相結合。
  36. 如申請專利範圍第19項所述之封裝結構之製法，其中，該堆疊件係為第二基板或封裝件。
  37. 如申請專利範圍第36項所述之封裝結構之製法，其中，該第二基板係為線路板。
  38. 如申請專利範圍第19項所述之封裝結構之製法，其中，該堆疊件之寬度係小於該第一基板之寬度。
  39. 如申請專利範圍第38項所述之封裝結構之製法，復包括形成封裝膠體於該增層部與該堆疊件之間，且該封裝膠體係包覆該堆疊件。
  40. 如申請專利範圍第19項所述之封裝結構之製法，復包括形成封裝膠體於該增層部與該堆疊件之間。
  41. 如申請專利範圍第40項所述之封裝結構之製法，其中，該封裝膠體復形成於該第一基板與該堆疊件之間。
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