CN105633055A - 半导体封装结构及其制法 - Google Patents

半导体封装结构及其制法 Download PDF

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Publication number
CN105633055A
CN105633055A CN201410673881.3A CN201410673881A CN105633055A CN 105633055 A CN105633055 A CN 105633055A CN 201410673881 A CN201410673881 A CN 201410673881A CN 105633055 A CN105633055 A CN 105633055A
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layer
those
semiconductor package
line layer
dielectric layer
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CN201410673881.3A
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CN105633055B (zh
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萧惟中
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装结构及其制法，半导体封装结构包括介电层、第一线路层、多个导电柱、第二线路层以及多个突出构件。介电层具有相对的第一与第二表面，第一线路层嵌埋于介电层内并外露于第一表面，导电柱嵌埋于介电层内并外露于第二表面，且导电柱电性连接第一线路层，第二线路层形成于介电层的第二表面上并电性连接外露于第二表面的导电柱，突出构件形成于第一线路层上。藉此，本发明可藉由突出构件的较大接触面积以提升接合强度。

Description

半导体封装结构及其制法
技术领域
本发明涉及一种半导体封装结构及其制法，特别是指一种形成突出构件于线路层上的半导体封装结构及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品已逐渐迈向多功能及高性能的发展趋势。为满足半导体封装结构朝向高积集度(integration)及微型化(miniaturization)的封装需求，该半导体封装结构内的线路层的电性接触垫的宽度也愈来愈小。
但是，当透过多个导电凸块将晶片接置于该线路层的电性接触垫上，并对该些导电凸块进行回焊(reflow)制程时，该些导电凸块会形成软塌状态与外溢而影响电性连接，也导致相邻的两导电凸块容易互相电性连接而造成短路。此外，该电性接触垫的接触面为平面，使得该电性接触垫与该导电凸块的接触面积较小，故易导致彼此之间的接合强度不足而降低产品的信赖性。
图1A至图1D为绘示现有技术的半导体封装结构1及其制法的剖视示意图。
如图1A所示，先提供一承载板10，并形成具有多个电性接触垫111的线路层11于该承载板10上。
如图1B所示，形成具有相对的第一表面12a与第二表面12b的第一封装胶体12于该承载板10上以包覆该线路层11，且该第一封装胶体12的第二表面12b面向该承载板10。
如图1C所示，将图1B的整体结构上下倒置，并移除该承载板10，再将晶片13透过多个导电凸块14接置于该线路层11的电性接触垫111上。
如图1D所示，形成第二封装胶体15于该第一封装胶体12的第二表面12b上，以包覆该第二表面12b的线路层11、晶片13及导电凸块14。同时，自该第一封装胶体12的第一表面12a形成多个开孔121以分别外露出部分该线路层11，并植接多个焊球16于该些开孔121内以电性连接该线路层11。
然而，上述半导体封装结构1的缺点在于：将图1C的晶片13透过多个导电凸块14接置于线路层11的多个电性接触垫111上，并对该些导电凸块14进行回焊制程时，该些导电凸块14会形成软塌状态，使得该些导电凸块14的导电材料(如焊锡)往外溢出而影响电性连接，也导致相邻的两导电凸块14容易互相电性连接而造成短路。另外，该电性接触垫111的接触面112为平面，故该电性接触垫111与该导电凸块14的接触面积较小，使得该导电凸块14与该线路层11之间容易产生接合强度不足的问题，进而降低后续产品的信赖性。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
本发明提供一种半导体封装结构及其制法，可藉由突出构件的较大接触面积以提升接合强度。
本发明的半导体封装结构包括：介电层，其具有相对的第一表面与第二表面；第一线路层，其嵌埋于该介电层内并令该第一线路层的一表面外露于该介电层的第一表面；多个导电柱，其嵌埋于该介电层内并令各该导电柱一端外露于该介电层的第二表面，且该些导电柱分别电性连接该第一线路层；第二线路层，其形成于该介电层的第二表面上，并电性连接外露于该介电层的第二表面的该些导电柱；以及多个突出构件，其分别形成于该介电层的第一表面的第一线路层上。
该介电层为封装胶体或预浸体。该第一线路层具有多个第一电性接触垫，供该些突出构件分别形成于该些第一电性接触垫上。
该突出构件与该第一电性接触垫可为相同材质所形成者或一体成形者，而该突出构件的宽度可小于或等于该第一电性接触垫的宽度，且该突出构件可为另一导电柱或一导电迹线的焊垫。
该第二线路层具有多个第二电性接触垫，供该导电柱的相对第一端部与第二端部分别电性连接该第一线路层及该第二电性接触垫。
该半导体封装结构可包括绝缘保护层，其形成于该介电层的第二表面上以包覆该第二线路层，并外露部分该第二线路层。
本发明复提供一种半导体封装结构的制法，其包括：提供一具有相对的第一表面与第二表面的介电层，该介电层内嵌埋有一表面外露于该介电层的第一表面的第一线路层、及多个一端外露于该介电层的第二表面并电性连接该第一线路层的导电柱，且外露于该介电层的第一表面的第一线路层上形成有多个突出构件；以及形成第二线路层于该介电层的第二表面上以电性连接外露于该介电层的第二表面的该些导电柱。
该半导体封装结构的制法复包括下列步骤以提供该介电层：准备一具有相对的第一表面与第二表面的承载板；形成多个凹部于该承载板的第二表面；形成该些突出构件于该些凹部；形成该第一线路层于该承载板的第二表面；形成该些导电柱于该第一线路层上；以及形成该介电层。该些突出构件的下表面可齐平于该承载板的第二表面。
该第一线路层的制程可包括：形成一第一阻层于该承承载板的第二表面及该突出构件的下表面上；形成多个第一沟槽于该第一阻层；以及形成该第一线路层于该些第一沟槽内，且该第一线路层具有多个第一电性接触垫，以分别电性连接该些突出构件的下表面。
该些导电柱的制程可包括：形成一具有多个开孔的第二阻层于该第一阻层与该第一线路层上，且该些开孔分别外露出部分该第一线路层；以及形成该些导电柱于该些开孔内，且该些导电柱的第一端部分别电性连接外露于该些开孔的第一线路层。
该介电层的制程可包括：移除该第一阻层与该第二阻层以外露出该第一线路层及该些导电柱；以及形成该介电层于该承载板上，以包覆该第一线路层及导电柱并外露出该些导电柱的第二端部。
该第二线路层的制程可包括：形成一具有多个第二沟槽的第三阻层于该介电层的第二表面上，且该些第二沟槽外露出该些导电柱的第二端部及部分该介电层的第二表面；以及形成该第二线路层于该些第二沟槽内，且该第二线路层的多个第二电性接触垫分别电性连接该些导电柱的第二端部。
该半导体封装结构的制法可包括：移除该第三阻层，以外露出该介电层的第二表面及该第二线路层；以及形成绝缘保护层于该介电层的第二表面上，以包覆该第二线路层并外露部分该第二线路层。
该半导体封装结构的制法可包括：形成一具有至少一开口的框体于该承载板的第一表面上；依据该框体的开口移除部分该承载板；以及进行切单作业。
该半导体封装结构及其制法可包括：形成第一表面处理层于该第一线路层与该些突出构件的接触面上，或者形成第二表面处理层于该第二线路层上。
该半导体封装结构及其制法可包括：将半导体元件透过多个第一导电元件接置于该些突出构件上，且该些第一导电元件分别包覆该些突出构件的接触面，该第一导电元件可为凸块。
该半导体封装结构及其制法可包括：形成绝缘材于该介电层的第一表面与该半导体元件之间，以包覆该第一线路层及该些第一导电元件，且该绝缘材可为底胶或封装胶体。
该半导体封装结构及其制法可包括：形成多个第二导电元件于该第二表面处理层上以分别电性连接该第二线路层。
由上可知，本发明的半导体封装结构及其制法中，主要在第一线路层的多个第一电性接触垫上形成多个具有立体的接触面(如上表面和侧表面)的突出构件，以透过多个第一导电元件将半导体元件(如晶片)接置于该些突出构件上并包覆该些接触面。
藉此，该些突出构件不会于回焊制程中形成软塌状态，故可避免该些第一导电元件的导电材料(如焊锡)往外溢出而影响电性连接的状况，也可免除相邻的两第一导电元件互相电性连接而形成短路的情形。同时，该些突出构件具有较大的接触面积，故可提升该第一导电元件与该第一线路层的第一电性接触垫间的接合强度，从而提高后续产品的信赖性。
附图说明
图1A至图1D为绘示现有技术的半导体封装结构及其制法的剖视示意图；以及
图2A至图2Q为绘示本发明的半导体封装结构及其制法的剖视示意图，其中，图2L'为图2L的另一实施例。
主要组件符号说明
1、2半导体封装结构
10、20承载板
11线路层
111电性接触垫
112、221接触面
12第一封装胶体
12a、27a第一表面
12b、27b第二表面
121、251开孔
13晶片
14导电凸块
15第二封装胶体
16焊球
20a第一表面
20b第二表面
201凹部
21晶种层
22突出构件
220下表面
23第一阻层
231第一沟槽
24第一线路层
241第一电性接触垫
25第二阻层
26导电柱
26a第一端部
26b第二端部
27介电层
28第三阻层
281第二沟槽
29第二线路层
291第二电性接触垫
292侧表面
30绝缘保护层
31框体
311开口
32第一表面处理层
33第二表面处理层
34半导体元件
35第一导电元件
36第二导电元件
37绝缘材
S1移除线
S2切割线。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
同时，本说明书中所引用的如“上”、“一”、“第一”、“第二”、“表面”、“接触面”或“端部”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2Q为绘示本发明的半导体封装结构2及其制法的剖视示意图，其中，图2L'为图2L的另一实施例。
如图2A所示，先准备一具有相对的第一表面20a与第二表面20b的承载板20。该承载板20可为基板、中介板、金属板或不锈钢板等。
如图2B所示，以蚀刻或激光钻孔等方式，形成多个凹部201于该承载板20的第二表面20b。
如图2C所示，以溅镀或其他方式，形成晶种层(seedlayer)21于该承载板20的第二表面20b及该些凹部201的壁面(如内壁和底面)上。该晶种层21可为导电层等。
如图2D所示，形成多个突出构件22于该些凹部201的晶种层21上，且该些突出构件22的下表面220齐平于该晶种层21或该承载板20的第二表面20b。该突出构件22可为导电柱(如铜柱)或导电迹线的焊垫等。
如图2E所示，形成一第一阻层23于该第二表面20b的晶种层21及该突出构件22的下表面220上，并于该第一阻层23形成多个第一沟槽231。
接着，形成具有多个第一电性接触垫241的第一线路层24于该些第一沟槽231内，且该些第一电性接触垫241分别电性连接该些突出构件22的下表面220，俾使该第一线路层24上形成有该些突出构件22。
在本实施例中，该些突出构件22与该第一线路层24可先后形成或分别成形，并可为相同材质或不同材质。但在其他实施例中，该些突出构件22与该第一线路层24也可同时形成或一体成形，并可为相同材质。
如图2F所示，形成一具有多个开孔251的第二阻层25于该第一阻层23与该第一线路层24上，且该些开孔251分别外露出部分该第一线路层24。
接着，形成多个具有第一端部26a与第二端部26b的导电柱26于该些开孔251内，且该些导电柱26的第一端部26a分别电性连接外露于该些开孔251的第一线路层24。该导电柱26可为金属柱(如铜柱)等，且该导电柱26可为嵌埋或填充导电材料或金属材料于该第二阻层25的开孔251内所形成之。
如图2G所示，移除图2F的第一阻层23与第二阻层25，以外露出该晶种层21、第一线路层24及导电柱26。
如图2H所示，形成一具有相对的第一表面27a与第二表面27b的介电层27于该该承载板20的第二表面20b上，以包覆该第一线路层24及该些导电柱26并外露出该些导电柱26的第二端部26b，且该介电层27可为封装胶体或预浸体(prepreg)。藉此，可使该介电层27内嵌埋有该第一线路层24及该些导电柱26，并使该第一线路层24与该些导电柱26的第二端部26b分别外露于该介电层27的第一表面27a及第二表面27b。
如图2I所示，形成一具有多个第二沟槽281的第三阻层28于该介电层27的第二表面27b上，且该些第二沟槽281外露出该些导电柱26的第二端部26b及部分该介电层27的第二表面27b。
接着，形成一具有多个第二电性接触垫291的第二线路层29于该些第二沟槽281所外露的介电层27的第二表面27b上，且该些第二电性接触垫291分别电性连接该些导电柱26的第二端部26b。
如图2J所示，移除图2I的第三阻层28，以外露出该介电层27的第二表面27b及该第二线路层29的侧表面292。
接着，形成绝缘保护层30(如防焊层)于该介电层27的第二表面27b上，以包覆该第二线路层29并外露出部分该第二线路层29。
在本实施例中，该绝缘保护层30的高度高于该第二线路层29的高度。但在其他实施例中，该绝缘保护层30的高度也可等于该第二线路层29的高度，以使该绝缘保护层30齐平于该第二线路层29。
如图2K所示，可对应于例如该第一线路层24的外侧或周围，设置一具有至少一开口311的框体31于该承载板20的第一表面20a上。该框体31的形状可依据该开口311的数量而构成口字形、田字形或网状等，且该框体31的材质可为金属材料或防蚀材料以防止蚀刻。
如图2L所示，藉由蚀刻或其他方式，并依据图2K的开口311与移除线S1，自该框体31的开口311移除部分该承载板20，以外露出该晶种层21。
在其他实施例中，本发明也可不必形成有该晶种层21，从而直接外露出该介电层27的第一表面27a、第一线路层24、及突出构件22的接触面221(如上表面和侧表面)。
如图2L'所示，其为图2L的另一实施例。在图2L'中，本发明可不必设置有图2K的框体31，从而直接移除该承载板20以外露出该晶种层21。除此之外，图2L'的后续制程均可类似于下列图2M至图2Q所述的技术内容，故不再重复叙述。
如图2M所示，其接续上述图2L，并移除该开口311内的晶种层21，以外露出该开口311内的介电层27的第一表面27a、第一线路层24与突出构件22的接触面221。
如图2N所示，形成第一表面处理层32(如抗氧化层)于该第一线路层24与该些突出构件22的接触面221上，也可形成第二表面处理层33(如抗氧化层)于该第二线路层29上。
如图2O所示，依据图2N的切割线S2，自该框体31的开口311对图2N的整体结构进行切单(singulation)作业，以形成多个如图2O所示的半导体封装结构2。
如图2P所示，以覆晶(filpchip)方式将半导体元件34(如晶片)透过多个第一导电元件35(如凸块)接置于该些突出构件22上，且该些第一导电元件35分别包覆该些突出构件22的接触面221(如上表面和侧表面)上的第一表面处理层32，或再包覆该些第一电性接触垫241上的第一表面处理层32。同时，可形成多个第二导电元件36(如焊球)于该第二表面处理层33上，以分别电性连接该第二线路层29的多个第二电性接触垫291。
在其他实施例中，本发明可先接置该半导体元件34于该些突出构件22上，再对该半导体封装结构2进行切单作业。而且，本发明也可不必形成有该第一表面处理层32与该第二表面处理层33，从而直接将该些第一导电元件35包覆该些突出构件22的接触面221或再包覆该些第一电性接触垫241，并直接将该些第二导电元件36形成于该些第二电性接触垫291上。
如图2Q所示，形成绝缘材37于该介电层27的第一表面27a与该半导体元件34之间，以包覆该第一表面处理层32及该些第一导电元件35。在其他实施例中，当未形成有该第一表面处理层32时，该绝缘材37可直接包覆该第一线路层24。该绝缘材37可为底胶或封装胶体。
本发明还提供一种半导体封装结构2，如图2O至图2Q所示。该半导体封装结构2主要包括介电层27、第一线路层24、多个导电柱26、第二线路层29以及多个突出构件22。
该介电层27具有相对的第一表面27a与第二表面27b，且该介电层27可为封装胶体或预浸体。该第一线路层24嵌埋于该介电层27内并令该第一线路层24的一表面外露于该介电层27的第一表面27a，且该第一线路层24具有多个第一电性接触垫241。
该些导电柱26嵌埋于该介电层27内并令该导电柱26的一端外露于该介电层27的第二表面27b，各该导电柱26具有相对的第一端部26a与第二端部26b，而该第一端部26a电性连接该第一线路层24，且该导电柱26可为金属柱(如铜柱)等。
该第二线路层29形成于该介电层27的第二表面27b上，并电性连接外露于该第二表面27b的该些导电柱26，且该第二线路层29具有多个第二电性接触垫291，该导电柱26的第二端部26b电性连接该第二电性接触垫291。
该些突出构件22分别形成于该介电层27的第一表面27a的第一线路层24的该些第一电性接触垫241上，各该突出构件22具有接触面221，该接触面221可包括该突出构件22的上表面和侧表面，且该突出构件22的宽度可小于或等于该第一电性接触垫241的宽度。同时，该突出构件22与该第一电性接触垫241可为相同材质或不同材质所形成者，并可为一体成形或分别成形者，且该突出构件22可为导电柱(如铜柱)或导电迹线的焊垫等。
该半导体封装结构2可包括半导体元件34(如晶片)，其以覆晶方式并透过多个第一导电元件35接置于该些突出构件22上，且该些第一导电元件35分别包覆该些突出构件22的接触面221。该第一导电元件35为凸块。
该半导体封装结构2可包括第一表面处理层32(如抗氧化层)，其形成于该第一线路层24及该些突出构件22的接触面221上。
该些第一导电元件35分别包覆该些突出构件22的接触面221(如上表面和侧表面)的第一表面处理层32，或再包覆该些第一电性接触垫241的第一表面处理层32。
在其他实施例中，本发明也可不必形成有该第一表面处理层32，从而直接将该些第一导电元件35包覆该些突出构件22的接触面221、或再包覆该些第一电性接触垫241。
该半导体封装结构2可包括第二表面处理层33(如抗氧化层)，其形成于该第二线路层29上。
该半导体封装结构2可包括绝缘保护层30，其形成于该介电层27的第二表面27b上以包覆该第二线路层29。
该半导体封装结构2可包括多个第二导电元件36，其形成于该第二表面处理层33上，以分别电性连接该第二线路层29的该些第二电性接触垫291上。在其他实施例中，本发明也可不必形成有该第二表面处理层33，从而直接将该些第二导电元件36形成于该些第二电性接触垫291上。
该半导体封装结构2可包括绝缘材37，其形成于该介电层27的第一表面27a与该半导体元件34之间，以包覆该第一线路层24上的第一表面处理层32及该些第一导电元件35，且该绝缘材37可为底胶或封装胶体。
由上可知，本发明的半导体封装结构及其制法中，主要通过在第一线路层的多个第一电性接触垫上形成多个具有立体的接触面(如上表面和侧表面)的突出构件，以透过多个第一导电元件将半导体元件接置于该些突出构件上并包覆该些接触面。
藉此，该些突出构件不会于回焊制程中形成软塌状态，故可避免该些第一导电元件的导电材料(如焊锡)往外溢出而影响电性连接的状况，也可免除相邻的两第一导电元件互相电性连接而形成短路的情形。同时，该些突出构件具有较大的接触面积，故可提升该第一导电元件与该第一线路层的第一电性接触垫间的接合强度，从而提高后续产品的信赖性。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (29)

1.一种半导体封装结构，其包括：
介电层，其具有相对的第一表面与第二表面；
第一线路层，其嵌埋于该介电层内并令该第一线路层的一表面外露于该介电层的第一表面；
多个导电柱，其嵌埋于该介电层内并令各该导电柱一端外露于该介电层的第二表面，且该些导电柱分别电性连接该第一线路层；
第二线路层，其形成于该介电层的第二表面上，并电性连接外露于该介电层的第二表面的该些导电柱；以及
多个突出构件，其分别形成于外露该介电层的第一表面的第一线路层上。
2.如权利要求1所述的半导体封装结构，其特征为，该介电层为封装胶体或预浸体。
3.如权利要求1所述的半导体封装结构，其特征为，该第一线路层具有多个第一电性接触垫，供该些突出构件分别形成于该些第一电性接触垫上。
4.如权利要求3所述的半导体封装结构，其特征为，该突出构件与该第一电性接触垫为相同材质所形成者或一体成形者。
5.如权利要求3所述的半导体封装结构，其特征为，该突出构件的宽度小于或等于该第一电性接触垫的宽度。
6.如权利要求1所述的半导体封装结构，其特征为，该突出构件为另一导电柱或一导电迹线的焊垫。
7.如权利要求1所述的半导体封装结构，其特征为，该第二线路层具有多个第二电性接触垫，供该导电柱的相对第一端部与第二端部分别电性连接该第一线路层及该第二电性接触垫。
8.如权利要求1所述的半导体封装结构，其特征为，该结构还包括绝缘保护层，其形成于该介电层的第二表面上以包覆该第二线路层，并外露部分该第二线路层。
9.如权利要求1所述的半导体封装结构，其特征为，该结构还包括第一表面处理层，其形成于该第一线路层及该些突出构件的接触面上。
10.如权利要求1所述的半导体封装结构，其特征为，该结构还包括半导体元件，其透过多个第一导电元件接置于该些突出构件上，且该些第一导电元件分别包覆该些突出构件的接触面。
11.如权利要求10所述的半导体封装结构，其特征为，该结构还包括绝缘材，其形成于该介电层的第一表面与该半导体元件之间，以包覆该第一线路层及该些第一导电元件。
12.如权利要求11所述的半导体封装结构，其特征为，该绝缘材为底胶或封装胶体。
13.如权利要求10所述的半导体封装结构，其特征为，该第一导电元件为凸块。
14.如权利要求1所述的半导体封装结构，其特征为，该结构还包括第二表面处理层，其形成于该第二线路层上。
15.如权利要求14所述的半导体封装结构，其特征为，该结构还包括多个第二导电元件，其形成于该第二表面处理层上以分别电性连接该第二线路层。
16.一种半导体封装结构的制法，其包括：
提供一具有相对的第一表面与第二表面的介电层，该介电层内嵌埋有一表面外露于该介电层的第一表面的第一线路层、及多个一端外露于该介电层的第二表面并电性连接该第一线路层的导电柱，且外露于该介电层的第一表面的第一线路层上形成有多个突出构件；以及
形成第二线路层于该介电层的第二表面上以电性连接外露于该介电层的第二表面的该些导电柱。
17.如权利要求16所述的半导体封装结构的制法，其特征为，该制法还包括下列步骤以提供该介电层：
准备一具有相对的第一表面与第二表面的承载板；
形成多个凹部于该承载板的第二表面；
形成该些突出构件于该些凹部；
形成该第一线路层于该承载板的第二表面；
形成该些导电柱于该第一线路层上；以及
形成该介电层。
18.如权利要求17所述的半导体封装结构的制法，其特征为，该些突出构件的下表面齐平于该承载板的第二表面。
19.如权利要求17所述的半导体封装结构的制法，其特征为，该第一线路层的制程包括：
形成一第一阻层于该承载板的第二表面及该突出构件的下表面上；
形成多个第一沟槽于该第一阻层；以及
形成该第一线路层于该些第一沟槽内，且该些第一线路层具有多个第一电性接触垫，以分别电性连接该些突出构件的下表面。
20.如权利要求19所述的半导体封装结构的制法，其特征为，该些导电柱的制程包括：
形成一具有多个开孔的第二阻层于该第一阻层与该第一线路层上，且该些开孔分别外露出部分该第一线路层；以及
形成该些导电柱于该些开孔内，且该些导电柱的第一端部分别电性连接外露于该些开孔的第一线路层。
21.如权利要求20所述的半导体封装结构的制法，其特征为，该介电层的制程包括：
移除该第一阻层与该第二阻层，以外露出该第一线路层及该些导电柱；以及
形成该介电层于该承载板上，以包覆该第一线路层及该些导电柱并外露出该些导电柱的第二端部。
22.如权利要求21所述的半导体封装结构的制法，其特征为，该第二线路层的制程包括：
形成一具有多个第二沟槽的第三阻层于该介电层的第二表面上，且该些第二沟槽外露出该些导电柱的第二端部及部分该介电层的第二表面；以及
形成该第二线路层于该些第二沟槽内，且该第二线路层的多个第二电性接触垫分别电性连接该些导电柱的第二端部。
23.如权利要求22所述的半导体封装结构的制法，其特征为，该制法还包括：
移除该第三阻层，以外露出该介电层的第二表面及该第二线路层；以及
形成绝缘保护层于该介电层的第二表面上，以包覆该第二线路层并外露出部分该第二线路层。
24.如权利要求23所述的半导体封装结构的制法，其特征为，该制法还包括：
形成一具有至少一开口的框体于该承载板的第一表面上；
依据该框体的开口移除部分该承载板；以及
进行切单作业。
25.如权利要求16所述的半导体封装结构的制法，其特征为，该制法还包括形成第一表面处理层于该第一线路层与该些突出构件的接触面上。
26.如权利要求16所述的半导体封装结构的制法，其特征为，该制法还包括将半导体元件透过多个第一导电元件接置于该些突出构件上，且该些第一导电元件分别包覆该些突出构件的接触面。
27.如权利要求26所述的半导体封装结构的制法，其特征为，该制法还包括形成绝缘材于该介电层的第一表面与该半导体元件之间，以包覆该第一线路层及该些第一导电元件。
28.如权利要求16所述的半导体封装结构的制法，其特征为，该制法还包括形成第二表面处理层于该第二线路层上。
29.如权利要求28所述的半导体封装结构的制法，其特征为，该制法还包括形成多个第二导电元件于该第二表面处理层上以分别电性连接该第二线路层。
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