CN104425417A - 半导体装置及其制法与半导体结构 - Google Patents

半导体装置及其制法与半导体结构 Download PDF

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Publication number
CN104425417A
CN104425417A CN201310449992.1A CN201310449992A CN104425417A CN 104425417 A CN104425417 A CN 104425417A CN 201310449992 A CN201310449992 A CN 201310449992A CN 104425417 A CN104425417 A CN 104425417A
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conductive part
semiconductor
conductive
width
perforate
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CN104425417B (zh
Inventor
林长甫
姚进财
张宏铭
庄旻锦
黄富堂
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Abstract

一种半导体装置及其制法与半导体结构，该半导体装置包括：具有相邻的二连接垫的基板；半导体组件，具有对应于各该连接垫的焊垫与形成于该些焊垫上的凸块底下金属层；具有依序形成于该凸块底下金属层上的第一导电部与第二导电部的导电组件，其中，该第二导电部的宽度小于该第一导电部的宽度；以及形成于该第二导电部与该连接垫之间的焊球，用于连接该导电组件与该基板。藉此，本发明能避免相邻的导电组件间产生焊料桥接的情形，并降低该导电组件与该凸块底下金属层间的应力。

Description

半导体装置及其制法与半导体结构
技术领域
本发明涉及一种半导体装置及其制法与半导体结构，特别是指一种可提升良率的半导体装置及其制法与半导体结构。
背景技术
现有的覆晶式封装件(flip chip package)于芯片的焊垫上形成多个凸块，并藉由该些凸块将该芯片接置于基板上。由于该芯片的输出入(I/O)线路的数量增加及该些凸块间之间距缩小，使得该些凸块彼此之间容易产生焊料桥接(solder bridge)的问题，于是发展出铜柱(Cupillar)的结构，但随着各铜柱之间距持续缩小，相邻的铜柱间仍会产生焊料桥接的情形。
图1A与图1B为绘示现有技术的半导体装置及其制法的剖视示意图。
如图1A所示，先提供基板10以及芯片11，该基板10具有相邻的二连接垫101，该芯片11具有形成于其表面110上的二焊垫111、形成于该表面110及该些焊垫111上的介电层112、形成于该介电层112的开孔113所外露的焊垫111上的凸块底下金属层114、与形成于该介电层112上及该凸块底下金属层114的周缘的保护层115。接着，依序形成铜柱12与焊料13于该凸块底下金属层114上。
然后，如图1B所示，藉由该焊料13将该铜柱12接置于该基板10的连接垫101上，并形成胶体14于该基板10与该芯片11之间以包覆该铜柱12与该焊料13，藉此形成半导体装置1。
上述半导体装置1的缺点，在于相邻的二铜柱12的间距D太小，以致该二铜柱12容易产生焊料桥接的情形，如图1B所示的桥接处131。但若缩小该铜柱12的宽度W，则会减少该该铜柱12与该凸块底下金属层114间的接触面积而增加应力，因而导致该铜柱12与该凸块底下金属层114之间可能发生裂痕或断裂(crack)的状况。此外，无论是否缩小该铜柱12的宽度W，皆需于该芯片11的介电层112上形成该保护层115以减少该应力，使得该半导体装置1的生产成本上升。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的主要目的为提供一种半导体装置及其制法与半导体结构，能避免相邻的导电组件间产生焊料桥接的情形，提升该半导体装置与半导体结构的良率。
本发明的半导体装置，其包括：基板，其具有相邻的二连接垫；半导体组件，其具有对应于各该连接垫的焊垫与形成于该些焊垫上的凸块底下金属层；导电组件，其具有依序形成于该凸块底下金属层上的第一导电部与第二导电部，其中，该第二导电部的宽度小于该第一导电部的宽度；以及焊球，其形成于该第二导电部与该连接垫之间，俾连接该导电组件与该基板。
该半导体装置可包括胶体，其形成于该基板与该半导体组件之间，以包覆该导电组件及该焊球。
本发明还提供一种半导体结构，其包括：半导体组件，其具有相邻的二焊垫与形成于该些焊垫上的凸块底下金属层；以及导电组件，其具有依序形成于该凸块底下金属层上的第一导电部与第二导电部，其中，该第二导电部的宽度小于该第一导电部的宽度。
上述的半导体结构可包括焊料，其形成于该第二导电部上。
上述的半导体装置与半导体结构可包括形成于该半导体组件的表面及该些焊垫上的介电层，且该介电层具有第一开孔以外露出该些焊垫，该凸块底下金属层可形成于该介电层及该第一开孔所外露的焊垫上。
上述的半导体装置与半导体结构中，该凸块底下金属层的表面上可形成有第二开孔，该第一导电部可形成于该凸块底下金属层的表面上及第二开孔内。
本发明另提供一种半导体装置的制法，其包括：提供基板与半导体组件，该基板具有相邻的二连接垫，该半导体组件具有形成于其表面上且对应于各该连接垫的焊垫；形成金属层于该些焊垫上；形成第一导电部于该金属层上；形成第二导电部于该第一导电部上，且该第二导电部的宽度小于该第一导电部的宽度；以及形成焊球于该第二导电部与该连接垫之间，用于连接该导电组件与基板。
上述的半导体装置的制法可包括：形成介电层于该半导体组件的表面及该些焊垫上，且该介电层具有第一开孔以外露出该些焊垫，该金属层可形成于该介电层及该第一开孔所外露的焊垫上。
该金属层的表面上可形成有第二开孔，该第一导电部可形成于该金属层的表面上及该第二开孔内。
形成该第一导电部于该金属层上的步骤可包括：形成第一阻层于该金属层上，且该第一阻层具有第一开口以外露出该金属层；形成该第一导电部于该第一开口所外露的金属层上；以及移除该第一阻层。
形成该第二导电部于该第一导电部上的步骤可包括：形成第二阻层于该金属层及该第一导电部上，该第二阻层具有第二开口以外露出该第一导电部，且该第二开口的宽度小于该第一开口的宽度；以及形成该第二导电部于该第二开口内的第一导电部上。
形成该焊球于该第二导电部上的步骤可包括：形成焊料于该第二开口内的第二导电部上；进行加热以使该焊料形成该焊球；以及移除该第二阻层。
上述的半导体装置的制法可包括：移除该第一导电部的周缘所对应的金属层以外的金属层以形成凸块底下金属层；以及形成胶体于该基板与该半导体组件之间，以包覆该导电组件及该焊球。
上述的半导体装置及其制法与半导体结构中，该第二导电部的宽度可为该第一导电部的宽度的30%至70%。该第二导电部的高度可小于该第一导电部的高度，且该第二导电部的高度可为该第一导电部的高度的25%至50%。
上述的半导体装置及其制法与半导体结构中，该第一导电部与该第二导电部可为一体成形或分别形成，并可为相同材质或不同材质。该导电组件可为铜柱，该第一导电部与该第二导电部的材质可为铜材。
由上可知，本发明的半导体装置及其制法与半导体结构，主要在半导体组件的凸块底下金属层上依序形成导电组件的第一导电部与第二导电部，且该第二导电部的宽度小于该第一导电部的宽度，该第二导电部的高度也可小于该第一导电部的高度。
因此，本发明无须使用现有技术的保护层，故可降低该半导体装置与半导体结构的生产成本。同时，本发明的第一导电部的宽度可大于现有技术的铜柱的宽度，以增加该第一导电部与该凸块底下金属层间的接触面积而降低应力。此外，本发明的第二导电部的宽度则可小于现有技术的铜柱的宽度，以增加相邻的第二导电部间的间距而避免产生焊料桥接的情形，进而提升该半导体装置与半导体结构的良率。
附图说明
图1A与图1B为绘示现有技术的半导体装置及其制法的剖视示意图；
图2A至图2N为绘示本发明的半导体装置及其制法的第一实施例的剖视示意图；以及
图3为绘示本发明的半导体装置的第二实施例的剖视示意图。
符号说明
1、2、2'           半导体装置
10、20             基板
101、201           连接垫
11                 芯片
110、210、221、241 表面
111、211           焊垫
112、212           介电层
113                开孔
114、223           凸块底下金属层
115                保护层
12                 铜柱
13、28             焊料
131                桥接处
14、29             胶体
21                 半导体组件
213                第一开孔
22                 金属层
222                第二开孔
23                 第一阻层
231                第一开口
24                 第一导电部
25                 第二阻层
251                第二开口
26                 第二导电部
27                 导电组件
28'                焊球
D、D1              间距
H1、H2             高度
S                  线段
W、W1、W2          宽度。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
同时，本说明书中所引用的如「上」、「一」、「第一」、「第二」及「表面」等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2N为绘示本发明的半导体装置及其制法的第一实施例的剖视示意图。
如图2A所示，先提供如半导体芯片的半导体组件21，其具有形成于其表面210上且彼此相邻的二焊垫211、与形成于该表面210及该些焊垫211上的介电层212，该介电层212具有第一开孔213以外露出该些焊垫211。
如图2B所示，形成金属层22于该半导体组件21的介电层212及该第一开孔213所外露的焊垫211上，且该金属层22的表面221上形成有第二开孔222，但不以此为限。
在其它实施例中，该金属层22可直接形成于该半导体组件21的表面210及焊垫211上，而该金属层22的表面221上也可不形成有该第二开孔222。
如图2C所示，形成第一阻层23于该金属层22的表面221上，该第一阻层23具有对应于该些焊垫211的第一开口231以外露出该金属层22的表面221及第二开孔222，且该第一开口231的宽度为W1。
如图2D所示，以电镀或其它方式形成第一导电部24于该第一开口231所外露的金属层22的表面221及第二开孔222上，且该第一导电部24的宽度与高度分别为W1及H1。
如图2E所示，移除第一阻层23。
如图2F所示，形成第二阻层25于该金属层22及该第一导电部24上，该第二阻层25具有第二开口251以外露出该第一导电部24的表面241，且该第二开口251的宽度W2小于该第一开口231的宽度W1。
如图2G所示，以电镀或其它方式形成第二导电部26于该第二开口251内的第一导电部24上，使第一导电部24与第二导电部26结合成导电组件27。
该第二导电部26的宽度W2小于该第一导电部24的宽度W1，该第二导电部26的高度H2小于该第一导电部24的高度H1，该第一导电部24的形状为T字形，该第二导电部26的形状为一字形，该导电组件27的形状为类似十字形，但不以此为限。
如图2H所示，形成焊料28于该第二开口251内的第二导电部26上。
如图2I所示，移除第二阻层25。
如图2J所示，以蚀刻或其它方式沿着线段S移除该第一导电部24的周缘所对应的金属层22以外的金属层22，以形成类似U字形或V字形的凸块底下金属层223。
如图2K所示，进行加热以使该焊料28形成焊球28'。
如图2L所示，将图2K的整体结构上下翻转，并将该焊球28'对应于该基板20的连接垫201。
相较于现有技术图1A中相邻的二铜柱12的间距为D，本发明中相邻的二第二导电部26的间距为D1且其大于该间距D，以避免相邻的第二导电部26间产生焊料桥接的情形。
如图2M所示，藉由该焊球28'将该第二导电部26接置于该连接垫201上，以电性连接该导电组件27及该基板20。
如图2N所示，形成胶体29于该基板20与该半导体组件21的介电层212之间，以包覆该基板20、连接垫201、介电层212、凸块底下金属层223、导电组件27及该焊球28'。
本发明还提供一种半导体结构，其包括半导体组件21以及导电组件27。
该半导体组件21具有相邻的焊垫211与形成于该些焊垫211上的凸块底下金属层223。该导电组件27具有依序形成于该凸块底下金属层223上的第一导电部24与第二导电部26，其中，该第二导电部26的宽度W2小于该第一导电部24的宽度W1，而该第二导电部26的高度H2也可小于该第一导电部24的高度H1。
该半导体结构可包括焊料28，其形成于该第二导电部26上。
在本实施例中，该第二导电部26的宽度W2可为该第一导电部24的宽度W1的30%至70%，该第二导电部26的高度H2可为该第一导电部24的高度H1的25%至50%，但不以此为限。该第一导电部24与该第二导电部26为一体成形或分别形成，并可为相同材质或不同材质。该导电组件27可为铜柱或其它导电体，该第一导电部24与该第二导电部26的材质可为铜材或其它导电材料。
该半导体组件21可具有形成于其表面210及该些焊垫211上的介电层212，且该介电层212具有第一开孔213以外露出该些焊垫211，该凸块底下金属层223可形成于该介电层212及该第一开孔213所外露的焊垫211上。
该凸块底下金属层223的表面221上可形成有第二开孔222，该第一导电部24可形成于该凸块底下金属层223的表面221上及第二开孔222内。
本发明另提供一种半导体装置，如图2N所示。半导体装置2包括基板20、半导体组件21、导电组件27以及焊球28'。
该基板20具有相邻的二连接垫201。该半导体组件21具有对应于各该连接垫201的焊垫211与形成于该些焊垫211上的凸块底下金属层223。
该导电组件27具有依序形成于该凸块底下金属层223上的第一导电部24与第二导电部26，其中，该第二导电部26的宽度W2小于该第一导电部24的宽度W1。该焊球28'形成于该第二导电部26与该连接垫201之间。
在本实施例中，该第二导电部26的宽度W2可为该第一导电部24的宽度W1的30%至70%，该第二导电部26的高度H2可为该第一导电部24的高度H1的25%至50%，但不以此为限。该第一导电部24与该第二导电部26为一体成形或分别形成，并可为相同材质或不同材质。该导电组件27可为铜柱或其它导电体，该第一导电部24与该第二导电部26的材质可为铜材或其它导电材料。
该半导体组件21可具有形成于其表面210及该些焊垫211上的介电层212，且该介电层212具有第一开孔213以外露出该些焊垫211，该凸块底下金属层223可形成于该介电层212及该第一开孔213所外露的焊垫211上。
该凸块底下金属层223的表面221上可形成有第二开孔222，该第一导电部24可形成于该凸块底下金属层223的表面221上及第二开孔222内。
该半导体装置2也可包括胶体29，其形成于该基板20与该半导体组件21的介电层212之间，以包覆该基板20、连接垫201、介电层212、凸块底下金属层223、导电组件27及该焊球28'。
图3为绘示本发明的半导体装置的第二实施例的剖视示意图。图3的半导体装置2'与上述图2N的半导体装置2大致相同，其主要差异如下：
在图3中，该凸块底下金属层223的表面221上未形成有图2N的第二开孔222，且该凸块底下金属层223、第一导电部24及第二导电部26的形状均为一字形，该导电组件27的形状可为T字形。
由上可知，本发明的半导体装置及其制法与半导体结构，主要通过在半导体组件的凸块底下金属层上依序形成导电组件的第一导电部与第二导电部，且该第二导电部的宽度小于该第一导电部的宽度，该第二导电部的高度也可小于该第一导电部的高度。
因此，本发明无须使用现有技术图1A与图1B的保护层，故可降低该半导体装置与半导体结构的生产成本。同时，本发明的第一导电部的宽度(如50μm)可大于现有技术的铜柱的宽度(如40μm)，以增加该第一导电部与该凸块底下金属层间的接触面积而降低应力。此外，本发明的第二导电部的宽度(如30μm)则可小于现有技术的铜柱的宽度(如40μm)，以增加相邻的第二导电部间的间距而避免产生焊料桥接的情形，进而提升该半导体装置与半导体结构的良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (31)

1.一种半导体装置，其包括：
基板，其具有相邻的二连接垫；
半导体组件，其具有对应于各该连接垫的焊垫与形成于该些焊垫上的凸块底下金属层；
导电组件，其具有依序形成于该凸块底下金属层上的第一导电部与第二导电部，其中，该第二导电部的宽度小于该第一导电部的宽度；以及
焊球，其形成于该第二导电部与该连接垫之间，以连接该导电组件与该基板。
2.根据权利要求1所述的半导体装置，其特征在于，该装置还包括形成于该半导体组件的表面及该些焊垫上的介电层，且该介电层具有第一开孔以外露出该些焊垫，该凸块底下金属层形成于该介电层及该第一开孔所外露的焊垫上。
3.根据权利要求1所述的半导体装置，其特征在于，该凸块底下金属层的表面上形成有第二开孔，该第一导电部形成于该凸块底下金属层的表面上及第二开孔内。
4.根据权利要求1所述的半导体装置，其特征在于，该第二导电部的宽度为该第一导电部的宽度的30%至70%。
5.根据权利要求1所述的半导体装置，其特征在于，该第二导电部的高度小于该第一导电部的高度。
6.根据权利要求5所述的半导体装置，其特征在于，该第二导电部的高度为该第一导电部的高度的25%至50%。
7.根据权利要求1所述的半导体装置，其特征在于，该第一导电部与该第二导电部为一体成形或分别形成。
8.根据权利要求1所述的半导体装置，其特征在于，该第一导电部与该第二导电部为相同材质或不同材质。
9.根据权利要求1所述的半导体装置，其特征在于，该导电组件为铜柱，该第一导电部与该第二导电部的材质为铜材。
10.根据权利要求1所述的半导体装置，其特征在于，该装置还包括胶体，其形成于该基板与该半导体组件之间，以包覆该导电组件及该焊球。
11.一种半导体装置的制法，其包括：
提供基板与半导体组件，该基板具有相邻的二连接垫，该半导体组件具有形成于其表面上且对应于各该连接垫的焊垫；
形成金属层于该些焊垫上；
形成第一导电部于该金属层上；
形成第二导电部于该第一导电部上，且该第二导电部的宽度小于该第一导电部的宽度；以及
形成焊球于该第二导电部与该连接垫之间，以连接该导电组件与基板。
12.根据权利要求11所述的半导体装置的制法，其特征在于，该制法还包括形成介电层于该半导体组件的表面及该些焊垫上，且该介电层具有第一开孔以外露出该些焊垫，该金属层形成于该介电层及该第一开孔所外露的焊垫上。
13.根据权利要求11所述的半导体装置的制法，其特征在于，该金属层的表面上形成有第二开孔，该第一导电部形成于该金属层的表面上及该第二开孔内。
14.根据权利要求11所述的半导体装置的制法，其特征在于，该第二导电部的宽度为该第一导电部的宽度的30%至70%。
15.根据权利要求11所述的半导体装置的制法，其特征在于，该第二导电部的高度小于该第一导电部的高度。
16.根据权利要求15所述的半导体装置的制法，其特征在于，该第二导电部的高度为该第一导电部的高度的25%至50%。
17.根据权利要求11所述的半导体装置的制法，其特征在于，形成该第一导电部于该金属层上的步骤包括：
形成第一阻层于该金属层上，且该第一阻层具有对应于该些焊垫的第一开口以外露出该金属层；
形成该第一导电部于该第一开口所外露的金属层上；以及
移除该第一阻层。
18.根据权利要求17所述的半导体装置的制法，其特征在于，形成该第二导电部于该第一导电部上的步骤包括：
形成第二阻层于该金属层及该第一导电部上，该第二阻层具有第二开口以外露出该第一导电部，且该第二开口的宽度小于该第一开口的宽度；以及
形成该第二导电部于该第二开口内的第一导电部上。
19.根据权利要求18所述的半导体装置的制法，其特征在于，形成该焊球于该第二导电部上的步骤包括：
形成焊料于该第二开口内的第二导电部上；
进行加热以使该焊料形成该焊球；以及
移除该第二阻层。
20.根据权利要求11所述的半导体装置的制法，其特征在于，该制法还包括移除该第一导电部的周缘所对应的金属层以外的金属层以形成凸块底下金属层。
21.根据权利要求11所述的半导体装置的制法，其特征在于，该制法还包括形成胶体于该基板与该半导体组件之间，以包覆该导电组件及该焊球。
22.一种半导体结构，其包括：
半导体组件，其具有相邻的二焊垫与形成于该些焊垫上的凸块底下金属层；以及
导电组件，其具有依序形成于该凸块底下金属层上的第一导电部与第二导电部，其中，该第二导电部的宽度小于该第一导电部的宽度。
23.根据权利要求22所述的半导体结构，其特征在于，该结构还包括焊料，其形成于该第二导电部上。
24.根据权利要求22所述的半导体结构，其特征在于，该结构还包括形成于该半导体组件的表面及该些焊垫上的介电层，且该介电层具有第一开孔以外露出该些焊垫，该凸块底下金属层形成于该介电层及该第一开孔所外露的焊垫上。
25.根据权利要求22所述的半导体结构，其特征在于，该凸块底下金属层的表面上形成有第二开孔，该第一导电部形成于该凸块底下金属层的表面上及第二开孔内。
26.根据权利要求22所述的半导体结构，其特征在于，该第二导电部的宽度为该第一导电部的宽度的30%至70%。
27.根据权利要求22所述的半导体结构，其特征在于，该第二导电部的高度小于该第一导电部的高度。
28.根据权利要求27所述的半导体结构，其特征在于，该第二导电部的高度为该第一导电部的高度的25%至50%。
29.根据权利要求22所述的半导体结构，其特征在于，该第一导电部与该第二导电部为一体成形或分别形成。
30.根据权利要求22所述的半导体结构，其特征在于，该第一导电部与该第二导电部为相同材质或不同材质。
31.根据权利要求22所述的半导体结构，其特征在于，该导电组件为铜柱，该第一导电部与该第二导电部的材质为铜材。
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