六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種微間 距凸塊結構及其製程。 【先前技術】 先進的晶圓級封裴與覆晶接合技術的發展日益成 熟’目前研發的主要重點之一為微間距凸塊的設置，以 因應積體電路封裝技術之微型化與高密度化的開發。而 所謂凸塊的微間距係指相鄰凸塊的中心點到中心點的距 離控制在1 50微米（// m)以内。對於可攜式及高性能微電 子產品而言，縮短凸塊的微間距距離.將有助於產品短、 小、輕、薄的需求’是以微間距凸塊的應用已漸成為高 密度積體電路封裝的主流。由於微間距凸塊之間的距離 過近’常會因凸塊接合材料之橋接而產生短路問題，尤 其當晶片覆晶結合至基板時，因微間距凸塊之接合材料 可能彼此電性連接’而造成非預期的短路現象。 如第1圖所示者為習知微間距凸塊結構1 〇〇，用以設 置於一晶片20之一銲墊21上，該晶片20之一表面22 形成有一保護層23，係局部包覆該銲墊21之周邊。該 微間距凸塊結構1〇〇係包含一底座11〇、一基礎層12〇 以及一回焊銲料13〇β該底座11〇係接合於該銲墊2ι並 延伸到該保護層23上。該基礎層12〇係形成於該底座 110，該基礎層120係具有一頂面121與一侧面122。依 照目前的晶圓電鍍技術，該頂面121係面積等於該底座 3 。心回焊銲料130形成於該基礎層120之該頂面121， 、回焊銲料13G的厚度或體積約為相等於基礎層120的 厚度（或體積）’該回焊銲# 13〇在回焊步帮之後會形成 W㈣°^用以電鍍形成該基礎層12G的光阻層（圖 未會出）必須不可移除’該半球狀的回焊銲料13G的邊緣 基礎層12()之該侧面122。若該回烊銲料13〇 在回焊時光®層6移除則會回包汙染至該基礎層120的 侧面122，造成擴散汙染。此外，該基礎層12G的材料 為熔點高於該回焊銲料13〇的銲料，即使覆晶接合與回 焊時未達到該基礎層12〇的熔點，仍會與該回焊銲料13〇 互炫’並易有變形之問題。 此外，如第2圖所示者為習知晶片以微間距凸塊結構 覆^…^至基板之截面示意圖。施加一預定之溫度與 壓力使得該晶片20覆晶結合至該印刷電路板丨〇上藉 由該微間距凸塊結構刚焊接至該印刷電路板ig之對應 凸塊接墊12。因為該半球狀的回焊銲料13〇已橫向地外 擴於該基礎層120之該側面122。所以在受到結合壓力 之影響下更容易被擠出至該基礎層12〇之該側面122, 造成擴散汙染。更甚者，會造成相鄰的回焊銲料13〇相 接觸而造成電信短路（Short)，導致覆晶接合的良率降低。 基於上述的問題點，習知的微間距凸塊結構易因凸塊 接合材料之橋接而造成短路問題。因此，在現今微間距 凸塊技術中需更多改變與改善以解決上述問題。 【發明内容】 為了解決上述之門eg r Λ v 猶…几 主要目的係在於提供 種微間距凸塊結構及苴费 β曰 ，、製程達成微間距凸塊結構在 片上可為微間距钟里#。十 1距叹置並且不會有接合材料橋接之短路 問題，並能增進在媒技 逆任誶接後之應力緩衝。此外，電鍍 層能被集中有效率谁并+s拉 .^ ° 半進仃知接，以達成微間距覆晶接合 免用回焊的低溫熱壓合焊接。 σ… 本發明'次—目的係在於提供一種微間距凸塊結構 、’程避免凸塊接合材料在焊接時的擴散汗染。 本發明之再-目的係在於提供一種微間距凸塊結構 及其製程’以增進防止凸塊接合材料擴散汙染之功效。 本發明之再一目的係在於提供一種微間距凸塊結構 及其製程’以提高製程良率與降低製造成本，並能解決 習知凸塊接合材料需要回焊而回包汙染至基礎層的側 面。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種微間距凸塊結構，用以設 置於一晶片之一銲#上，該晶片之一表面形&有一保護 層’係局部包覆該銲墊之周$，該微間距凸塊結構係包 3 一底座、一電鍍基礎層以及一電鍍接合層。該底座係 接合於該銲墊並延伸到該保護層上。該電鍍基礎層係形 成於該底座，該電鍍基礎層係具有一頂面與—侧面。該 電錢接合層係僅形成於該電鍍基礎層之該頂面，而顯露 u侧面’其中該頂面係面積小於該底座’用以限制該電 鍍接合層。本發明另揭示一種微間距凸塊結構之製程。 i?m25 . 本發明的目的及解決其技術問題還可採用以下技術 v 措施進一步實現。 在前述的微間距凸塊結構中，該側面係可為傾斜壁以 使該電鍍基礎層為半錐形。 在前述的微間距凸塊結構中，該電鍍基礎層係可具有 • 一狹槽’用以縮小該頂面之面積。 在前述的微間距凸塊結構中，該狹槽係可貫穿至顯露 出該底座。 • 在前述的微間距凸塊結構中，該電鍍基礎層之該頂面 係可形成為一碗狀承座。 在前述的微間距凸塊結構中，該電鍍接合層係可為全 金屬。 在前述的微間距凸塊結構中，該電鍍基礎層係可為一 鋼柱’該電鍍接合層之材質係選自於錫'銀、錫雜與無 紐銲料之其令之一。 Φ 在前述的微間距凸塊結構中，該電鍍接合層之厚度係 可不大於該電鍍基礎層之二分之一厚度。 在前述的微間距凸塊結構中，該電鍍接合層係可具有 連續側面，係連續地連接該電锻基礎層之該侧面。 在前述的微間距凸塊結構中，該電鍍接合層係可更具 有一頂面，係小於該電鍍基礎層之該頂面。 此外，本發明另揭示一種微間距凸塊結構，用以設置 於一晶片之一銲墊上，該晶片之一表面形成有—保護 層’係局部包覆該銲墊之周邊，該微間距凸塊結構係包 6 . 含一底座、一電鍍基礎層、一圖案化電鍍接合層。該底 v 座係接合於該銲墊並延伸到該保護層上，該電鍍基礎層 係形成於該底座，該電鍍基礎層係具有一頂面與一側 面’該圖案化電鍍接合層係僅形成於該電鍍基礎層之該 頂面，而顯露該側面，並且該圖案化電鍍接合層之覆蓋 . 面積係小於該頂面》 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 • 在前述的微間距凸塊結構中’該圖案化電鍍接合層係 可具有單一個微凸塊之形狀。 在前述的微間距凸塊結構中，該圖案化電鍍接合層係 可具有由複數個分離微凸塊所組成之圖案。 在前述的微間距凸塊結構中，該電鍍接合層之厚度係 可不大於該電鍍基礎層之二分之一厚度。 由以上技術方案可以看出，本發明之微間距凸塊結構 及其製程，具有以下優點與功效： 鲁一、可藉由改變電鍍基礎層之頂面以致使其面積小於底 座以限制電鍍接合層的方式並加以組合電鍍接合層 的電鑛形成方式作為其中一技術手段，使電鍍接合 層集中形成於受限的縮小面積内並且自然產生不需 要回焊的一體化複合式凸塊形狀，故能達成微間距 凸塊結構在晶片上可為微間距設置並且不會有接合 材料橋接之短路問題’並能增進在焊接後之應力緩 衝。此外，電鍍接合層能被集中有效率進行焊接， 7 故電鑛接合層與電鍍基礎層的厚度（或 V X鐙積）比值能 降低，例如達到電鍍接合層厚度不大於電铲美礎層 之二分之一厚度，以達成微間距覆晶 Α ,克用回 焊的低溫熱壓合焊接。 二、 可藉由改變電鍍基礎層之頂面以致使其面積小於底 座以限制電鍵接合層的方式並加以組合電鍍基礎層 與電鑛接合層皆為電鍵形成之方式料其中—技4 手段，使得電鍍接合層僅形成於電鍍基礎層之頂面 而顯露電鍍基礎層之侧面’能避免凸塊接合材料(即 電鍍接合層）在焊接時的擴散汙染。 三、 可藉由電鍍基礎層具有之狹槽或是電鍍基礎層之頂 面形成之碗狀承座等形狀改變作為其中一技術手 段’可以收容覆晶接合時被擠出之電鍍接合層或減 少被擠出量’以增進防止擴散汙染之功效。 四、 可藉由電艘基礎層的侧面與電鑛接合層的側面為連 續地連接以作為其巾—技術手段，在錢製程中 可共用一光阻層，ν+ 增 以乂尚製程良率與降低製造成 本’並能解決習知凸塊接合材料需要回焊而回包汙 染至基礎層的側面。 ) 以下將配合所附圖示詳細說明本發明之實施例，然 注意的是’該些圖示均為簡化之示意冑，僅以示意方 來說明本發明之基本架構 _ _ 傅4貫施方法，故僅顯示與本 有關之元件與組合關係 係，圖t所顯示之元件並非以實 4 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 ¥ 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種微間距凸塊結構 舉例說明於第3圖之截面示意圖。該微間距凸塊結構2〇〇 係用以設置於一晶片20之—銲墊21上，該晶片2〇之一 表面22形成有一保護層（passivati〇n [叮以）23，係局部 • 包覆該銲墊21之周邊，可提供保護該表面22上。該表 面22係為該晶片20之主動面，該表面22係設有積體電 路70件（圖中未繪出），如微控制器、微處理器、記憶體、 邏輯電路、特殊應用積體電路（如顯示器驅動電路）等或 上述之組合。該銲墊2 1係為連接積體電路之對外端點， 其材質通常為鋁、銅或鉻。該保護層23之材質係為電絕 緣材料所構成的表面層，例如一氮矽化合物層、一氧矽 化合物層、一磷矽玻璃層或上述材質之組合。該保護層 • 23具有至少-開口以暴露該鲜塾21。 • 如第3圖所示，該微間距凸塊結構200係包含一底座 -21G、—電鍍基礎層22 G以及-電鐘接合層23 0。該底座 210係接合於該銲墊21並延伸到該保護層23上。該底 座210係可提供該鲜墊21與該電鍍基礎層22〇之間的連 結。該底座210通常由附著層、擴散阻障層及接著層所 構成，該底座210為一複合金屬層，可為鉻/鉻鈉/銅 (Cr/CrCu/Cu)、鈦 / 鋼 / 鎳（Ti/Cu/Ni)、鋁 / 鎳釩 / 銅 (S3 9 (A1/NlV/Cu)及無電鍍鎳/金（Ni/Au)等。該底座210的形 成係可利用電子束蒸鍍、磁控濺鍍或無電鍍等方法形成。 該電鐘基礎層220係形成於該底座210，而該電鍍基 礎層220係具有一頂面221與一側面222。其中，該側 面222係可為傾斜壁以使該電鍍基礎層220為半錐形， 藉以縮小該頂面221之面積。更具體地，該電鍍基礎層 220係可為一銅柱（c〇pper pi丨丨訂）。銅柱具有耐高溫與不 變形的特性，能使該電鍍基礎層220發揮良好的間隔維 持作用’不會在覆晶接合之過程造成凸塊的過度潰陷， 並且銅柱可由電鑛方式低成本的形成。此外，本發明所 稱之「柱」係指一物件的高度大於該物件之長度也大於 該物件之寬度，或者是大於該物件之端面直徑。故該電 鑛基礎層220以細長狀為較佳，可達到微間距的高密度 配置》 該電鑛接合層230係僅形成於該電鍍基礎層22〇之該 頂面221，而顯露該侧面222,其中該頂面221係面積小 於該底座210，用以限制該電鍍接合層23 〇。具體而言， 該電鑛接合層230係可為全金屬。詳細而言，該電鑛接 合層230之材質係可選自於踢、银、錫錯與無錯銲料之 其中之一。該電錢接合層23 0的熔點應低於該電鍍基礎 層220的熔點’並可電鍵形成。當該電錄接合層230可 由電鍍形成，便可省略回焊步驟並能在有限的頂面221 上產生平坦的層狀物’不會回包到該電錄基礎層220之 該侧面222 » [S3 10 較佳地，再如筮^ s 221 # ^rr S不，I電鍍基礎層220之該頂 面22广形成為一碗狀承座，在中央為下凹周邊則 接近平坦。該碗狀承座可減少在 復BB接合時被擠出之電 鍵接合層230的被擠出量 ：:皮撥出之： L ^ ^ ^ 日運防止擴散汙染之功 效。較佳地，該電鍍基礎層 〈側面222係可為傾斜 壁以使該電艘基礎層220為__ 马手錐形，可呈現底部大且頂 部小之收敛狀，以用來限制.該電錢接合層23〇之形成面 積。該電鍍接合層230係僅形成於該電鍍基礎層—之 該頂面22卜而顯露該側面222’其中該頂面221係面積 小於該底座210,用以限制該電鍍接合層23〇。因此該 電鍍接合層230能被集中有效率地進行焊接。當該電鍍 接合層230與該電鍍基礎層22〇的厚度比值固定於一預 定值時，該電鐘接合層230的體積能磚少。在本實施例 中’該電锻接合層230之厚度H1係可不大於該電鍵基 礎層220之二分之一厚度H2(如第3圓所示）。因此，利 用該電鍵接合層230的電鑛形成形狀、位置，微間距覆 晶接合可採用免用回焊的低溫熱壓焊接方法達成，同時 不會有接合材料橋接之短路問題，並能增進在焊接後之 應力緩衝之優點。 該電鍍接合層230係可具有一連續侧面23 1，係連續 地連接該電鍍基礎層220之該側面222。此一技術手段 可在電鍍製程中共用一光阻層（容後詳述），以提高製程 良率與降低製造成本，並能解決習知凸塊接合材料需要 回焊而回包汙染至該電鍍基礎層220的側面222。另外， m 11 f3S0^25 % 該電鑛接合層230係可更具有一頂面232，係小於該電 鐘基礎層220之該頂面221，以使微間距凸塊呈現為收 斂狀。 請參閱第4A至4H圖為依據本發明之第一具體實施 例的微間距凸塊結構在製程中元件之截面示意圖。本發 明進一步說明該微間距凸塊結構之製程，以彰顯本案的 功效。 首先’如第4A圖所示’提供一晶片2〇，該晶片2〇 之一表面22具有複數個銲墊2卜該晶片20之一表面22 形成有一保護層23’係局部包覆該些銲墊21之周邊。 該晶片20可形成於一晶圓。 接著’如第4B圖所示’形成一凸塊下金屬層3〇,係 覆蓋於該保護層23之上並接合於該銲墊21。該凸塊了 金屬30係作為凸塊的基底與電鍍種子層，具有附著於晶 片之銲塾21和該保護層23之性能。其中，該凸塊下金 屬層3〇係能以濺鍍方法形成 之後’如第4C圖所示’形成一光阻層40於該凸塊 下金屬層30上《該光阻層40係可為感光性介電材料， 可利用塗佈或貼附方式形成於該凸塊下金屬層30上。 之後’如第4D圖所示’曝光顯影該光阻層40，以使 該光阻層40形成有一對應該銲墊21之開孔41，以顯露 該凸塊下金屬層30之一部位31，該部位31為上述電鍍 基礎層222的預定形成位置。更具體地，上述曝光顯影 該先阻層40之步驟係包含等向性顯影（Is〇tr〇py [S3 12 13804-25 ψ • D—g)，以使該開孔41有傾斜的孔壁。例如，該VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a micro-pitch bump structure and a process therefor. [Prior Art] The development of advanced wafer level sealing and flip chip bonding technology is becoming more and more mature. One of the main focuses of the current research and development is the setting of micro pitch bumps to meet the miniaturization and high density of integrated circuit packaging technology. Development. The so-called micro-pitch of the bumps means that the distance from the center point to the center point of the adjacent bumps is controlled within 1 50 micrometers (//m). For portable and high-performance microelectronics, shortening the micro-pitch distance of the bumps will help the product to be short, small, light and thin. The application of micro-pitch bumps has become a high-density product. The mainstream of bulk circuit packaging. Since the distance between the micro-pitch bumps is too close, the short-circuit problem often occurs due to the bridging of the bump bonding materials, especially when the wafer is flip-chip bonded to the substrate, because the bonding materials of the micro-pitch bumps may be electrically connected to each other' Causes an unexpected short circuit. As shown in FIG. 1 , the conventional micro pitch bump structure 1 is disposed on one of the pads 21 of a wafer 20 . One surface 22 of the wafer 20 is formed with a protective layer 23 and is partially covered. The periphery of the pad 21. The micro pitch bump structure 1 includes a base 11 〇, a base layer 12 〇, and a reflow solder 13 〇 β. The base 11 is spliced to the pad 2 and extends to the protective layer 23. The base layer 12 is formed on the base 110, and the base layer 120 has a top surface 121 and a side surface 122. According to current wafer plating techniques, the top surface 121 is equal in area to the base 3. The core reflow solder 130 is formed on the top surface 121 of the base layer 120, and the thickness or volume of the reflow solder 13G is approximately equal to the thickness (or volume) of the base layer 120. The reflow soldering #13〇 is reflowed. After the step is formed, a photoresist layer (which is not shown) for electroplating to form the base layer 12G must be formed. The side surface 122 of the edge base layer 12 () of the hemispherical reflow solder 13G must be removed. . If the return solder 13 is removed during reflow, the light layer 6 is removed and contaminated to the side 122 of the base layer 120, causing diffusion contamination. In addition, the material of the base layer 12G is a solder having a melting point higher than that of the reflow solder 13 ,, and even if the melting point of the base layer 12 未 is not reached during the flip chip bonding and reflow soldering, the solder reflow solder 13 is still dazzled. 'And easy to have deformation problems. Further, as shown in Fig. 2, a schematic cross-sectional view of a conventional wafer covered with a fine pitch bump structure is shown. A predetermined temperature and pressure is applied such that the wafer 20 is flip-chip bonded to the printed circuit board, and the micro-pitch bump structure is soldered to the corresponding bump pads 12 of the printed circuit board ig. Because the hemispherical reflow solder 13 is laterally expanded laterally to the side 122 of the base layer 120. Therefore, it is more likely to be extruded to the side surface 122 of the base layer 12 under the influence of the bonding pressure, causing diffusion contamination. What is more, the adjacent reflow solder 13 is in contact with each other to cause a short-circuit of the telecommunications, resulting in a decrease in the yield of flip-chip bonding. Based on the above problems, the conventional micro pitch bump structure is liable to cause a short circuit problem due to the bridging of the bump bonding material. Therefore, more changes and improvements are needed in today's micro-pitch bump technology to solve the above problems. SUMMARY OF THE INVENTION In order to solve the above-mentioned door eg r Λ v, the main purpose is to provide a kind of micro-pitch bump structure and a 曰β曰, and the process reaches a micro-pitch bump structure on the chip which can be a micro-pitch clock. . The distance between the sighs and the sighs is not short-circuited by the bridging of the bonding material, and the stress buffer after the mediation is reversed. In addition, the plating layer can be concentrated and efficient. Whoever +s pulls it into a half-pitch, to achieve a fine-pitch flip-chip bonding, low-temperature thermocompression bonding without reflow. σ... The present invention is intended to provide a micro-pitch bump structure that prevents diffusion of the bump bonding material during soldering. A further object of the present invention is to provide a micro pitch bump structure and process thereof to enhance the effectiveness of preventing diffusion contamination of the bump bonding material. A further object of the present invention is to provide a micro pitch bump structure and a process thereof to improve process yield and reduce manufacturing cost, and to solve the problem that the conventional bump bonding material needs to be reflowed and returned to the side of the base layer. . The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a micro-pitch bump structure for being disposed on a solder # of a wafer, wherein a surface of the wafer has a protective layer ′ which partially covers the periphery of the solder pad, and the micro pitch bump The structural package 3 has a base, an electroplated base layer, and an electroplated joint layer. The base is bonded to the bond pad and extends onto the protective layer. The electroplated base layer is formed on the base, and the electroplated base layer has a top surface and a side surface. The electric wire bonding layer is formed only on the top surface of the electroplated base layer, and the u side 'where the top surface area is smaller than the base ' is used to limit the electroplated bonding layer. The invention further discloses a process for a micro pitch bump structure. i?m25. The object of the present invention and solving the technical problems thereof can be further realized by the following techniques. In the aforementioned fine pitch bump structure, the side surface may be an inclined wall to make the plating base layer semi-tapered. In the aforementioned micro pitch bump structure, the plating base layer may have a slit to reduce the area of the top surface. In the aforementioned fine pitch bump structure, the slot can be penetrated to reveal the base. • In the aforementioned micro pitch bump structure, the top surface of the plating base layer may be formed as a bowl-shaped socket. In the aforementioned fine pitch bump structure, the plated bonding layer may be an all metal. In the foregoing micro pitch bump structure, the plating base layer may be a steel column. The material of the plating joint layer is selected from one of tin 'silver, tin and no solder. Φ In the aforementioned micro pitch bump structure, the thickness of the plating joint layer may be no more than one-half the thickness of the plating base layer. In the aforementioned micro pitch bump structure, the plated bonding layer may have continuous sides that are continuously connected to the side of the electrically forged base layer. In the foregoing micro pitch bump structure, the plated bonding layer may have a top surface which is smaller than the top surface of the plating base layer. In addition, the present invention further discloses a micro pitch bump structure for being disposed on a pad of a wafer, and a surface of the chip is formed with a protective layer that partially covers the periphery of the pad, the micro pitch bump The structural package 6 includes a base, an electroplated base layer, and a patterned electroplated joint layer. The bottom v-seat is bonded to the solder pad and extends to the protective layer. The electroplated base layer is formed on the base. The electroplated base layer has a top surface and a side surface. The patterned electroplated bonding layer is formed only. The top surface of the electroplated base layer is exposed, and the patterned electroplated joint layer is covered. The area is smaller than the top surface. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. • In the aforementioned micro pitch bump structure, the patterned plated bonding layer may have the shape of a single microbump. In the aforementioned fine pitch bump structure, the patterned plated bonding layer may have a pattern composed of a plurality of discrete microbumps. In the foregoing micro pitch bump structure, the thickness of the plating bonding layer may be no more than one-half the thickness of the plating base layer. It can be seen from the above technical solutions that the micro pitch bump structure and the process thereof of the present invention have the following advantages and effects: Lu Yi can limit the plating joint layer by changing the top surface of the plating base layer so that the area thereof is smaller than the base The method of combining and forming the electroplating of the electroplated bonding layer as one of the technical means, the electroplating bonding layer is concentratedly formed in a limited reduced area and naturally produces an integrated composite bump shape that does not require reflow, so Achieving a micro-pitch bump structure can be micro-pitched on the wafer without the short-circuit problem of bridging material bridging' and can enhance stress buffering after soldering. In addition, the electroplated bonding layer can be concentrated and efficiently soldered, so that the ratio of the thickness of the electrowinning bonding layer to the plating base layer (or VX convolution) can be reduced, for example, the thickness of the electroplated bonding layer is not greater than that of the electric shovel. Divided into one thickness to achieve micro-pitch flip-chip, and low-temperature thermocompression bonding with reflow. 2. By means of changing the top surface of the electroplated base layer such that its area is smaller than the base to limit the bond bonding layer and combining the electroplated base layer and the electro-mineral bonding layer are formed by means of electric bonds, The electroplated bonding layer is formed only on the top surface of the electroplated base layer to reveal the side of the electroplated base layer' to prevent diffusion contamination of the bump bonding material (ie, the electroplated bonding layer) during soldering. 3. The shape change of the bowl-shaped socket formed by the slit of the plating base layer or the top surface of the electroplated base layer can be used as one of the technical means to accommodate the electroplated joint layer which is extruded when the flip chip joint is extruded or reduced. The amount of extrusion is 'to enhance the effect of preventing diffusion pollution. Fourth, the side of the base layer of the electric ship can be continuously connected with the side of the electric ore joint layer as its towel-technical means, a photoresist layer can be shared in the money process, and ν+ is increased by the process yield. And reducing the manufacturing cost 'and can solve the problem that the conventional bump bonding material needs to be reflowed and returned to the side of the base layer. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, in which <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; Therefore, only the components and combinations related to this are displayed. The components shown in Figure t are not drawn in proportion to the number, shape, and size of the implementation. Some sizes are proportional to other related dimensions or are exaggerated or It is a simplified process to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, a micro pitch bump structure is illustrated in cross section in Fig. 3. The micro pitch bump structure 2 is disposed on a pad 21 of a wafer 20, and a surface 22 of the chip 2 is formed with a protective layer (passivati) 23, which is a partial package. Covering the periphery of the pad 21 provides protection to the surface 22. The surface 22 is an active surface of the wafer 20, and the surface 22 is provided with 70 integrated circuits (not shown), such as a microcontroller, a microprocessor, a memory, a logic circuit, and a special application integrated body. A circuit (such as a display drive circuit) or the like or a combination thereof. The pad 2 1 is an external end point for connecting the integrated circuit, and the material thereof is usually aluminum, copper or chromium. The material of the protective layer 23 is a surface layer composed of an electrically insulating material such as a nitrogen arsenide compound layer, an oxonium compound layer, a phosphorous silicate glass layer or a combination of the above materials. The protective layer • 23 has at least an opening to expose the fresh mash 21 . • As shown in FIG. 3, the micro pitch bump structure 200 includes a base -21G, an electroplated base layer 22G, and an electric clock bond layer 230. The base 210 is bonded to the pad 21 and extends to the protective layer 23. The base 210 provides a connection between the fresh pad 21 and the plated base layer 22A. The base 210 is generally composed of an adhesion layer, a diffusion barrier layer and an adhesive layer. The base 210 is a composite metal layer, which may be chromium/chromium/copper (Cr/CrCu/Cu), titanium/steel/nickel (Ti). /Cu/Ni), aluminum/nickel vanadium/copper (S3 9 (A1/NlV/Cu) and electroless nickel/gold (Ni/Au), etc. The base 210 can be formed by electron beam evaporation, magnetron control The base layer 220 is formed on the base 210, and the plating base layer 220 has a top surface 221 and a side surface 222. The side surface 222 can be an inclined wall. The electroplated base layer 220 is semi-tapered to reduce the area of the top surface 221. More specifically, the electroplated base layer 220 can be a copper post (c〇pper pi). The non-deformation property enables the electroplated base layer 220 to perform a good interval maintaining function 'not causing excessive collapse of the bump during the flip chip bonding, and the copper post can be formed at low cost by electro-mineralization. The term "column" as used in the present invention means that the height of an object is greater than the length of the object and greater than the width of the object, or It is larger than the diameter of the end face of the object. Therefore, the base layer 220 of the electric ore is preferably elongated, and can achieve a high-density configuration with a fine pitch. The electric ore bonding layer 230 is formed only on the top surface of the plating base layer 22 221, the side surface 222 is exposed, wherein the top surface 221 is smaller than the base 210 to limit the plating joint layer 23. Specifically, the electric ore bonding layer 230 may be all metal. In detail, The material of the electric ore bonding layer 230 may be selected from one of kick, silver, tin, and error-free solder. The melting point of the money bonding layer 230 should be lower than the melting point of the plating base layer 220. The key is formed. When the galvanic bonding layer 230 can be formed by electroplating, the reflow step can be omitted and a flat layer can be produced on the limited top surface 221 'will not be returned to the side of the logger base layer 220. 222 » [S3 10 Preferably, as further as 筮^ s 221 # ^rr S No, the top surface 22 of the I-plated base layer 220 is widely formed as a bowl-shaped socket, and is nearly flat at the center of the concave periphery. The bowl-shaped socket can reduce the number of the electrode bonding layer 230 that is extruded at the time of the complex BB bonding. Output::Picking out: L ^ ^ ^ The effect of the day to prevent the spread of pollution. Preferably, the plating base layer <side 222 can be an inclined wall so that the base layer 220 of the electric boat is __ The tapered shape may have a large bottom and a small convergence at the top to limit the formation area of the electric wire bonding layer 23. The plating bonding layer 230 is formed only on the plating base layer - the top surface 22 The side surface 222 ′ is exposed, wherein the top surface 221 is smaller than the base 210 to limit the plating joint layer 23 . Therefore, the plated bonding layer 230 can be concentrated and efficiently welded. When the thickness ratio of the plating bonding layer 230 to the plating base layer 22 is fixed to a predetermined value, the volume of the electric clock bonding layer 230 can be reduced. In the present embodiment, the thickness H1 of the wrought bonding layer 230 may be no more than one-half of the thickness H2 of the key infrastructure layer 220 (as indicated by the third circle). Therefore, the shape and position of the electric ore forming the bonding layer 230 can be achieved by using the low-temperature hot-welding method without reflow soldering, and there is no short-circuit problem of bridging of the bonding material, and the The advantage of stress buffering after welding. The plated bonding layer 230 can have a continuous side 23 1 that is continuously joined to the side 222 of the plated base layer 220. The technical means can share a photoresist layer (described later in detail) in the electroplating process to improve the process yield and reduce the manufacturing cost, and can solve the problem that the conventional bump bonding material needs to be reflowed and returned to the plating. Side 222 of base layer 220. In addition, m 11 f3S0^25 % of the electric ore bonding layer 230 may further have a top surface 232 which is smaller than the top surface 221 of the clock base layer 220 to make the fine pitch bumps appear convergent. 4A to 4H are schematic cross-sectional views showing the components of the micro pitch bump structure in the process according to the first embodiment of the present invention. The present invention further illustrates the process of the micro pitch bump structure to demonstrate the efficacy of the present invention. First, as shown in FIG. 4A, a wafer 2 is provided. One surface 22 of the wafer 2 has a plurality of pads 2. A surface 22 of the wafer 20 is formed with a protective layer 23' to partially cover the solder. The periphery of the pad 21. The wafer 20 can be formed on a wafer. Next, an under bump metal layer 3 is formed as shown in Fig. 4B, overlying the protective layer 23 and bonded to the pad 21. The bump metal 30 serves as a base of the bump and a plating seed layer, and has the properties of the bonding pad 21 attached to the wafer and the protective layer 23. Wherein, the under bump metal layer 3 can be formed by sputtering, and then a photoresist layer 40 is formed on the under bump metal layer 30 as shown in FIG. 4C. A photosensitive dielectric material can be formed on the under bump metal layer 30 by coating or attaching. Then, the photoresist layer 40 is exposed and exposed as shown in FIG. 4D such that the photoresist layer 40 is formed with a pair of openings 41 of the pads 21 to expose a portion 31 of the under bump metal layer 30, This portion 31 is a predetermined formation position of the above-described plating base layer 222. More specifically, the step of exposing and developing the pre-resist layer 40 includes isotropic development (Is〇tr〇py [S3 12 13804-25 ψ • D-g) so that the opening 41 has a slanted hole wall . For example, the
•曝光顯影方式係為讓光源通過—光罩50之M 而在光阻層40上顯影出所需的開孔41。該開孔4ι係可 利用負光阻之曝光不足方式使呈現收斂狀。 之後，如第4E圖所示，在該凸塊下金屬層3〇的導電 連通下，以電鍍方式形成一電鍍基礎層22〇於該凸塊下 金屬層30之顯露部位31並位於該開孔41内^該開孔 41係呈現底部大且頂部小的收斂狀，以使該側壁42係 • 為傾斜壁。故其内所形成之該電鍍基礎層220為半錐. $該電鍍基礎層220係具有一頂面221與一側面222， 其中該側面222係緊貼於該開孔41之侧壁42，該頂面 22 1係不超出於該光阻層40。在本實施例中，自該電鍍 基礎層220之該頂面221所形成之一碗狀承座係在此步 驟中形成。 之後，如第4F圖所示，在該凸塊下金屬層30與該電 鑛基礎層220的導電連通下，以電鍍方式形成一電鍍接 鲁 合層23 0於該電鍍基礎層220之該頂面221。並在該光 阻層40之該開孔41之限制下，該電鍍接合層230不會 覆蓋至該電鍍基礎層220之該側面222。因此，該電鍍 接合層230係以電鑛方式形成於電鐘基礎層220上，並 且不需經過回焊步驟，故能避免因回焊所造成之回包汙 染至該電鍍基礎層220的侧面222。其中該電鍍基礎層 22〇之頂面221係面積小於該凸塊下金屬層30之該部位 3 1，以用來限制該電鍍接合層230的面積。 m 13 在其後的-較佳步釋中，如第4G圖所示，在該電鑛 接合層230形成之後與在移除該光阻層4〇之前另包含 之步驟為：平坦化研磨該光阻層4〇肖該電錢接合声 230,以使該電鑛接合層23〇不突出於該光阻層4〇j 此，平坦化該電鍍接合層230之方式，亦可使得該電鍵 接合層230之該頂面232為平坦化，以不突出於該光阻 層4 0 〇The exposure development mode is such that the light source passes through the M of the mask 50 to develop the desired opening 41 on the photoresist layer 40. The opening 4ι can be rendered in a convergent manner by means of an underexposed manner of negative photoresist. Then, as shown in FIG. 4E, an electroplated base layer 22 is formed by electroplating on the exposed portion 31 of the sub-bump metal layer 30 and is located in the opening under the conductive connection of the metal layer 3〇 under the bump. 41. The opening 41 has a large bottom and a small convergence at the top so that the side wall 42 is an inclined wall. Therefore, the plating base layer 220 formed therein is a half cone. The plating base layer 220 has a top surface 221 and a side surface 222, wherein the side surface 222 is closely attached to the sidewall 42 of the opening 41. The top surface 22 1 does not extend beyond the photoresist layer 40. In the present embodiment, a bowl-shaped socket formed from the top surface 221 of the plating base layer 220 is formed in this step. Then, as shown in FIG. 4F, under the conductive connection between the under bump metal layer 30 and the electric ore base layer 220, a plating connection layer 230 is formed on the top of the plating base layer 220 by electroplating. Face 221. The plated bonding layer 230 does not cover the side 222 of the plating base layer 220 under the restriction of the opening 41 of the photoresist layer 40. Therefore, the plating bonding layer 230 is formed on the electric clock base layer 220 by electric ore, and does not need to go through the reflowing step, so that the back coating contamination caused by the reflow can be prevented from being contaminated to the side surface 222 of the electroplating base layer 220. . The top surface 221 of the plating base layer 22 is smaller than the portion 321 of the under-metal layer 30 to limit the area of the plating joint layer 230. m 13 In the subsequent - preferred step release, as shown in FIG. 4G, the step of additionally including after the formation of the electric ore bonding layer 230 and before removing the photoresist layer 4 is: planarizing and grinding The photoresist layer 4 embodies the electric wire bonding sound 230 so that the electric metal bonding layer 23 does not protrude from the photoresist layer 4, planarizing the plating bonding layer 230, and the bonding The top surface 232 of the layer 230 is planarized so as not to protrude from the photoresist layer 40 〇
最後，如第4H圖所示，移除該光阻層4〇，以顯露該 側面222。其中該電鍍接合層23〇係具有一連續側面 231，係連續地連接該電鍍基礎層22〇之該側面222。藉 此，連續地連接方式以形成不需要回焊的一體化複合式 凸塊形狀。且該電鐘接合層230係更具有一頂面232， 係小於該電鍍基礎層220之該頂面221。最後，以钱刻 方式移除該&塊下金屬層3 0。此外，在該電錄接合層2 3 〇 與該電鍍基礎層220之遮蔽下，該凸塊下金屬層3〇被該 電鍍基礎層220覆蓋的部位將被保留，而形成為上述之 底座210(如第3圖所示）。 依據本發明之第二具體實施例，一種微間距凸塊結構 舉例說明於第5圖之截面示意圖。該微間距凸塊結構 300，用以設置於一晶片20之一銲墊21上，該晶片20 之一表;面22形成有一保護層23，係局部包覆該銲墊21 之周邊。該微間距凸塊結構300係包含一底座2 1 0、一 電鍵基礎層220以及一電鍍接合層230。其中與第一實 施例相同的主要元件將以相同符號標示，其中具有相同 { S1 14 ' 或類似的作用與功效的部分在此不再予以贅述。較佳 . 地，該電鍵基礎層220係可具有一狹槽323，用以縮小 該頂面221之面積，藉以限制該電鍍接合層23〇之形成 面積，並且能在覆晶接合時收容多餘被擠出之該電鍍接 合層230 ^在本實施例中，該狹槽323係可貫穿至顯露 出該底座210，以使得該底座21〇上同時具有分離的兩 或多個微凸塊。 依據本發明之第二具體實施例，另一種微間距凸塊結 • 構舉例說明於第6圖之截面示意圖。該微間距凸塊結構 400，用以設置於一晶片20之一銲墊21上，該晶片2〇 之一表面22形成有一保護層23，係局部包覆該銲墊21 之周邊。該微間距凸塊結構4〇〇係包含一底座4丨〇、一 電鍍基礎層420、一圖案化電鍍接合層43〇。該底座41〇 係接合於該銲墊21並延伸到該保護層23上。其中該底 座410之作用與功效與第一實施例相同，故不再贅述。 該電鍍基礎層420係形成於該底座41〇上該電鍍基 籲礎層420係具有-頂面421與一側面422。其中，該電 鍍基礎層420係可為一非柱狀的凸塊形狀，即其高度不 大於凸塊之寬度、長度或直徑。 該圖案化電鍍接合層43〇係僅形成於該電鍍基礎層 420之該頂面421，而顯露該側面422，並且該圖案化電 鐘接合層430之覆蓋面積係小於該頂面421。該圖案化 電鍍接合層430為不需要回焊並與該電鍍基礎層42〇結 合為複合式凸塊。該電鍍基礎層42〇之該頂面421未覆Finally, as shown in Fig. 4H, the photoresist layer 4 is removed to reveal the side surface 222. The electroplated bonding layer 23 has a continuous side 231 which is continuously connected to the side 222 of the electroplated base layer 22 . As a result, the connection is continuously formed to form an integrated composite bump shape that does not require reflow. The electric clock bonding layer 230 further has a top surface 232 which is smaller than the top surface 221 of the plating base layer 220. Finally, the & under-metal layer 30 is removed in a money-cut manner. In addition, under the shielding of the galvanic bonding layer 2 3 〇 and the plating base layer 220, the portion of the under bump metal layer 3 覆盖 covered by the plating base layer 220 will be retained, and formed into the above-mentioned base 210 ( As shown in Figure 3). According to a second embodiment of the present invention, a micro pitch bump structure is illustrated in cross section in Fig. 5. The micro pitch bump structure 300 is disposed on a pad 21 of a wafer 20, and one surface of the wafer 20; the surface 22 is formed with a protective layer 23 for partially covering the periphery of the pad 21. The micro pitch bump structure 300 includes a base 210, a key base layer 220, and a plated bonding layer 230. The same main elements as those in the first embodiment will be denoted by the same reference numerals, and portions having the same {S1 14 ' or similar functions and effects will not be described herein. Preferably, the key base layer 220 can have a slot 323 for reducing the area of the top surface 221, thereby limiting the formation area of the plating bonding layer 23, and accommodating excess during the flip chip bonding. Extrusion of the plated bonding layer 230. In this embodiment, the slot 323 can extend through to expose the base 210 such that the base 21 has two or more discrete microbumps thereon. In accordance with a second embodiment of the present invention, another micro pitch bump structure is illustrated in cross section in Fig. 6. The micro pitch bump structure 400 is disposed on a pad 21 of a wafer 20, and a surface 22 of the chip 2 is formed with a protective layer 23 for partially covering the periphery of the pad 21. The micro pitch bump structure 4 includes a base 4, an electroplated base layer 420, and a patterned electroplated bonding layer 43. The base 41 is spliced to the pad 21 and extends to the protective layer 23. The function and function of the base 410 are the same as those of the first embodiment, and therefore will not be described again. The plating base layer 420 is formed on the base 41. The plating base layer 420 has a top surface 421 and a side surface 422. The electroplated base layer 420 may be in the shape of a non-columnar bump, that is, the height is not greater than the width, length or diameter of the bump. The patterned plated bonding layer 43 is formed only on the top surface 421 of the plating base layer 420, and the side surface 422 is exposed, and the patterned motor bonding layer 430 has a smaller coverage area than the top surface 421. The patterned plated bonding layer 430 is a composite bump that does not require reflow and is bonded to the plated base layer 42. The top surface 421 of the plating base layer 42 is uncovered
f SJ 15 蓋面積可供該圖案化電鍍接合層43〇的擠壓擴散，故能 達成微間距凸塊結構在晶片上可為微間距設置並且不會 有接合材料橋接之短路問題。 該圖案化電鍍接合層43〇係可具有單一個微凸塊對 應於一個電鍍基礎層42〇之形狀。該圖案化電鍍接合層 430之厚度係可不大於該電鍍基礎層42〇之二分之一厚 度，較佳應用為可達成微間距覆晶接合是使用免用回焊 的低溫熱壓合焊接。The cover area of the f SJ 15 allows for the extrusion diffusion of the patterned plated bonding layer 43. Therefore, it is possible to achieve a micro-pitch structure in which the micro-pitch bump structure can be arranged at a fine pitch without bridging of the bonding material. The patterned plated bonding layer 43 can have a single microbump corresponding to the shape of an electroplated base layer 42. The thickness of the patterned electroplated bonding layer 430 may be no more than one-half the thickness of the electroplated base layer 42. It is preferably applied to achieve a fine pitch flip-chip bonding using a low temperature thermocompression bonding without reflow.
依據本發明之第四具體實施例，另一種微間距凸塊結 構舉例說明於第7圖之截面示意圖。該微間距凸塊結構 500中，其與第三實施例皆具有相同的主要元件將以相 同符號標示’並由於具有相同或類似的作用與功效，故 在此不再予以贅述。 在本實施例中，該圖案化電鍍接合層43〇係可具有 複數個分離微凸塊所組成之圖案，同樣地能達到不需In accordance with a fourth embodiment of the present invention, another micro pitch bump structure is illustrated in cross-section of Fig. 7. In the micro-pitch bump structure 500, the same main elements as those of the third embodiment will be denoted by the same reference numerals and have the same or similar functions and effects, and therefore will not be further described herein. In this embodiment, the patterned electroplated bonding layer 43 can have a pattern of a plurality of discrete microbumps, and can be achieved without
回焊的-體化複合式凸塊形狀，並且不會有接合材们 接之短路問題，並能增進在焊接後之應力緩衝。 以上所述，僅是本發明的較佳實施例而已，並非對^ 發明作任何形式上的限制1然本發明已以較佳實心 揭露如上，然而並非用以限定本發明，任何熟 術者’在不脫離本發明之技#範圍Μ，所作的任何簡^ :改、等效性變化與修飾’均仍屬於本發明的技術範§ 内〇 【圖式簡單說明】 16 [S3 1380425 第1圖：為習知微間距凸塊結構之截面示意圖。 第2圖：為習知晶片以微間距凸塊結構覆晶結合至一印 刷電路板之截面示意圖。 第3圖：為依據本發明之第一具體實施例的一種微間距 凸魄結構之截面示意圖。 第4A至4H圖：為依據本發明之第一具體實施例的微間 距凸塊結構在製程中元件之截面示意圖。 第5圖：為依據本發明之第二具體實施例的另一種微間 距凸塊結構之截面示'意圖。 第6圖：為依據本發明之第三具體實施例的另一種微間 距凸塊結構之截面示意圖。 第7圖：為依據本發明之第四具體實施例的另一種微間 距凸塊結構之截面示意圖。 【主要元件符號說明】 H1 厚度 H2 厚度 10 印刷電路板 12 凸塊接墊 20 晶片 21 銲墊 22 表1 23 保護層. 30 凸塊下金屬層 31 部位 40 光阻層 41 開孔 42 側壁 50 光罩 51 孔洞 100 微間距凸塊結構 110 底座 120 基礎層 121 頂面 122 側面 17 1380425 130 回 焊 銲料 200 微 間 距凸 塊結構 210 底 座 220 電 鍍 基礎層 221 頂 面 222 側 面 230 電 鍍接合層 23 1 連 續 側面 300 微 間 距凸 塊結構 323 狹 槽 400 微 間 距凸 塊結構 410 底 座 420 電 鍍 基礎層 421 頂 面 422 侧 面 430 圖 案 化電 鍍接合層 500 微 間 距凸 塊結構 232頂面 18The reflow-composite composite bump shape does not have short-circuit problems with the joints and enhances the stress buffer after soldering. The above is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way. However, the present invention has been described above with better solidity, but is not intended to limit the invention, and any skilled person' Without departing from the scope of the invention, any modifications, equivalent changes and modifications are still within the technical scope of the invention. [Simplified illustration] 16 [S3 1380425 1 : is a schematic cross-sectional view of a conventional micro-pitch bump structure. Fig. 2 is a schematic cross-sectional view showing a wafer in which a conventional wafer is flip-chip bonded to a printed circuit board with a fine pitch bump structure. Figure 3 is a schematic cross-sectional view showing a micro-pitched tenon structure in accordance with a first embodiment of the present invention. 4A to 4H are cross-sectional views showing the components of the micro-pitch bump structure in the process according to the first embodiment of the present invention. Fig. 5 is a cross-sectional view showing another micro-pitch structure in accordance with a second embodiment of the present invention. Figure 6 is a cross-sectional view showing another micro-pitch bump structure in accordance with a third embodiment of the present invention. Figure 7 is a cross-sectional view showing another micro-pitch bump structure in accordance with a fourth embodiment of the present invention. [Main component symbol description] H1 Thickness H2 Thickness 10 Printed circuit board 12 Bump pad 20 Wafer 21 Pad 22 Table 1 23 Protective layer. 30 Bump under metal layer 31 Part 40 Photoresist layer 41 Opening 42 Side wall 50 Light Cover 51 Hole 100 Micro pitch bump structure 110 Base 120 Base layer 121 Top surface 122 Side 17 1380425 130 Reflow solder 200 Micro pitch bump structure 210 Base 220 Plating base layer 221 Top surface 222 Side 230 Plating joint 23 1 Continuous side 300 micro pitch bump structure 323 slot 400 micro pitch bump structure 410 base 420 plating base layer 421 top surface 422 side 430 patterned plating joint layer 500 micro pitch bump structure 232 top surface 18