201034141 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種微間 距凸塊結構及其製程。 【先前技術】 先進的晶圓級封裝與覆晶接合技術的發展日益成 熟’目前研發的主要重點之一為微間距凸塊的設置，以 因應積髗電路封裝技術之微型化與高密度化的開發。而 ❹ 所謂凸塊的微間距係指相鄰凸塊的中心點到中心點的距 離控制在1 50微米（私m)以内。對於可攜式及高性能微電 子產品而言’縮短凸塊的微間距距離將有助於產品短、 小、輕、薄的需求’是以微間距凸塊的應用已漸成為高 密度積體電路封裝的主流。由於微間距凸塊之間的距離 過近，常會因凸塊接合材料之橋接而產生短路問題，尤 其當晶片覆晶結合至基板時，因微間距凸塊之接合材料 可能彼此電性連接，而造成非預期的短路現象。 β 如第1圖所示者為習知微間距凸塊結構100，用以設 置於一晶片20之一銲墊21上，該晶片2〇之一表面22 形成有一保護層23,係局部包覆該銲墊21之周邊。該 微間距凸塊結構100係包含一底座11〇、一基礎層12〇 以及一回焊銲料130。該底座110係接合於該銲墊21並 延伸到該保護層23上。該基礎層12〇係形成於該底座 110，該基礎層120係具有一頂面121與一側面122。依 照目前的晶圓電鍍技術，該頂面121係面積等於該底座 201034141 110該回焊銲料130形成於該基礎層12〇之該頂面12卜 其回焊銲料130的厚度或體積約為相等於基礎層12〇的 厚度（或體積）’該回焊銲料13〇在回焊步驟之後會形成 為半球狀。由於用以電鍍形成該基礎層12〇的光阻層（圖 未繪出）必須不可移除，該半球狀的回焊銲料的邊緣 會突出於該基礎層12〇之該側面122。若該回焊銲料13〇 在回焊時光阻層已移除則會回包汗染至該基礎層12〇的 側面122，造成擴散汗染。此外，該基礎層12〇的材料 • 為熔點高於該回焊銲料130的銲料，即使覆晶接合與回 焊時未達到該基礎層12〇的熔點，仍會與該回焊銲料 • 互溶’並易有變形之問題。 此外，如第2圖所示者為習知晶片以微間距凸塊結構 覆晶結合至一基板之截面示意圓。施加一預定之溫度與 壓力使得該晶片20覆晶結合至該印刷電路板1 〇上，藉 由該微間距凸塊結構100谭接至該印刷電路板10之對應 凸塊接墊12 °因為該半球狀㈣料料13G已横向地外 擴於該基礎層12G之該側面122β所以在受到結合壓力 之影響下更容易被擠出至該基礎層12〇之該侧面US， 造成擴散汗染。更甚者，會造成相鄰的回焊鲜料13〇相 接觸而造成電信短路（Sh〇rt)，導致覆晶接合的良率降低。 基於上述的問題點’習知的微間距凸塊結構易因凸塊 =:橋接而造成短路問題。因此，在現今微間： 凸塊技術中需更多改變與改善以解決上述問題。 【發明内容】 201034141 為了解決上述之問題，本發明之主要目的係在於提供 一種微間距凸塊妹堪B #杂， 现鲒構及其製程，達成微間距凸塊結構在 晶片上可為微間距設置並且不會有接合材料橋接之短路 ]題並能增進在焊接後之應力緩衝。此外，電鍛接合 層此被集巾有效率進行焊接，以達成微間距覆晶接合為 免用回焊的低溫熱壓合焊接。 本發明之次一目的係在於提供一種微間距凸塊結構 及其製程，能避免凸塊接合材料在焊接時的擴散汙染。 ® 本發明之再一目的係在於提供一種微間距凸塊結構 及其製程’以增進防止凸塊接合材料擴散汙染之功效。 • 本發明之再一目的係在於提供一種微間距凸塊結構 及其製程，以提高製程良率與降低製造成本，並能解決 習知凸塊接合材料需要回焊而回包汙染至基礎層的側 面。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種微間距凸塊結構’用以設 置於一晶片之一銲墊上’該晶片之一表面形成有一保護 層’係局部包覆該銲墊之周邊，該微間距凸塊結構係包 含一底座、一電鍍基礎層以及一電鍍接合層。該底座係 接合於該銲墊並延伸到該保護層上。該電鍍基礎層係形 成於該底座’該電鍍基礎層係具有一頂面與一側面。該 電鍍接合層係僅形成於該電鍍基礎層之該頂面，而顯露 該側面，其中該頂面係面積小於該底座，用以限制該電 鍵接合層》本發明另揭示一種微間距凸塊結構之製程。 5 201034141 參201034141 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a micro-pitch bump structure and a process therefor. [Prior Art] The development of advanced wafer-level packaging and flip-chip bonding technology is becoming more and more mature. One of the main focuses of current research and development is the setting of micro-pitch bumps, in order to miniaturize and increase the density of circuit packaging technology. Development. And 微 The so-called micro-pitch of the bumps means that the distance from the center point to the center point of the adjacent bumps is controlled within 150 μm (private m). For portable and high-performance microelectronics, 'shortening the micro-pitch distance of the bumps will help the product to be short, small, light and thin.' The application of micro-pitch bumps has become a high-density integrated body. The mainstream of circuit packaging. Since the distance between the micro-pitch bumps is too close, the short-circuit problem often occurs due to the bridging of the bump bonding materials, especially when the wafer flip-chip is bonded to the substrate, the bonding materials of the micro-pitch bumps may be electrically connected to each other, and Causes an unexpected short circuit. As shown in FIG. 1 , the conventional micro-pitch bump structure 100 is disposed on a pad 21 of a wafer 20 , and a surface 22 of the wafer 2 is formed with a protective layer 23 and is partially covered. The periphery of the pad 21. The micro pitch bump structure 100 includes a base 11 , a base layer 12 , and a reflow solder 130 . The base 110 is bonded to the pad 21 and extends to the protective layer 23. The base layer 12 is formed on the base 110, and the base layer 120 has a top surface 121 and a side surface 122. According to the current wafer plating technology, the top surface 121 is equal to the base 201034141 110. The reflow solder 130 is formed on the top surface 12 of the base layer 12, and the thickness or volume of the reflow solder 130 is approximately equal to The thickness (or volume) of the base layer 12A' is such that the reflow solder 13 is formed into a hemispherical shape after the reflow step. Since the photoresist layer (not shown) for electroplating to form the base layer 12 must be non-removable, the edge of the hemispherical reflow solder will protrude from the side 122 of the base layer 12 . If the solder reflow solder 13 is removed during reflow, the photoresist layer is swept back to the side 122 of the base layer 12, causing diffuse sweating. In addition, the material of the base layer 12 is a solder having a melting point higher than that of the reflow solder 130, and even if the melting point of the base layer 12〇 is not reached during the flip chip bonding and reflow, the reflow solder is still miscible with the reflow solder. And easy to have problems with deformation. Further, as shown in Fig. 2, a conventional wafer is flip-chip bonded to a substrate with a fine pitch bump structure. Applying a predetermined temperature and pressure to bond the wafer 20 to the printed circuit board 1 ,, the micro pitch bump structure 100 is connected to the corresponding bump pad 12 of the printed circuit board 10 because The hemispherical (four) material 13G has been laterally expanded outwardly on the side surface 122 of the base layer 12G so that it is more easily extruded to the side US of the base layer 12 by the influence of the bonding pressure, causing diffuse sweating. What's more, the adjacent reflow soldering material will contact 13〇 and cause a short circuit (Sh〇rt), which will reduce the yield of flip chip bonding. Based on the above problem, the conventional micro-pitch bump structure is susceptible to a short circuit problem due to bump = bridge. Therefore, in today's micro-room: more changes and improvements are needed in the bump technology to solve the above problems. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a micro-pitch bump, which can be used for micro-pitching on a wafer. Set and there will be no short circuit of the joint material bridge] and improve the stress buffer after welding. In addition, the electric forging bonding layer is efficiently welded by the collecting towel to achieve the micro-spaced flip-chip bonding as a low-temperature thermocompression bonding which is free from reflow. A second object of the present invention is to provide a micro pitch bump structure and a process thereof, which can avoid diffusion contamination of the bump bonding material during soldering. A further object of the present invention is to provide a micro pitch bump structure and process thereof to enhance the effectiveness of preventing diffusion contamination of the bump bonding material. A further object of the present invention is to provide a micro pitch bump structure and a process thereof for improving process yield and manufacturing cost, and solving the problem that the conventional bump bonding material needs to be reflowed and returned to the base layer. side. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a micro pitch bump structure for mounting on a pad of a wafer. A surface of a surface of the wafer is formed with a protective layer that partially covers the periphery of the pad. The micro pitch bump structure includes a pad. A base, an electroplated base layer, and an electroplated joint layer. The base is bonded to the bond pad and extends onto the protective layer. The electroplated base layer is formed on the base. The electroplated base layer has a top surface and a side surface. The electroplated bonding layer is formed only on the top surface of the electroplating base layer, and the side surface is exposed, wherein the top surface area is smaller than the base to limit the electric bonding layer. The present invention further discloses a micro pitch bump structure. Process. 5 201034141 Reference
本發明的目的及解決其技術 措施進一步實現。 在前述的微間距凸塊結構中 使該電鍍基礎層為半錐形。 在前述的微間距凸塊結構中， 一狹槽，用以縮小該頂面之面積 在前述的微間距凸塊結構中， 出該底座。 在前述的微間距凸塊結構中 係可形成為一碗狀承座。 在前述的微間距凸塊結構中 金屬。 問題還可採用以 下技術 該侧面係可為傾斜壁以 該電錢基礎層係可具有 〇 該狹槽係T貫穿至顯露 ，該電鍍基礎層之該頂面 ’該電鍍接合層係可為全 在前述的微間距凸塊結構中，該電鍍基礎層係可為一 銅柱，該電鍍接合層之材質係選自於錫、銀、锡船與無 鉛銲料之其中之一。 在前述的微間距凸塊結構中’該電鍍接合層之厚度係 可不大於該電鍍基礎層之二分之一厚度。 在前述的微間距凸塊結構中，該電鍍接合層係可具有 一連續側面’係連續地連接該電艘基礎層之該側面。 在前述的微間距凸塊結構中，該電鍍接合層係可更具 有—頂面，係小於該電艘基礎層之該頂面。 此外，本發明另揭示一種微間距凸塊結構，用以設置 於一晶片之一銲塾上，該晶片之一表面形成有一保護 層，係局部包覆該銲整之周邊’該微間距凸塊結構係包 201034141 含一底座、一電鍍基礎層、一圖案化電鍍接合層。該底 座係接合於該銲墊並延伸到該保護層上，該電鍵基礎層 係形成於該底座，該電鍵基礎層係具有一頂面與一側 面’該圖案化電鍍接合層係僅形成於該電鍍基礎層之該 頂面，而顯露該側面，並且該圖案化電鍍接合層之覆蓋 面積係小於該頂面。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。The object of the present invention and the technical measures for solving the same are further realized. The electroplated base layer is semi-tapered in the aforementioned fine pitch bump structure. In the aforementioned fine pitch bump structure, a slot is formed for reducing the area of the top surface. In the aforementioned fine pitch bump structure, the base is removed. In the aforementioned fine pitch bump structure, it can be formed as a bowl-shaped socket. In the aforementioned micro pitch bump structure, metal. The problem may also be that the side surface may be a sloping wall, and the electric money base layer may have the slot system T penetrating to reveal, the top surface of the electroplated base layer 'the galvanic joint layer may be all In the above micro pitch bump structure, the plating base layer may be a copper pillar, and the material of the plating joint layer is selected from one of tin, silver, tin boat and lead-free solder. In the foregoing fine pitch bump structure, the thickness of the plated bonding layer may be no more than one-half the thickness of the plated base layer. In the foregoing micro pitch bump structure, the plated bonding layer may have a continuous side' that continuously connects the side of the base layer of the electric boat. In the aforementioned micro pitch bump structure, the plated bonding layer may have a top surface which is smaller than the top surface of the base layer of the electric boat. In addition, the present invention further discloses a micro pitch bump structure for being disposed on a solder fillet of a wafer, and a surface of one surface of the wafer is formed to partially cover the periphery of the soldered portion. The structural package 201034141 includes a base, an electroplated base layer, and a patterned electroplated joint layer. The base is bonded to the soldering pad and extends to the protective layer. The keying base layer is formed on the base. The keying base layer has a top surface and a side surface. The patterned plating bonding layer is formed only on the base layer. The top surface of the base layer is electroplated to reveal the side surface, and the patterned electroplated bonding layer has a coverage area that is smaller than the top surface. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures.
在前述的微間距凸塊結構中，該圖案化電鍍接合層係 可具有單一個微凸塊之形狀。 在前述的微間距Λ塊結構中，該圖案化電鍍接合層係 可具有由複數個分離微凸塊所組成之圖案。 在前述的微間距凸塊結構中，該電鍍接合層之厚度係 可不大於該電鍍基礎層之二分之一厚度。 由以上技術方案可以看出，太菰Μ —如 ®本發明之微間距凸塊結構 及其製程’具有以下優點與功效： 一、可藉由改變電鍍基礎層 層之頂面以致使其面積小於底 座以限制電鍍接合層的古 增的方式並加以組合電鍍接合層 的電鍍形成方式作為其中一 Ύ 技術手段，使電鍍接合 層集中形成於受限的始，π Α 又u的縮小面積内並且自$產生不需 要回焊的一體化複合式凡祕水也 而 π ^ ^ 式凸塊形狀，故能達成微間距 凸塊結構在晶片上 了為微間距設置並且不會有接合 ^ 斗橋接之短路問題，並能增進在焊接後之應力緩 外，電鍵接合層能被集中有效率進行焊接， 7 201034141 故電鍍接合層與電鍍基礎層的厚度（或體積）比值能 降低’例如達到電鍍接合層厚度不大於電鍍基礎層 之二分之—厚度’以達成微間距覆晶接合為免用回 焊的低溫熱壓合焊接。 二、可藉由改變電鍍基礎層之頂面以致使其面積小於底 座以限制電鍍接合層的方式並加以組合電鍍基礎層 與電鑛接合層皆為電鍍形成之方式作為其中一技術 手段’使得電鍍接合層僅形成於電鍍基礎層之頂面 φ 而顯露電鍍基礎層之側面，能避免凸塊接合材料（即 電鍍接合層）在焊接時的擴散汙染。 二、可藉由電鍍基礎層具有之狹槽或是電鍍基礎層之頂 面形成之碗狀承座等形狀改變作為其中一技術手 段’可以收容覆晶接合時被擠出之電鍍接合層或減 被擠出量’以增進防止擴散汗染之功效。 四、可藉由電鍍基礎層的側面與電鍍接合層的側面為連 續地連接方式作為其中一技術手段，在電鍍製程中 • 可共用一光阻層，以提高製程良率與降低製造成 本，並能解決習知凸塊接合材料需要回焊而回包汙 染至基礎層的側面。 【實施方式】 ， 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是’該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元伴與組合關係，圖令所顯示之元件並非以實際 201034141 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種微間距凸塊結構 舉例說明於第3圖之截面示意圖。該微間距凸塊結構2〇〇 係用以設置於一晶片20之一銲墊21上，該晶片2〇之一 表面22形成有一保護層（passivati〇n Layer)23 ,係局部 鲁 包覆該銲墊21之周邊，可提供保護該表面22上。該表 面22係為該晶片20之主動面，該表面22係設有積體電 路元件（圖中未繪出），如微控制器、微處理器、記憶體、 邏輯電路、特殊應用積體電路（如顯示器驅動電路）等戋 上述之組合》該銲墊21係為連接積體電路之對外端點， 其材質通常為鋁、銅或鉻。該保護層23之材質係為電絕 緣材料所構成的表面層，例如一氮矽化合物層、一氧矽 化合物層、一磷矽玻璃層或上述材質之組合。該保護層 _ 23具有至少一開口以暴露該銲墊21。 如第3圖所示，該微間距凸塊結構2〇〇係包含一底座 210、一電鍍基礎層22〇以及一電鍍接合層2 礴底座 210係接合於該銲墊21並延伸到該保護層23上❶誃In the aforementioned fine pitch bump structure, the patterned plated bonding layer may have a shape of a single microbump. In the aforementioned micro-pitch block structure, the patterned plated bonding layer may have a pattern composed of a plurality of discrete micro-bumps. In the foregoing micro pitch bump structure, the thickness of the plating bonding layer may be no more than one-half the thickness of the plating base layer. It can be seen from the above technical solutions that the structure of the micro-pitch bump structure of the present invention and the process thereof have the following advantages and effects: 1. The area of the top layer of the electroplated base layer can be changed so that the area thereof is smaller than The base is used as one of the technical means for limiting the ancient increase of the plating bonding layer and the plating forming method of the combined plating bonding layer, so that the plating bonding layer is concentratedly formed in the limited initial, π Α u and the reduced area and $Integrated composite water that does not require reflow is also π ^ ^ type bump shape, so that the micro-pitch bump structure can be achieved on the wafer for micro-pitch setting and there is no short circuit of the bonding bridge Problem, and can improve the stress after soldering, the bond bonding layer can be concentrated and efficiently welded, 7 201034141 Therefore, the ratio of thickness (or volume) of the plating joint layer to the plating base layer can be reduced 'for example, to achieve the thickness of the plating joint layer Not less than the two-thickness of the base layer of the plating - to achieve the micro-spaced flip-chip bonding as a low-temperature thermocompression welding that is free of reflow. Second, by changing the top surface of the plating base layer so that its area is smaller than the base to limit the plating joint layer and combining the plating base layer and the electric ore joint layer are all formed by electroplating as one of the technical means to make electroplating The bonding layer is formed only on the top surface φ of the plating base layer to expose the side surface of the plating base layer, and the diffusion contamination of the bump bonding material (ie, the plating bonding layer) during soldering can be avoided. 2. The shape change of the bowl-shaped socket formed by the slot of the electroplated base layer or the top surface of the electroplated base layer can be used as one of the technical means to accommodate the electroplated joint layer or the extruded layer which is extruded during the flip chip bonding. The amount of extrusion is 'to enhance the effect of preventing diffusion and sweating. Fourth, the side of the plating base layer and the side of the plating joint layer are continuously connected as one of the technical means, in the electroplating process, a photoresist layer can be shared to improve the process yield and reduce the manufacturing cost, and It can solve the problem that the conventional bump bonding material needs to be reflowed and returned to the side of the base layer. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which, Therefore, only the meta-companion and combination relationship related to the case are displayed. The components shown in the plan are not drawn in proportion to the number, shape and size of the actual implementation of 201034141. Some size ratios are exaggerated or different from other related sizes. Simplify the process to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, a micro pitch bump structure is illustrated in cross section in Fig. 3. The micro-pitch bump structure 2 is disposed on a pad 21 of a wafer 20, and a surface 22 of the wafer 2 is formed with a protective layer 23, which is partially covered. The periphery of the pad 21 is provided to protect the surface 22. The surface 22 is an active surface of the wafer 20, and the surface 22 is provided with integrated circuit components (not shown), such as a microcontroller, a microprocessor, a memory, a logic circuit, and a special application integrated circuit. (such as a display driver circuit), etc. The combination of the above-mentioned solder pads 21 is an external terminal to which the integrated circuit is connected, and the material thereof is usually aluminum, copper or chromium. The material of the protective layer 23 is a surface layer composed of an electrically insulating material such as a nitrogen arsenide compound layer, an oxonium compound layer, a phosphorous silicate glass layer or a combination of the above materials. The protective layer _ 23 has at least one opening to expose the pad 21. As shown in FIG. 3, the micro pitch bump structure 2 includes a base 210, an electroplated base layer 22, and an electroplated bonding layer. The base 210 is bonded to the bonding pad 21 and extends to the protective layer. 23 Shangyu
座210係可提供該銲墊21與該電鍍基礎層2 L u〜「al的連 結。該底座210通常由附著層、擴散阻障層及接著層 構成，該底座210為一複合金屬層，可為鉻/鉻鋼 (Cr/CrCu/Cu)、鈦 / 銅 / 鎳（Ti/Cu/Ni)、 ’殊訊/銅 201034141 (Al/NiV/Cu)及無電鍍鎳/金（Ni/Au)等。該底座2i〇的形 成係可利用電子束蒸鍍、磁控濺鍍或無電鍍等方法形成。 該電鍍基礎層220係形成於該底座21〇，而該電鍍基 礎層220係具有一頂面221與一側面222。其中，該侧 面222係可為傾斜壁以使該電鍍基礎層22〇為半錐形， 藉以縮小該頂面221之面積。更具體地，該電鍍基礎層 220係可為一銅柱（c〇pper pilUr)。銅柱具有耐高溫與不 變形的特性，能使該電鍍基礎層22〇發揮良好的間隔維 ❿ 持作用，不會在覆晶接合之過程造成凸塊的過度潰陷， 並且銅柱可由電鍍方式低成本的形成。此外，本發明所 稱之「柱」係指一物件的高度大於該物件之長度也大於 該物件之寬度，或者是大於該物件之端面直徑。故該電 鍍基礎層220以細長狀為較佳，可達到微間距的高密度 配置。 該電鍍接合層230係僅形成於該電锻基礎層22〇之該 頂面221，而顯露該侧面222,其中該頂面221係面積小 ❼ 於該底座210,用以限制該電鍍接合層23〇。具體而言， 該電鍍接合層230係可為全金屬。詳細而言，該電鍍接 合層230之材質係可選自於錫、銀、錫鉛與無鉛銲料之 其中之。該電锻接合層230的炼點應低於該電锻基礎 層220的炼點，並可電鍍形成。當該電鍍接合層23 0可 由電鍍形成，便可省略回焊步驟並能在有限的頂面22工 上產生平坦的層狀物，不會回包到該電鍍基礎層220之 該側面222。 201034141 較佳地’再如第3圖所示，該電鍍基礎層220之該頂 面221係可形成為一碗狀承座，在中央為下凹，周邊則 接近平坦。該碗狀承座可減少在覆晶接合時被擠出之電 鍍接合層230的被擠出量，以增進防止擴散汙染之功 效°較佳地’該電鍍基礎層22〇之側面222係可為傾斜 壁以使該電鍍基礎層220為半錐形，可呈現底部大且頂 部小之收斂狀’以用來限制.該電鍍接合層23〇之形成面 積。該電鑛接合層23 0係僅形成於該電鍍基礎層22〇之 ❹ 該頂面221 ’而顯露該側面222，其中該頂面221係面積 小於該底座210’用以限制該電鍍接合層230»因此，該 電鍍接合層230能被集中有效率地進行焊接。當該電锻 接合層230與該電鍍基礎層220的厚度比值固定於一預 定值時’該電鍍接合層230的體積能減少。在本實施例 中’該電鑛接合層23 0之厚度hi係可不大於該電鍍基 礎層220之二分之一厚度H2(如第3圖所示）。因此，利 用該電鑛接合層230的電鍍形成形狀、位置，微間距覆 鲁 晶接合可採用免用回焊的低溫熱壓焊接方法達成，同時 不會有接合材料橋接之短路問題，並能增進在焊接後之 應力緩衝之優點。 該電鍍接合層230係可具有一連續側面23 i，係連續 地連接該電鍍基礎層220之該侧面222。此一技術手段 可在電鍍製程中共用一光阻層（容後詳述），以提高製程 良率與降低製成本’並能解決習知凸塊接合材料需要 回焊而回包汙染至該電鍍基礎層220的侧面222。另外， 11 201034141 該電鍍接合層230係可更具有一頂面232，係小於該電 鍍基礎層220之該頂面221，以使微間距凸塊呈現為收 斂狀。 請參閱第4A至4H圖為依據本發明之第一具體實施 例的微間距凸塊結構在製程中元件之截面示意圖。本發 明進一步說明該微間距凸塊結構之製程，以彰顯本案的 功效。The base 210 is provided with a connection between the bonding pad 21 and the plating base layer 2 L u~ "al. The base 210 is generally composed of an adhesion layer, a diffusion barrier layer and an adhesive layer. The base 210 is a composite metal layer. Chromium/chromium steel (Cr/CrCu/Cu), titanium/copper/nickel (Ti/Cu/Ni), 'Xunxun/copper 201034141 (Al/NiV/Cu) and electroless nickel/gold (Ni/Au) The formation of the base 2i can be formed by electron beam evaporation, magnetron sputtering or electroless plating, etc. The plating base layer 220 is formed on the base 21, and the plating base layer 220 has a top. The surface 221 and the side surface 222. The side surface 222 can be an inclined wall to make the plating base layer 22 semi-tapered, thereby reducing the area of the top surface 221. More specifically, the plating base layer 220 can be It is a copper column (c〇pper pilUr). The copper column has the characteristics of high temperature resistance and non-deformation, so that the plating base layer 22 〇 can exert a good spacing maintenance effect, and does not cause bumps during the flip chip bonding process. Excessive collapse, and the copper pillars can be formed at low cost by electroplating. Further, the term "column" as used in the present invention means A height greater than the object's length is greater than a width of the object, or the object is larger than the diameter of the end face. Therefore, the electroplated base layer 220 is preferably elongated, and can be arranged in a high-density configuration with a fine pitch. The plated bonding layer 230 is formed only on the top surface 221 of the wrought base layer 22, and the side surface 222 is exposed. The top surface 221 is smaller than the base 210 to limit the plating bonding layer 23. Hey. In particular, the plated bonding layer 230 can be all metal. In detail, the material of the plating contact layer 230 may be selected from the group consisting of tin, silver, tin-lead and lead-free solder. The wrought joint layer 230 should have a refining point lower than that of the wrought base layer 220 and can be formed by electroplating. When the plated bonding layer 230 can be formed by electroplating, the reflow step can be omitted and a flat layer can be created on the limited top surface 22 without being wrapped back to the side 222 of the electroplated base layer 220. 201034141 Preferably, as shown in Fig. 3, the top surface 221 of the electroplated base layer 220 can be formed as a bowl-shaped socket, recessed at the center, and the periphery is nearly flat. The bowl-shaped socket can reduce the amount of extrusion of the plated bonding layer 230 that is extruded during the flip chip bonding to enhance the effect of preventing diffusion contamination. Preferably, the side 222 of the plating base layer 22 can be The wall is inclined such that the plated base layer 220 is semi-tapered, and may have a large bottom and a small convergence at the top to limit the formation area of the plated bonding layer 23 . The electric ore bonding layer 230 is formed only on the top surface 221 ′ of the plating base layer 22 , and the side surface 222 is exposed. The top surface 221 is smaller than the base 210 ′ to limit the plating bonding layer 230 . » Therefore, the plated bonding layer 230 can be concentrated and efficiently welded. When the thickness ratio of the electric forging bonding layer 230 to the plating base layer 220 is fixed to a predetermined value, the volume of the plating bonding layer 230 can be reduced. In the present embodiment, the thickness hi of the electric ore bonding layer 230 may be no more than one-half of the thickness H2 of the electroplated substrate 220 (as shown in Fig. 3). Therefore, the shape and position of the electroplating bonding layer 230 can be formed by using the electroplating bonding layer 230. The micro-pitch coating can be achieved by a low-temperature hot-welding method without solder reflow, and there is no short-circuit problem of bridging of the bonding material, and can be improved. The advantage of stress buffering after soldering. The plated bonding layer 230 can have a continuous side 23 i that is continuously joined to the side 222 of the plated base layer 220. The technical means can share a photoresist layer in the electroplating process (detailed later) to improve the process yield and reduce the cost of the fabrication process, and can solve the problem that the conventional bump bonding material needs to be reflowed and returned to the plating. Side 222 of base layer 220. In addition, 11 201034141, the electroplated bonding layer 230 may further have a top surface 232 which is smaller than the top surface 221 of the electroplated base layer 220 to make the micro pitch bumps appear convergent. 4A to 4H are schematic cross-sectional views showing the components of the micro pitch bump structure in the process according to the first embodiment of the present invention. The present invention further illustrates the process of the micro pitch bump structure to demonstrate the efficacy of the present invention.
首先，如第4A圖所示，提供一晶片20，該.晶片20 之一表面22具有複數個銲墊21，該晶片20之一表面22 形成有一保護層23，係局部包覆該些銲墊21之周邊。 該晶片20可形成於一晶圓。 接著，如第4B圖所示，形成一凸塊下金屬層30，係 覆蓋於該保護層23之上並接合於該銲墊21 ^該凸塊下 金屬30係作為凸塊的基底與電鍍種子層，具有附著於晶 片之銲墊21和該保護層23之性能。其中，該凸塊下金 屬層30係能以濺鍍方法形成 之後，如第4C圖所示，形成一光阻層4〇於該凸塊 下金屬層30上。該光阻層40係可為感光性介電材料， 可利用塗佈或貼附方式形成於該凸塊下金屬層上。 之後，如第4D圖所示，曝光顯影該光阻層4〇,以使 該光阻層40形成有一對應該銲墊21之開孔Ο，以顯露 該凸塊下金屬層30之一部位3卜該部位31為上述電鍍 :礎層222的預定形成位置。更具艘地，上述曝光顯影 〇光阻層40之步驟係包含等向性顯影 12 201034141First, as shown in FIG. 4A, a wafer 20 is provided. One surface 22 of the wafer 20 has a plurality of pads 21, and a surface 22 of the wafer 20 is formed with a protective layer 23 for partially covering the pads. Around the 21st. The wafer 20 can be formed on a wafer. Next, as shown in FIG. 4B, a under bump metal layer 30 is formed over the protective layer 23 and bonded to the pad 21. The under bump metal 30 is used as a bump base and plating seed. The layer has the properties of the pad 21 attached to the wafer and the protective layer 23. After the bump underlying metal layer 30 can be formed by a sputtering method, as shown in FIG. 4C, a photoresist layer 4 is formed on the under bump metal layer 30. The photoresist layer 40 can be a photosensitive dielectric material, and can be formed on the under bump metal layer by coating or attaching. Thereafter, as shown in FIG. 4D, the photoresist layer 4 is exposed and developed such that the photoresist layer 40 is formed with a pair of opening pads of the pads 21 to expose a portion of the under bump metal layer 30. This portion 31 is a predetermined formation position of the above-described plating: base layer 222. More preferably, the step of exposing and developing the photoresist layer 40 includes isotropic development 12 201034141
Developing)’以使該開孔41有傾斜的孔壁。例如，該 曝光顯影方式係為讓光源通過一光罩5〇之孔洞51，進 而在光阻層40上顯影出所需的開孔4丨。該開孔4i係可 利用負光阻之曝光不足方式使呈現收斂狀。 之後’如第4E圖所示，在該凸塊下金屬層3〇的導電 連通下’以電鍍方式形成一電鍍基礎層22〇於該凸塊下 金屬層3 0之顯露部位31並位於該開孔41内》該開孔 41係呈現底部大且頂部小的收斂狀，以使該侧壁42係 .為傾斜壁。故其内所形成之該電鍍基礎層22〇為半錐 形。該電鑛基礎層220係具有一頂面221與一侧面222， 其中該側面222係緊貼於該開孔41之側壁42，該頂面 221係不超出於該光阻層40。在本實施例中，自該電锻 基礎層220之該頂面221所形成之一碗狀承座係在此步 驟中形成。 之後，如第4F圖所示，在該凸塊下金屬層30與該電 鍍基礎層220的導電連通下，以電鍍方式形成一電鍍接 ® 合層23 0於該電鍍基礎層220之該頂面221。並在該光 阻層40之該開孔41之限制下，該電鍍接合層230不會 覆蓋至該電鍍基礎層220之該側面222。因此，該電鍍 接合層230係以電鍍方式形成於電鍍基礎層220上，並 且不需經過回焊步驟，故能避免因回焊所造成之回包汙 染至該電鍍基礎層220的側面222。其中該電鍍基礎層 220之頂面221係面積小於該凸塊下金屬層30之該部位 31’以用來限制該電鍍接合層230的面積。 13 201034141 在其後的-較佳步驟中，如第4G圖所示，在該電鍛 接合層230形成之後與在移除該光阻層4()之前另包含 之步驟為：平坦化研磨該光阻層40肖該電鍍接合層 230 ’以使該電鍵接…30不突出於該光阻層40。藉 此’平坦化該電鑛接合層23Q之方式，亦可使得該電鍛 接合層230之該頂面232為平坦化，以不突出於該光阻 層40。 最後，如第4H圖所示，移除該光阻層4〇,以顯露該 粵御222。其中該電艘接合《23〇係具有一速續側面 231，係連續地連接該電鍍基礎層22〇之該側面Μ]。藉 此，連續地連接彳式以|成不冑要回焊的一體化複合式 凸塊形狀。且該電鍍接合層23〇係更具有一頂面232, 係小於該電鍍基礎層220之該頂面221。最後，以蝕刻 方式移除該凸塊下金屬層30。此外，在該電鍍接合層23〇 與該電錄基礎層220之遮蔽下’該凸塊下金屬層3〇被該 電鍍基礎層220覆蓋的部位將被保留，而形成為上述之 • 底座21〇(如第3圖所示）》 依據本發明之第一具體實施例，—種微間距凸塊結構 舉例說明於第5圖之截面示意圖。該微間距凸塊結構 3 00 ’用以設置於一晶片20之一銲墊21上，該晶片2〇 之一表面22形成有一保護層23’係局部包覆該銲墊21 之周邊。該微間距凸塊結構300係包含一底座21〇、一 電鍍基礎層220以及一電鍍接合層23〇。其中與第一實 施例相同的主要元件將以相同符號標示，其中具有相同 14 201034141 或類似的作用與功效的部分在此不再予以贅述。較佳 地’該電鍍基礎層220係可具有一狹槽323，用以縮小 該頂面221之面積，藉以限制該電鍍接合層230之形成 面積’並且能在覆晶接合時收容多餘被擠出之該電鍍接 合層230。在本實施例中，該狹槽323係可貫穿至顯露 出該底座210，以使得該底座210上同時具有分離的兩 或多個微凸塊》 依據本發明之第三具體實施例，另一種微間距凸塊結 Φ 構舉例說明於第6圖之截面示意圖。該微間距凸塊結構 400 ’用以設置於一晶片2〇之一銲墊21上，該晶片2〇 之一表面22形成有一保護層23，係局部包覆該銲墊21 之周邊。該微間距凸塊結構400係包含一底座410、一 電鐘基礎層420、一囷案化電鍍接合層430。該底座410 係接合於該銲墊21並延伸到該保護層23上。其中該底 座410之作用與功效與第一實施例相同，故不再贅述。 該電鍍基礎層420係形成於該底座410上，該電鍍基 礎層420係具有一頂面421與一側面422。其中，該電 鍛基礎層420係可為一非柱狀的凸塊形狀，即其高度不 大於凸塊之寬度、長度或直徑。 該圖案化電鍍接合層43〇係僅形成於該電鍍基礎層 420之該頂面421，而顯露該側面422，並且該圖案化電 鍵接合層430之覆蓋面積係小於該頂面421。該圖案化 電鍍接合層430為不需要回焊並與該電鍍基礎層420結 合為複合式凸塊。該電鍍基礎層420之該頂面421未覆 15 201034141 蓋面積可供該圖案化電鍍接合層43 0的擠壓擴散，故能 達成微間距凸塊結構在晶片上可為微間距設置並且不會 有接合材料橋接之短路問題。 該圖案化電鍍接合層43 0係可具有單一個微凸塊對 應於一個電鍍基礎層42〇之形狀。該圖案化電鍍接合層 430之厚度係可不大於該電鍍基礎層420之二分之一厚 度’較佳應用為可達成微間距覆晶接合是使用免用回焊 的低溫熱壓合焊接。Developing) so that the opening 41 has a slanted hole wall. For example, the exposure development method is such that the light source passes through a hole 51 of a mask 5 to develop a desired opening 4 on the photoresist layer 40. The opening 4i can be rendered convergent by an underexposure method using a negative photoresist. Then, as shown in FIG. 4E, under the conductive connection of the metal layer 3〇 under the bump, an electroplated base layer 22 is formed by electroplating on the exposed portion 31 of the under-metal layer 30 of the bump and is located at the opening The opening 41 in the hole 41 has a large bottom and a small convergence at the top so that the side wall 42 is an inclined wall. Therefore, the plating base layer 22 formed therein has a semi-conical shape. The base layer 220 has a top surface 221 and a side surface 222. The side surface 222 is in close contact with the side wall 42 of the opening 41. The top surface 221 does not extend beyond the photoresist layer 40. In the present embodiment, a bowl-shaped socket formed from the top surface 221 of the electric forging base layer 220 is formed in this step. Then, as shown in FIG. 4F, a top surface of the plating base layer 220 is formed by electroplating under the conductive communication between the under bump metal layer 30 and the plating base layer 220. 221. The plated bonding layer 230 does not cover the side 222 of the plating base layer 220 under the restriction of the opening 41 of the photoresist layer 40. Therefore, the plating bonding layer 230 is formed on the plating base layer 220 by electroplating, and does not need to undergo a reflow step, so that the back coating due to reflow can be prevented from being contaminated to the side surface 222 of the plating base layer 220. The top surface 221 of the plating base layer 220 has an area smaller than the portion 31' of the under-metal layer 30 of the bump to limit the area of the plating bonding layer 230. 13 201034141 In a subsequent preferred step, as shown in FIG. 4G, the step of additionally including after the formation of the wrought bonding layer 230 and before removing the photoresist layer 4 is: planarizing the polishing The photoresist layer 40 is plated with the bonding layer 230' such that the electrical contacts ... 30 do not protrude from the photoresist layer 40. By flattening the electrodeposited bonding layer 23Q, the top surface 232 of the wrought bonding layer 230 may be planarized so as not to protrude from the photoresist layer 40. Finally, as shown in Fig. 4H, the photoresist layer 4 is removed to reveal the Yusuke 222. Wherein the electric boat is engaged with the "23" series having a continuous side surface 231 which is continuously connected to the side surface of the electroplated base layer 22". As a result, the integrated composite bump shape is continuously connected to the 彳 type. The plated bonding layer 23 has a top surface 232 which is smaller than the top surface 221 of the plating base layer 220. Finally, the under bump metal layer 30 is removed by etching. In addition, under the shielding of the plating bonding layer 23 and the accommodating base layer 220, the portion where the under bump metal layer 3 is covered by the plating base layer 220 is retained, and is formed into the above-mentioned base 21 〇 (As shown in Fig. 3) According to a first embodiment of the present invention, a micro-pitch bump structure is illustrated in a cross-sectional view of Fig. 5. The micro pitch bump structure 300' is disposed on one of the pads 21 of a wafer 20. One surface 22 of the wafer 2 is formed with a protective layer 23' to partially cover the periphery of the pad 21. The micro pitch bump structure 300 includes a base 21, an electroplated base layer 220, and an electroplated bonding layer 23A. The same main elements as those in the first embodiment will be denoted by the same reference numerals, and portions having the same effect and efficacy of 14 201034141 or the like will not be described herein. Preferably, the electroplated base layer 220 can have a slot 323 for reducing the area of the top surface 221, thereby limiting the formation area of the electroplated bonding layer 230 and accommodating excess during the flip chip bonding. The plating joint layer 230 is formed. In this embodiment, the slot 323 can be penetrated to expose the base 210 such that the base 210 has two or more micro-bumps at the same time. According to the third embodiment of the present invention, another The micro pitch bump junction structure is illustrated in the cross-sectional view of Fig. 6. The micro pitch bump structure 400' is disposed on a pad 21 of a wafer 2, and a surface 22 of the chip 2 is formed with a protective layer 23 for partially covering the periphery of the pad 21. The micro pitch bump structure 400 includes a base 410, an electric clock base layer 420, and a patterned plating joint layer 430. The base 410 is bonded to the bonding pad 21 and extends to the protective layer 23. The function and function of the base 410 are the same as those of the first embodiment, and therefore will not be described again. The plating base layer 420 is formed on the base 410. The plating base layer 420 has a top surface 421 and a side surface 422. The electric forging base layer 420 can be a non-columnar shaped bump shape, that is, the height is not greater than the width, length or diameter of the bump. The patterned plated bonding layer 43 is formed only on the top surface 421 of the plating base layer 420 to expose the side surface 422, and the patterned electrode bonding layer 430 has a smaller coverage area than the top surface 421. The patterned plated bonding layer 430 does not require reflow and is combined with the plated base layer 420 as a composite bump. The top surface 421 of the plating base layer 420 is uncovered 15 201034141. The cover area is available for the extrusion diffusion of the patterned plating bonding layer 43 0. Therefore, the micro pitch bump structure can be achieved on the wafer and can be set for the micro pitch. There is a short circuit problem in which the bonding material is bridged. The patterned plated bonding layer 430 may have a single microbump corresponding to the shape of a plated base layer 42. The thickness of the patterned electroplated bonding layer 430 may be no more than one-half the thickness of the electroplated base layer 420. A preferred application is to achieve a micro-spaced flip-chip bonding using a low temperature thermocompression bonding that is free of reflow.
❹ 依據本發明之第四具體實施例，另一種微間距凸塊結 構舉例說明於第7圖之截面示意圖。該微間距凸塊結構 500中’其與第三實施例皆具有相同的主要元件將以相 同符號標示’並由於具有相同或類似的作用與功效，故 在此不再予以贅述。 在本實施例中，該圖案化電鍍接合層430係可具有 複數個分離微凸塊所組成之圖案，同樣地能達到不需 回焊的一體化複合式凸塊形狀，並且不會有接合材料 接之短路問題’並能增進在焊接後之應力緩衝。 以上所述，僅是本發明的較佳實施例而已，並非對 發明作任何形式上的限制，雖然本發明已以較佳實施 揭露如上’然❿並非用以限定本發日月，任何熟悉本項 術者，在不脫離本發明之技術範圍内，所作的任何簡 修改、等效性變化與修飾，均仍屬於本發明的技術範 内。 【圖式簡單說明】 16 201034141 第1圖：為習知微間距凸塊結構之截面示意圖。 第2圖：為習知晶片以微間距凸塊結構覆晶結合至一印 刷電路板之截面示意圖。 第3圖：為依據本發明之第-具體實施例的-種微間距 凸塊結構之截面示意圖。 第4A至4H圖·為依據本發明之第一具體實施例的微間 距凸塊結構在製程中元件之截面示意圖。 第5圖：為依據本發明之第二具體實施例的另一種微間 距凸塊結構之截面示，意圖。 第6圖：為依據本發明之第三具體實施例的另一種微間 距凸塊結構之截面示意圖。 第7圖：為依據本發明之第四具體實施例的另一種微間 距凸塊結構之截面示意圖。 【主要元件符號說明】 H1 厚度 H2 厚度 10 印刷電路板 12 凸塊接墊 20 晶片 21 銲墊 22 表 23 保護層 / 30 凸塊下金屬層 31 部位 40 光阻層 41 開孔 42 側壁 50 光罩 51 孔洞 100 微間距凸塊結構 110 底座 120 基礎層 121 頂面 122 側面 17 201034141 1 3 0 回焊銲料 200微間距凸塊結構 210底座 220電鍍基礎層 221 頂面 222側面 232頂面 230電鍍接合層 231 連續侧面 3 00微間距凸塊結構 323狹槽 400微間距凸塊結構 • 410底座 420電鍍基礎層 421 頂面 422側面 430圖案化電鍍接合層 500微間距凸塊結構 18According to a fourth embodiment of the present invention, another micro pitch bump structure is illustrated in a cross-sectional view of Fig. 7. In the micro-pitch bump structure 500, the same main elements as those of the third embodiment will be denoted by the same reference numerals and have the same or similar functions and effects, and therefore will not be described again. In this embodiment, the patterned electroplated bonding layer 430 can have a pattern composed of a plurality of discrete microbumps, and can also achieve an integrated composite bump shape without reflow, and there is no bonding material. The short-circuit problem is combined to improve the stress buffer after soldering. The above is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. It is still within the technical scope of the present invention to make any modifications, equivalent changes and modifications made by the subject matter without departing from the technical scope of the present invention. [Simple description of the figure] 16 201034141 Fig. 1 is a schematic cross-sectional view of a conventional micro-pitch bump structure. Fig. 2 is a schematic cross-sectional view showing a wafer in which a conventional wafer is flip-chip bonded to a printed circuit board with a fine pitch bump structure. Fig. 3 is a schematic cross-sectional view showing a micro-pitch bump structure in accordance with a first embodiment of the present invention. 4A to 4H are cross-sectional views showing the components of the micro-pitch bump structure in the process according to the first embodiment of the present invention. Figure 5 is a cross-sectional view showing another micro-pitch structure in accordance with a second embodiment of the present invention. Figure 6 is a cross-sectional view showing another micro-pitch bump structure in accordance with a third embodiment of the present invention. Figure 7 is a cross-sectional view showing another micro-pitch bump structure in accordance with a fourth embodiment of the present invention. [Main component symbol description] H1 Thickness H2 Thickness 10 Printed circuit board 12 Bump pad 20 Wafer 21 Solder pad 22 Table 23 Protective layer / 30 Bump under metal layer 31 Part 40 Photoresist layer 41 Opening 42 Side wall 50 Photomask 51 hole 100 micro pitch bump structure 110 base 120 base layer 121 top surface 122 side 17 201034141 1 3 0 reflow solder 200 micro pitch bump structure 210 base 220 plating base layer 221 top surface 222 side 232 top surface 230 plating joint layer 231 continuous side 300 ft micro pitch bump structure 323 slot 400 micro pitch bump structure • 410 base 420 plating base layer 421 top surface 422 side 430 patterned plating joint layer 500 micro pitch bump structure 18