CN105789066A - Manufacturing method for semiconductor packaging structure - Google Patents
Manufacturing method for semiconductor packaging structure Download PDFInfo
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- CN105789066A CN105789066A CN201610302306.1A CN201610302306A CN105789066A CN 105789066 A CN105789066 A CN 105789066A CN 201610302306 A CN201610302306 A CN 201610302306A CN 105789066 A CN105789066 A CN 105789066A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a manufacturing method for a semiconductor packaging structure. The method comprises the following steps: providing a substrate; forming a dielectric layer on the substrate; forming a rewiring layer on the dielectric layer; forming a first terminal on the rewiring layer, wherein the first terminal comprises welding flux; providing a chip which comprises a chip main body, an electrode disposed on the chip main body, and a metal convex block fixed on the electrode; and fixing the metal convex block on the rewiring layer through employing the welding flux. According to the invention, the metal convex block is used for replacing spherical welding flux formed on the electrode in the prior art, enables the metal convex block to be fixed on the rewiring layer through employing the welding flux formed in the first terminal on the rewiring terminal, and can effectively prevent the bridge connection and alpha rays in the welding flux from affecting the performances of the chip. Furthermore, the pitch of terminals in a semiconductor structure formed through the method is reduced, and enables the forming of a plurality of terminals on a small-size chip to be possible.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the manufacture method of a kind of semiconductor package.
Background technology
In recent years, semiconductor device is under the collectively promoting of cost reduction and the lifting of front road wafer manufacturing process, achieve the target that the monomer chip size of the semiconductor device of said function is increasingly less, so can cause on semiconductor device more and more less for the pitch between external electrode, originally for the semiconductor device structure of flip chip bonding easily caused by the bridge joint between electrode thus causing semiconductor device failure.
Being presently used in the semiconductor device structure of flip chip bonding, semiconductor chip and again connection between circuit board form spherical salient point generally by after electrode enterprising row metal solder refluxes, and are then inverted in circuit board again and are formed.As it is shown in figure 1, be the structural representation of the semiconductor package that prior art provides.Semiconductor chip 101 is provided with electrode 102; semiconductor chip 101 and electrode 102 are optionally coated with the passivation layer 103 that the material such as silicon oxide or silicon nitride is formed, passivation layer 103 can be selectively formed one layer of protective layer 104 formed by polyimides PI, PBO etc. again.Then, adding electroplating technique at electrode 102 surface formation UBM metal level 105 and plated metal solder 106 by sputtering, metal level 107 and electroless nickel layer 108 that typical UBM metal level 105 is made up of the titanium layer sputtered and layers of copper form.Form spherical salient point (as shown in Figure 1) after brazing metal 106 backflow, be finally inverted in again on wiring layer 200, form the existing flip chip packaging structure shown in Fig. 1.
In this flip chip packaging structure, although structurally meet the requirement of flip chip packaging structure, but owing to brazing metal 106 is formed directly on electrode, it is easy to cause the bridge joint between electrode.Additionally, brazing metal 106 is arranged near semiconductor chip, cause that chip performance is impacted by the alpha ray in brazing metal 106.On the other hand, prior art wiring layer 200 again adopts the etching technics of complexity to be formed, and production cost height and thickness are difficult to semiconductor device, the design requirement of size of current is adjusted.
Summary of the invention
The technical problem that present invention mainly solves is to provide a kind of semiconductor package, the impact that chip performance is caused by the alpha ray in order to be prevented effectively from interelectrode bridge joint and brazing metal..
For solving above-mentioned technical problem, the technical scheme that the present invention adopts is to provide the manufacture method of a kind of semiconductor package, and described manufacture method comprises the following steps:
One base material is provided；
Form dielectric layer on the substrate；
Described dielectric layer is formed wiring layer again；
Forming the first terminal on described wiring layer again, wherein said the first terminal includes solder；
The electrode provide a chip, described chip to include chip body, being arranged in described chip body and fixing metal coupling on the electrodes；
Utilize described solder described metal coupling is fixed on described in again on wiring layer.
Wherein, the described step forming dielectric layer on the substrate includes:
Described dielectric layer is formed the first opening；
The described step forming again wiring layer on described dielectric layer includes:
Described dielectric layer is formed the first mask layer；
Described first mask layer is being exposed and development treatment, to form the second opening at least exposing described first opening on described first mask layer；
In described first opening, the second terminal is formed and wiring layer again described in being formed in described second opening with described first mask layer for mask.
Wherein, described in described first opening, the second terminal is formed with described first mask layer for mask and the step of wiring layer again described in being formed in described second opening includes:
Described second terminal and described wiring layer again it is integrally formed with electroplating technology.
Wherein, the described step forming the first terminal on described wiring layer again includes:
Described wiring layer again forms the second mask layer；
Described second mask layer is being exposed and development treatment, to form the 3rd opening of wiring layer again described in part exposure on described second mask layer；
In described 3rd opening, form metal column, and on the end of described chip body, form described solder at described metal column；
Peel off described second mask layer, expose described metal column and described solder.
Wherein, the described metal column that formed in described 3rd opening, and including towards the step forming described solder on the end of described chip body at described metal column:
In described 3rd opening, described metal column and described solder is sequentially formed by electroplating technology.
Wherein, the described metal column that formed in described 3rd opening, and including towards the step forming described solder on the end of described chip body at described metal column:
In described 3rd opening, described metal column is formed by electroplating technology；
The described end of described metal column is carried out microcorrosion and forms described solder on described end by planting ball reflow soldering process.
Wherein, the described step forming the first terminal on described wiring layer again includes:
Described wiring layer again forms the second mask layer；
Described second mask layer is being exposed and development treatment, to form the 3rd opening of wiring layer again described in part exposure on described second mask layer；
By electroplating or typography forms described solder in described 3rd opening so that described solder directly contact described in wiring layer again；
Wherein, the step of described offer one chip includes:
By ultrasonic welding process, described metal coupling is fixed on described electrode.
Wherein, described utilize described solder described metal coupling is fixed on described in again the step on wiring layer include:
By reflow soldering process described metal coupling is fixed on described in again on wiring layer so that described metal coupling is inserted in described solder.
Wherein, described manufacture method farther includes:
Utilize packing material that described chip, described wiring layer again and described the first terminal are filled with；
Described base material is removed from described dielectric layer.
The invention has the beneficial effects as follows: the present invention utilizes metal coupling to replace the spherical solder being formed on electrode of the prior art, and utilize the solder in the first terminal being formed at again on wiring layer to be fixed on again by metal coupling on wiring layer, the impact on chip performance of the alpha ray in interelectrode bridge joint and solder can be prevented effectively from.Further, reduced by the pitch of terminal in the semiconductor package that this manufacture method is formed, make on small-size chips, realize multi-terminal and be possibly realized.
Accompanying drawing explanation
Fig. 1 is the structural representation of the semiconductor package that prior art provides；
Fig. 2 is the schematic flow sheet of the embodiment one of the manufacture method of semiconductor package provided by the invention；
Fig. 3 a-Fig. 3 j is the sectional drawing of semiconductor package in each step in manufacture method of the present invention；
Fig. 4 is the sectional drawing of the alternate embodiment of the step S4 of the manufacture method shown in Fig. 2.
Fig. 5 is the structural representation of the semiconductor package one that manufacture method provided by the invention is formed；
Fig. 6 is the structural representation of the semiconductor package two that manufacture method provided by the invention is formed.
Detailed description of the invention
Below in conjunction with drawings and embodiments, the present invention is described in detail, and in accompanying drawing, the size of each several part is only signal, does not represent the size of practical devices.
Refer to the schematic flow sheet of embodiment one that Fig. 2 and Fig. 3 a-Fig. 3 j, Fig. 2 are the manufacture methods of semiconductor package provided by the invention；Fig. 3 a-Fig. 3 j is the sectional drawing of semiconductor package in each step in manufacture method of the present invention.As in figure 2 it is shown, the manufacture method of this semiconductor package specifically includes following steps:
S1: a base material S is provided.
In this step, base material S can be silicon material, rustless steel, copper coin, impurity iron etc., it is preferred to impurity iron, and cost is low and easily removes in postchannel process.
S2: form dielectric layer 401 on base material S.
In this step, it is preferable that form multiple opening 401a at dielectric layer 401, as shown in Figure 3 a.The material of dielectric layer 401 can be polyimides, PBO etc..
S3: form wiring layer 402 again on dielectric layer 401.
In this step, on dielectric layer 401, first form the first mask layer 407, and the first mask layer 407 is exposed and development treatment, to form the second opening 407a at least exposing the first opening 401a on the first mask layer 407, as shown in Figure 3 b.
Further, in the first opening 401a, form the second terminal 406 with the first mask layer 407 for mask and in the second opening 407a, form wiring layer 402 again, and peeling off the first mask layer 407, as shown in Figure 3 c.In a preferred embodiment, the second terminal 406 is identical with the material of wiring layer 402 again, for instance copper, and is integrally formed by electroplating technology.Certainly, the material of the second terminal 406 and wiring layer 402 again can be different, it is also possible to formed by different technique, for instance first adopt electroplating technology to be formed wiring layer 402 again that material is copper, then adopt screen painting to form the second terminal 406 that material is stannum.
The thickness of the second terminal 406 and wiring layer 402 again can be regulated and controled, by simple technological operation so that it is be applied to the semiconductor device of different size according to the design requirement of size of current.Further, it is possible to repeat this step to form at least two-layer wiring layer again and/or the second terminal as required.
S4: form the first terminal 403 on wiring layer 402 again.
In this step, wiring layer 402 again is formed the second mask layer 408, and the second mask layer 408 is exposed and development treatment, expose again the 3rd opening 408a of wiring layer 402 with formation part on the second mask layer 408, as shown in Figure 3 d.
Further, in the 3rd opening 408a formed metal column 405, and metal column 405 away from the end of wiring layer 402 again formed solder 404, as shown in Figure 3 e.Peel off the second mask layer 408, expose metal column 405 and solder 404, as illustrated in figure 3f.
The material of metal column 405 is preferably copper.In a preferred embodiment, sequentially forming metal column 405 and solder 404 by plating or other suitable techniques in the 3rd opening 408a, now solder 404 is the layer structure of consistency of thickness.In the alternative, only can form metal column 405 in the 3rd opening 408a, and the end of metal column 405 is carried out microcorrosion and forms solder 404 on metal column 405 end by planting ball reflow soldering process.Further, it is also possible to form solder 404 by typography, now the variable thickness of solder 404 is surely consistent.
S5: provide a chip 300, including chip 301, chip 301 is provided with electrode 302, electrode 302 is provided with metal coupling 303, as shown in figure 3g.
The shape of metal coupling 303 is not limit, and material can include at least one in copper, gold, stannum, it is preferred that the material of metal coupling 303 farther includes titanium.Metal coupling be preferably shaped to column.In this step, it is preferable that by ultrasonic welding process (such as, thermosonic welding), metal coupling 303 is fixed on electrode 302.
S6: utilize solder 404 to be fixed on again on wiring layer 402 by metal coupling 303.
In this step, it is preferable that by reflow soldering process, metal coupling 303 is fixed on wiring layer 402 again.The first terminal 403 includes solder 404 and metal column 405, and metal coupling 303 contacts solder 404, and solder 404 refluxes rear section protuberance, and then is wrapped up the end of metal coupling 303, as illustrated in figure 3h.
S7: utilize packing material 500 that chip 300, again wiring layer 402 and the first terminal 403 are filled with, as shown in figure 3i；
S8: remove base material S from dielectric layer 401, as shown in Fig. 3 j.
Can pass through to remove, grind, the mode such as corrosion removes base material S.
Further, it is also possible to microcorrosion can passed through in the end of the second terminal 406 and planting ball reflow soldering and form spherical solder bump 406a.
Schematic cross-section with reference to the alternate embodiment that Fig. 4, Fig. 4 are the step S4 shown in Fig. 2.
In the present embodiment, dielectric layer 801, again wiring layer 802 and the second terminal 801 are formed on base material S in the same fashion as figure 2, itself and the embodiment shown in Fig. 2 are different in that, directly form solder 804 with plating or mode of printing on wiring layer 802 again.Such as, the second mask layer on wiring layer 802 again is being exposed and development treatment, and then form the 3rd opening (identical with embodiment illustrated in fig. 2), in the 3rd opening, form solder 804 by plating or typography, so that solder 804 directly contacts wiring layer 802 again.Solder 804 is preferably the layer structure of consistency of thickness, and part is swelled in reflux course.
Refer to the structural representation that Fig. 5, Fig. 5 are the semiconductor packages one that manufacture method provided by the invention is formed.As it is shown in figure 5, this semiconductor package includes chip 300 and carrier 400.Further, chip 300 include chip body 301, the electrode 302 that is arranged in chip body 301 and the metal coupling 303 being fixed on electrode 302.In a preferred embodiment, metal coupling 303 is fixed on electrode 302 in ultrasonic bonding mode (such as, thermosonic welds), and the lateral dimension D1 of metal coupling 303 is less than the lateral dimension D2 of electrode 32.
In the present embodiment, chip 300 farther includes the passivation layer 304 being covered on chip body 301 and electrode 302, being provided with opening 304a on passivation layer 304, electrode 302 exposes at least partly through opening 304a, and metal coupling 303 is fixed on the exposed parts of electrode 302 and protrudes from passivation layer 304.Passivation layer 304 can include silicon nitride, silicon oxide, other insulator or their combination or multiple structure.
Carrier 400 includes dielectric layer 401, be formed on dielectric layer 401 wiring layer again 402 and the first terminal 403 being formed at again on wiring layer 402.The material of dielectric layer 401 can be polyimides, PBO etc..In the present embodiment, the first terminal 403 includes solder 404 and metal column 405.Wherein, metal column 405 is formed on wiring layer 402 again, solder 404 be formed at metal column 405 on the end of chip body 301.Metal coupling 303 is fixed on wiring layer 402 by solder 404 again.In a preferred embodiment, metal coupling 303 is fixed on wiring layer 402 in Reflow Soldering mode by solder 404 again.Specifically, being tipped upside down on by metal coupling 303 on solder 404, solder 404 backflow makes metal coupling 303 be placed in solder 404 and fix.The shape of metal coupling 303 is not limit, and material can include at least one in copper, gold, stannum, it is preferred that the material of metal coupling 303 farther includes titanium.Metal coupling be preferably shaped to column.The material of metal column 405 is preferably copper.
In a preferred embodiment, the lateral dimension D3 of solder 404 is more than the lateral dimension D1 of metal coupling 303, so that metal coupling 303 is inserted in solder 404.It is further preferred that the end that metal coupling 303 is inserted in solder 404 is tip-shape setting.
In the present embodiment, dielectric layer 401 being provided with opening 401a, carrier 400 farther includes to be formed in opening 401a and second terminal 406 in electrical contact with wiring layer 402 again.In the present embodiment, carrier 400 only includes one layer of wiring layer 402 and second terminal 406 again, can also include at least two-layer wiring layer again and/or the second terminal in other embodiments.In a preferred embodiment, the second terminal 406 is identical with the material of wiring layer 402 again, for instance copper, and one-body molded by electroplating technology.Certainly, the material of the second terminal 406 and wiring layer 402 again can be different, it is also possible to formed by different technique, for instance first adopt electroplating technology to be formed wiring layer 402 again that material is copper, then adopt screen painting to form the second terminal 406 that material is stannum.
According to semiconductor device the design requirement of size of current can be regulated and controled the thickness of the second terminal 406 and wiring layer 402 again, by simple technological operation so that it is be applied to the semiconductor device of different size.
Further, the gap between chip 300 and carrier 400 is filled with by packing material 500 and can pass through microcorrosion in the end of the second terminal 406 and plant ball reflow soldering and form spherical solder 406a.
By the way, utilize metal coupling to replace the spherical solder being formed on electrode of the prior art, and utilize the solder in the first terminal being formed at again on wiring layer to be fixed on again by metal coupling on wiring layer, interelectrode bridge joint can be prevented effectively from.Simultaneously as solder compared to prior art away from chip body, and then avoid the impact on chip performance of the alpha ray in solder.Further, in above-mentioned semiconductor package, the pitch of terminal reduces, and makes to realize multi-terminal on small-size chips and is possibly realized.Additionally, use again wiring layer to replace conventional substrate, it does not have the protective layer in conventional substrate, reduce dead resistance.The existence of metal column can increase chip and spacing between wiring layer again, is conducive to the diffusion of packing material when being filled with.
Referring to Fig. 6, wherein Fig. 6 is the structural representation of the semiconductor package two that manufacture method provided by the invention is formed.
As shown in Figure 6, this semiconductor package includes chip 600 and carrier 700.Embodiment shown in Fig. 6 is distinguished by with the embodiment shown in Fig. 5, and the metal coupling 603 on chip 600 is fixed by the solder 704 being formed directly into again on wiring layer 702.
These are only embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every equivalent structure utilizing description of the present invention and accompanying drawing content to make or equivalence flow process conversion; or directly or indirectly it is used in other relevant technical fields, all in like manner include in the scope of patent protection of the present invention.
Claims (10)
1. the manufacture method of a semiconductor package, it is characterised in that described manufacture method comprises the following steps:
One base material is provided；
Form dielectric layer on the substrate；
Described dielectric layer is formed wiring layer again；
Forming the first terminal on described wiring layer again, wherein said the first terminal includes solder；
The electrode provide a chip, described chip to include chip body, being arranged in described chip body and fixing metal coupling on the electrodes；
Utilize described solder described metal coupling is fixed on described in again on wiring layer.
2. manufacture method according to claim 1, it is characterised in that the described step forming dielectric layer on the substrate includes:
Described dielectric layer is formed the first opening；
The described step forming again wiring layer on described dielectric layer includes:
Described dielectric layer is formed the first mask layer；
Described first mask layer is being exposed and development treatment, to form the second opening at least exposing described first opening on described first mask layer；
In described first opening, the second terminal is formed and wiring layer again described in being formed in described second opening with described first mask layer for mask.
3. manufacture method according to claim 2, it is characterised in that described form the second terminal in described first opening with described first mask layer for mask and the step of wiring layer again described in being formed in described second opening includes:
Described second terminal and described wiring layer again it is integrally formed with electroplating technology.
4. manufacture method according to claim 1, it is characterised in that the described step forming the first terminal on described wiring layer again includes:
Described wiring layer again forms the second mask layer；
Described second mask layer is being exposed and development treatment, to form the 3rd opening of wiring layer again described in part exposure on described second mask layer；
In described 3rd opening, form metal column, and on the end of described chip body, form described solder at described metal column；
Peel off described second mask layer, expose described metal column and described solder.
5. manufacture method according to claim 4, it is characterised in that the described metal column that formed in described 3rd opening, and including towards the step forming described solder on the end of described chip body at described metal column:
In described 3rd opening, described metal column and described solder is sequentially formed by electroplating technology.
6. manufacture method according to claim 4, it is characterised in that the described metal column that formed in described 3rd opening, and including towards the step forming described solder on the end of described chip body at described metal column:
In described 3rd opening, described metal column is formed by electroplating technology；
The described end of described metal column is carried out microcorrosion and forms described solder on described end by planting ball reflow soldering process.
7. manufacture method according to claim 1, it is characterised in that the described step forming the first terminal on described wiring layer again includes:
Described wiring layer again forms the second mask layer；
Described second mask layer is being exposed and development treatment, to form the 3rd opening of wiring layer again described in part exposure on described second mask layer；
By electroplating or typography forms described solder in described 3rd opening so that described solder directly contact described in wiring layer again.
8. manufacture method according to claim 1, it is characterised in that the step of described offer one chip includes:
By ultrasonic welding process, described metal coupling is fixed on described electrode.
9. manufacture method according to claim 1, it is characterised in that described utilize described solder described metal coupling is fixed on described in again the step on wiring layer include:
By reflow soldering process described metal coupling is fixed on described in again on wiring layer so that described metal coupling is inserted in described solder.
10. manufacture method according to claim 1, it is characterised in that described manufacture method farther includes:
Utilize packing material that described chip, described wiring layer again and described the first terminal are filled with；
Described base material is removed from described dielectric layer.
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| CN201610302306.1A CN105789066A (en) | 2016-05-09 | 2016-05-09 | Manufacturing method for semiconductor packaging structure |
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| CN201610302306.1A CN105789066A (en) | 2016-05-09 | 2016-05-09 | Manufacturing method for semiconductor packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI692067B (en) * | 2018-03-15 | 2020-04-21 | 日商東芝記憶體股份有限公司 | Semiconductor device |
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