1357141 .九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種封裝基板及封裝 具電性連接結構之封裝基板及其半導體封構種 【先前技術】 装…構。 在現4亍覆晶（Flip Chid)枯供由. 半導俨祢田而1 ’於積體電路（1C)之 牛V體日日片的作用面上具有電極墊，而有 目 相對應該電極墊之電性連接墊 $板亦，、有 伽+ Α Λ +導體晶片之電極墊 板之電性連接塾之間形成焊錫結構或其他導電黏 者材料，該焊錫結構或導電㈣㈣提供該半導體晶片以 =電路板之間的電性連接以及機械性的連接，相關技術如 幻Α至1G圖所示。首先提供一基板本體1〇，係具有内 層線，ιοί及複數電性連接墊103’該電性連接塾1〇3位 於覆蓋該内層線路1〇1之介電層1〇2表面上，且該些電性 ，接墊103以導電盲孔104電性連接該内層線路⑻如 第1A圖所示；接著，於該介電層1〇2表面上形成一係如 防烊層之絕緣保護層u，於該絕緣保護層n中形成複數 相對應該電性連接墊103之開孔11〇，如第1B圖所示； 之後於該絕緣保護層U上表面、該開孔n〇側表面及顯 露於該開孔110之電性連接墊1〇3上表面形成一導電層 12,然後於該導電層12上表面形成一阻層13，於該阻層 13中形成複數開口 130以對應顯露該開孔11 〇及電性連 接塾103表面上的導電層12,如第·1(：圖所示；藉由該導 電層12作為電鑛之電流傳導路徑以於該阻層13之開口 5 110478 丄33/丄4丄 :130中電鐵形成係如焊錫之導電 係電性連接該電性連㈣1Q3，如電 除該阻層13及其所覆罢之導兩芦 Θ 丁，一後移 14,如第1ES所-' 層12以顯露該導電材料 E圖所不；之後，經回焊（^_^丨製 電材料14融熔成一係如錫球導 -封裝基板1，如第㈣所示。…件14，俾以完成 二=閲第1G圖’該封裝基w具有第一表面u及第 :表面ib’於該第_表面la具有該絕緣保 3緣保護層u中具有該外露之導電元件14，…半J 二具有一作用面2a，於該作用面2a具有複數相對 二導電凸塊21，使該導電元件“，經迴 包覆該導電凸塊2卜俾將該半導體晶片 連接該基板1，且於㈣裝純i財導體晶片 間填充有底部填耀 (un(jer;f i 1 1 )23。 惟，該導電元件14，係採用凸出於該絕緣保護層n 之上表面’使該半導體晶片2之導電凸塊21經迴焊而接 置於該導電元件14,後，該半導體晶片2與封裝基板}之 間的間隔較大，使得封裝體高度無法降低，而無法達到薄 小封裝之目的。 另外，該導電元件14，係形成於該平直之電性連接墊 1〇3表面，使該導電元件14，與電性連接墊1〇3之間的接 觸面積較小’因此該導電元件14，與電性連接塾1〇3之 間的結合力較弱，導致該導電元件14，容易產生脫落的情 110478 6 1357141 再者，該封裝基板！之導電元件14，凸出於該絕緣保 4層11表面且為球狀，使該半導體晶片2之導電凸塊21 與導電元件14,對接並經迴焊而接置後，為避免該些導電 元件14,於融溶狀態下因互相接觸而發生導致短路之橋接 (㈣㈣，該些導電元件14,之間必須保持較大的間距， 因此無法達到細間距以達增加輸出/輸入Unput/〇utput) 接點數之目的。 此外，該導電材料14經印刷及迴焊而形成導電元件 14’後，該導電元件14，之高度共面性不佳，使該半導體晶 片2之導電凸塊21與導電元件14’迴焊而對接後，因應 力分佈不均而導致該封裝體之接點斷裂或接觸不良，因此 降低可靠度，而影響產品的品質。 因此’如何提供一種得縮小封裝基板與半導體晶片之 間的間隔以達到薄小封裝、避免導電元件脫落、並且縮小 電性連接塾之間的間距以供細間距之應用、以及避免該導 電π件之高度共面性不佳所致之應力分佈不均，已成為業 界之重要課題。 0 〃 【發明内容】 鑑於上述習知技術之缺失，本發明之一目的係在於 提供一種具電性連接結構之封裝基板及其半導體封裝結 構，#降低封t體高度以達薄小化之封裝結構。 本發明又一目的係在於提供一種具電性連接結構之 封裝基板及其半導體封裝結構，得增加電性連接墊與焊接 材料之間的結合性，以避免該焊接材料產生脫落，俾提高 110478 7 1357141 •可靠度。 才毛月再一目的係在於提供一種具 :::板導體，構，得避免焊接二= • 進而得縮小電性連接墊之間的間距。 本發明另-目的係在於提供—種 •封裝基板及其半導體封梦处搂^ ^ 埂接^構之 丑 封裝…構，仵以避免焊接材料之高度 面性不么而致應力分佈不均的情況。 .構之及，他目的’本發明揭露一種具電性連接結 >構之封裝基板，係包括：基板本體，其至少一表面 ，層及設於其中之複數電性連接墊，該些電性連接墊之: 表面形成凹陷部且未高於該介電層；焊接 該電性連接墊之凹陷部中；以及絕緣 ^= 材料。 且〃有複數開孔以對應顯露該些焊接 依上述之結構，該絕緣保護層之開孔 戈 =連接?尺寸;復包括表面處理層，係設二 鋅/金or/凹與該焊接材料之間；該表面處理層係為 ㈤^)、錦Μ〆金（Nl/Pd/Au)、銀（Ag)及金㈤） 者，該焊接材料復延伸至該絕緣保護層之開孔 孔周緣之表面;或者，該谭接材料LI: 於、月平及低於該介電層上表面之其中—者，且未高詩 絕緣保護層之上表面。 ；“ 包括·基板本體’其至少一表面具有介電層及設於其尹之 110478 1357141 :複數電性連接墊與線路，該些電性連接墊之上表面具有凹 .陷部且未高於該介電層’該些線路之上表面係未高於該介 %層，：接材料，係没於該些電性連接塾之凹陷部中；以 及絕緣保護層，係設於該基板本體表面之線路區域並覆蓋 該些線路之上表面。 依上述之結構，復包括表面處理層，係設於該電性連 接墊之凹陷部與該焊接材料之間；該表面處理層係為錄/ 金（Ni/Au)、鎳/鈀 / 金（Ni/Pd/Au)、銀（Ag)及金（Au)之直 •中一者。 '、 本發明復提供一種半導體封裝結構，係包括：封裝基 板係於基板本體之至少一表面設有介電層，且於該介電 層中設有複數電性連接塾，該些電性連接塾之上表面並形 成凹陷部且未高於該介電層，於該凹㈣巾我有悍接材 又该介電層卩焊接材料上設有絕緣保護層’該絕緣保 蒦詹中…有複數開孔以對應顯露該焊接材料；半導體晶 藝片，係具有一作用面，該作用面具有複數導電凸塊，並藉 由該谭接材料以對應電性連接該封裝基板之電性連接塾 與，導體晶片之導電凸塊；以及底部填膠(underiiu)， 係設於該絕緣保護層及該半導體晶片之間。 依上述之結構，該絕緣保護層之開孔尺寸係小於及大 於該電性連接塾尺寸之其中一者；復包括表面處理層，係 设於該電性連接塾之凹陷部與該焊接材料之間；該表面 處理層係、為鎳/金⑻仏）、鎳/纪/金（Ni/Pd/Au)、銀（Ag) 及金（An)之其中一者。 110478 9 1357141 -：本發明復提供一種半導體封裝結構，係包括：封裝基 .板，係於基板本體之至少一表面設有介電層，且於該介電 層中設有複數電性連接墊與線路，該些電性連接墊之上表 面具有凹陷部且未高於該介電層，該些線路之上表面係未 问於該介電層，且該些電性連接墊之凹陷部中設有焊接材 料，又該介電層上之線路區域設有絕緣保 .該些線路上；半導體晶片，係具有一作用面，該作= 有複數導電凸塊，並藉由該焊接材料以對應電性連接該封 肇裝基板之電性連接墊與半導體晶片之導電凸塊；以及底 部填膠（underfill)，係設於該介電層及該半導體晶片之 間。 依上述之結構，復包括表面處理層，係設於該電性連 接塾之凹陷部與該悍接材料之間；該表面處理層係為錄/ 金W/Au)、鎳/把/金（Ni/Pd/Au)、銀（Ag)及金㈤之盆 中一者。 • 本發明之具電性連接結構之封裝基板及其半導體封 裝f構中，該電性連接墊之上表面具有凹陷部，使該半導 體晶片之導電凸塊對接在該凹陷部時得以縮小封裝體高 度；且該凹陷部與谭接材料之間具有較大的接觸面積，俾 =增加該塾與間的、象全教，以避免該 烊接材料產生脫落；又該焊接材料可不高於該絕緣保護 層之開孔’使該焊接材料經迴焊製程而電性連接該半導體 f片之導電凸塊得避免該焊接材料溢流而導致短路，進而 付縮小電性連接塾之間的間距；此外，可免除習知結構之 110478 10 1357141 ，導電元件的高度丑& 況’俾減少封裝體争晶片=致應力分佈不均的情況， 【實施方式:|化“ ▼靠度，避免影響產品的品質。 以下係藉由特定的具體實例說 式，熟悉此技藝之人+可山士上、 乃之声、鈀方 ^ , 本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 [第一實施例]1357141. EMBODIMENT OF THE INVENTION: TECHNICAL FIELD The present invention relates to a package substrate and a package substrate having an electrical connection structure and a semiconductor package thereof. [Prior Art] A structure. In the current 4亍 flip-chip (Flip Chid) dry supply. The semi-conducting field and the 1' in the integrated circuit (1C) of the cattle V-body sundial on the active surface of the electrode pad, and the corresponding electrode The electrical connection pad of the pad is also provided with a solder structure or other conductive adhesive material between the electrical connection pads of the electrode pads of the conductor chip, the solder structure or the conductive (4) (4) providing the semiconductor wafer With the electrical connection between the boards and the mechanical connection, the related art is shown in the illusion to 1G diagram. Firstly, a substrate body 1 is provided, which has an inner layer line, and a plurality of electrical connection pads 103'. The electrical connection layer 〇1〇3 is located on the surface of the dielectric layer 1〇2 covering the inner layer line 〇1, and the Electrically, the pad 103 is electrically connected to the inner layer line (8) by the conductive blind hole 104 as shown in FIG. 1A; then, an insulating protective layer such as an anti-mite layer is formed on the surface of the dielectric layer 1〇2. Forming a plurality of openings 11 相对 corresponding to the electrical connection pads 103 in the insulating protective layer n, as shown in FIG. 1B; then, on the upper surface of the insulating protective layer U, the opening n〇 side surface and the exposed surface A conductive layer 12 is formed on the upper surface of the electrical connection pad 1 3 of the opening 110, and then a resist layer 13 is formed on the upper surface of the conductive layer 12, and a plurality of openings 130 are formed in the resist layer 13 to correspondingly expose the opening. 11 and electrically connected to the conductive layer 12 on the surface of the crucible 103, as shown in Fig. 1 (: as shown in the figure; by the conductive layer 12 as the current conduction path of the electric ore to the opening of the resist layer 13 5110478 丄 33 /丄4丄: 130 medium electric iron forming system such as solder conductive system is electrically connected to the electrical connection (4) 1Q3, such as electricity to remove the resist layer 1 3 and its cover, two reeds, one after the shift, as in the 1ES - 'layer 12 to reveal the conductive material E picture; after that, after reflow (^_^丨 electric material 14 Melting into a series such as a solder ball guide-package substrate 1, as shown in the fourth (4)....14, 俾 to complete 2 = read 1G diagram 'The package base w has a first surface u and a surface: ib' The first surface 55 has the exposed conductive element 14 in the insulating layer 3, and the semiconductor layer 14 has an active surface 2a, and the active surface 2a has a plurality of opposite conductive bumps 21, so that the conductive element "When the conductive bump 2 is covered, the semiconductor wafer is connected to the substrate 1, and the bottom of the wafer is filled with a bottom fill (un(jer; fi 1 1 ) 23). The conductive element 14 is attached to the conductive element 14 by reflowing the conductive bump 21 of the semiconductor wafer 2 from the upper surface of the insulating protective layer n. Thereafter, the semiconductor wafer 2 and the package substrate The interval between the } is large, so that the height of the package cannot be reduced, and the purpose of the thin package cannot be achieved. In addition, the conductive element 14 is Forming the surface of the flat electrical connection pad 1〇3, so that the contact area between the conductive element 14 and the electrical connection pad 1〇3 is small. Therefore, the conductive element 14 is electrically connected. The bonding force between the three is weak, which causes the conductive element 14 to be easily detached. 110478 6 1357141 Moreover, the conductive element 14 of the package substrate protrudes from the surface of the insulating layer 4 and is spherical. After the conductive bump 21 of the semiconductor wafer 2 is brought into contact with the conductive element 14 and soldered back, in order to avoid the conductive elements 14, the short-circuit bridge occurs due to mutual contact in the melted state ((4) (4), The conductive elements 14 must be kept at a large distance between each other, so that the fine pitch cannot be achieved to increase the number of output/inputs. In addition, after the conductive material 14 is printed and reflowed to form the conductive element 14', the conductive element 14 has a low degree of coplanarity, and the conductive bump 21 of the semiconductor wafer 2 is reflowed with the conductive element 14'. After the docking, the joint of the package is broken or the contact is poor due to uneven stress distribution, thereby reducing the reliability and affecting the quality of the product. Therefore, how to provide a method for reducing the spacing between the package substrate and the semiconductor wafer to achieve a thin package, avoiding the dropping of the conductive member, and reducing the spacing between the electrical connections for fine pitch, and avoiding the conductive π The uneven distribution of stress caused by poor coplanarity has become an important issue in the industry. In view of the above-mentioned deficiencies of the prior art, one object of the present invention is to provide a package substrate having an electrical connection structure and a semiconductor package structure thereof, which can reduce the height of the package body to a thin package. structure. Another object of the present invention is to provide a package substrate having an electrical connection structure and a semiconductor package structure thereof, which can increase the bonding between the electrical connection pads and the solder material to prevent the solder material from falling off, and improve the 110478 7 1357141 • Reliability. Another purpose of the hairy month is to provide a ::: plate conductor, the structure, to avoid welding two = • and thus reduce the spacing between the electrical connection pads. Another object of the present invention is to provide an ugly package structure for a package substrate and a semiconductor enveloping device, and to avoid uneven distribution of stress caused by the high surface properties of the solder material. Happening. The present invention discloses a package substrate having an electrical connection structure, comprising: a substrate body having at least one surface, a layer and a plurality of electrical connection pads disposed therein, the electricity The connecting pad: the surface forms a recess and is not higher than the dielectric layer; the recess of the electrical connection pad is soldered; and the insulating material is material. And having a plurality of openings to correspondingly expose the solder according to the above structure, the opening of the insulating protective layer is the size of the connection; the surface includes a surface treatment layer, and the second zinc/gold or recess is provided with the solder material. The surface treatment layer is (5)^), koi gold (Nl/Pd/Au), silver (Ag), and gold (5)), and the solder material is extended to the periphery of the opening of the insulating protective layer. The surface; or, the tantalum material LI: is at, above, and below the upper surface of the dielectric layer, and is not high on the upper surface of the insulating layer. The "including the substrate body" has at least one surface having a dielectric layer and is disposed on its 110178 1357141: a plurality of electrical connection pads and lines, the upper surface of the electrical connection pads having a concave portion and not higher than The dielectric layer 'the upper surface of the lines is not higher than the dielectric layer, the bonding material is not in the recess of the electrical connection; and the insulating protective layer is disposed on the surface of the substrate a line region covering the upper surface of the circuit. According to the above structure, the surface treatment layer is further disposed between the recessed portion of the electrical connection pad and the solder material; the surface treatment layer is recorded/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au), silver (Ag), and gold (Au) straight one. ', the present invention provides a semiconductor package structure, including: package The substrate is provided with a dielectric layer on at least one surface of the substrate body, and a plurality of electrical connections are disposed in the dielectric layer, and the electrical connections are formed on the upper surface of the substrate and form a recess and are not higher than the dielectric Layer, in the concave (four) towel I have a splicing material and the dielectric layer 卩 welding material is insulated The protective layer 'the insulating layer has a plurality of openings to correspondingly expose the soldering material; the semiconductor crystal piece has an active surface, the active surface has a plurality of conductive bumps, and the material is matched by the tanned material Electrically connecting the electrical connection of the package substrate and the conductive bump of the conductor chip; and an underfill is disposed between the insulating protective layer and the semiconductor wafer. According to the above structure, the insulation protection The opening size of the layer is less than or greater than one of the dimensions of the electrical connection; the surface treatment layer is further disposed between the recess of the electrical connection and the solder material; the surface treatment layer, It is one of nickel/gold (8) 仏), nickel/kilo/gold (Ni/Pd/Au), silver (Ag), and gold (An). 110478 9 1357141 -: The present invention provides a semiconductor package structure The method includes a package base plate, a dielectric layer is disposed on at least one surface of the substrate body, and a plurality of electrical connection pads and lines are disposed in the dielectric layer, and the upper surface of the electrical connection pads has a recessed portion And not higher than the dielectric layer, the lines The upper surface is not addressed to the dielectric layer, and the soldering material is disposed in the recessed portions of the electrical connection pads, and the wiring region on the dielectric layer is provided with insulation protection. The semiconductor wafers are Having an active surface, the plurality of conductive bumps, and electrically connecting the electrical connection pads of the package substrate and the conductive bumps of the semiconductor wafer by the solder material; and underfilling the underfill Provided between the dielectric layer and the semiconductor wafer. According to the above structure, the surface treatment layer is further disposed between the recess of the electrical connection and the splicing material; the surface treatment layer It is one of the pots of gold/gold/handle/gold (Ni/Pd/Au), silver (Ag) and gold (five). • The package substrate and its semiconductor with electrical connection structure of the present invention In the package f structure, the upper surface of the electrical connection pad has a recessed portion, so that the conductive bump of the semiconductor wafer is docked in the recessed portion to reduce the height of the package; and the recessed portion and the tantalum material have a larger Contact area, 俾 = increase the 塾 and inter-, like the whole religion, Preventing the splicing material from falling off; and the soldering material may not be higher than the opening of the insulating protective layer, so that the soldering material is electrically connected to the conductive bump of the semiconductor f sheet through the reflow process to avoid overflow of the solder material The short circuit is caused, and the spacing between the electrical connections is reduced. In addition, the conventional structure 110478 10 1357141 can be dispensed with, and the height of the conductive element is ugly and the condition of the package is reduced. Situation, [Implementation: |化" ▼ depends on the degree to avoid affecting the quality of the product. The following is a specific example of a person skilled in the art, and can be easily understood by those skilled in the art, and can be easily understood by the contents disclosed in the present specification. [First Embodiment]
係詳細說明本發明之具電性連 導體封裝結構之第一實施例的 請參閱第2A至2F圖， 接結構之封裝基板及其半 衣法剖面不意圖。 如4 2A圖所示’首先提供具有内層線路撕之基板 本體30,於該基板本體3〇表面具有介電層3〇2及設於並 中之複數電性連接塾303,且該電性連接墊3〇3上表面^ 南於該介電層302上表面’較佳為與該介電層3〇2上表面 背平，又該些電性連接墊303以相對應之導電盲孔3〇4 電性連接該内層線路301;於該基板本體3〇之介電層3〇2 上形成一絕緣保護層31，且該絕緣保護層31中形成複數 對應該電性連接墊303之開孔310，且該開孔31〇之尺寸 係小於該電性連接墊303之尺寸，而為絕緣保護層所定義 電性連接墊（Solder Mask Defined Pad，SMD Pad)。 如第2B圖所示，該些電性連接墊303之上表面進行 飯刻製程，以於該電性連接塾303之上表面形成凹陷部 305。 110478 11 1357141 如第2C及2C圖所不，於各該電性連接塾3〇3之凹 陷部305中電鍍形成焊接材料34，該焊接材料％係齊平 於该介電層302上表面，或可低於該介電層302上表面（未 圖W，該焊接材料34係為錫（Sn)、鉛（pb)、銀（Ag)、鋼 (㈤、=(Zn)及叙㈤所組成群組之其中一者；第％，圖 =較於第2C圖之不同處，係於該電性連接塾綱之凹陷 T 305上依序形成表面處理層33及焊接材料^，該表面 理層33係、為錄/金（Ni/Au)、鎳繞/金⑻州/如、銀 (Ag)及金（Au)之其中一者。 另如第2D及2D’圖所示，於各該電性連接墊3〇3之 305中形成之桿接材料34係高於該介電層咖上 表面，且未高於該絕緣保護層31;第2 T同處’係於電性連接塾3。3之凹陷部3〇5上： 成表面處理層33及珲接材料34。 再如第2E及2E’圖所示’於各該電性連接墊3〇3之 ㈣部305中形成之焊接材料以復延伸至該絕緣保護層 孔310侧壁及其開孔31〇周緣之表面，·第2E，圖相 乂、’ 2E圖之不同處，係於電性連接墊3〇3之凹陷部加$ 上依序形成表面處理層33及焊接材料34 ^ 2明復提供-種具電性連接結構之封裝基板，係包 並中Γ 2體30 ’其至少一表面具有介電層302及設於 ”中之複數電性連接塾3〇3，該些電性連接塾·之上表 陷部305且未高於該介電層聽焊接材料34， 係故於各該電性連接塾303之凹陷部3〇5中；以及絕緣保 110478 12 1357141 :護f 3卜純於該介電層302及烊接材料34上，且且有 複數開孔3H)以對應顯露該些焊接 緣= 護層.31之開孔310尺寸係 H緣保 L j y、这電性連接墊303尺寸。 上述之結構中，該焊接材稱卩一 円所卞向度係高於(如第2D 圖所不)、齊平(如第2C圖所示)及 302上表面之1中一者，曰去古从、不圆丁 丨电層 表面；或者，該焊接材们4復延伸至該絕緣保護層31 之開孔310側壁及其開孔31〇周緣之表面(如第 示）0 依上述之結構，復包括表面處理層33，係設於該電 性連接塾303之凹陷部3G5與該焊接材料34之間（如第 2^’’2£，圖所*);該表面處理層33係為錦/全 W/Au)、錄/纪/金（Ni/Pd/Au)、銀（如及金（糾之复 一者。 請參閱第2F及2F，圖，本發明復提供一種半導體封 籲裝結構，係包括··封裝基板30,係於基板本體3〇之至少 一表面設有介電層302,且於該介電層3〇2中設有複數電 性連接墊303,該些電性連接墊3〇3之上表面並具有凹陷 部305且未南於該介電層302，於該凹陷部3〇5設有焊接 材料34,又該介電層302及焊接材料34上設有絕緣保護 層31，該絕緣保護層31中具有複數開孔31〇以對應顯露 該焊接材料34’且該絕緣保護層31之開孔31〇尺寸係小 於該電性連接墊303尺寸；半導體晶片4,係具有一作用 面4a，該作用面4a具有複數導電凸塊41 ’並藉由該焊接 Π0478 13 .材料34以對應電性連接該封裝基板3G之電性連接塾303 與半導_ S y θ 4之導電凸塊41;以及底部填膠 underfi 11)42,係設於該絕緣保護層31及該 4之間。 n 、依上述之結構，復包括表面處理層33,係設於該電 連接墊303之凹陷部3〇5與該焊接材料％之間該表 面處理層33係為錄/金（Ni/Au)、錄/纪/金⑻/pd/⑹、 銀（Ag)及金（au)之其中一者。 鲁[第二貫施例] 月，閱弟3A至3E圖，係詳細說明本發明之具電性連 2 構之封裝基板與製法之第二實施例的剖面示意圖，與 别一實施例之不同處在於該絕緣保護層開孔之尺寸係大 於該電性連接墊尺寸。 如第3A圖所示，首先提供係如第2A圖所示之結構， 不同處在於該絕緣保護層31中之開孔31〇，之尺寸係大於 鲁該電性連接墊303之尺寸，而為非絕緣保護層所定義電性 連接墊（Non Solder Mask Defined Pad, NSMD Pad)。 ^如第3B圖所示，於該些電性連接墊303之上表面進 行钱刻製程形成凹陷部305。 如第3C及3C’圖所示，於各該電性連接墊3〇3之凹 陷部305中以電鍍形成焊接材料34，該焊接材料^係齊 平於該介電層302上表面，或可低於該介電層3〇2上表面 (未圖示）；第3C，圖相較於第3C圖之不同處，係於該電 性連接墊303之凹陷部305上依序形成表面處理層犯及 110478 14 1357141 .，焊接材料3 4。 另如第3D及3D，冃私- 凹陷部305於各該電性連接墊3〇3之 未高於該絕緣保護3接材::34係高於該介電層302而 處，係於該電性連“ 〇3圖/目較於第3D圖之不同 處理層33及焊接材料34。之凹&部3°5上依序形成表面 凹陷:Γ〇Γφ3ΕΛ3Ε，圖所示，於各該電性連接塾303之 31 Imi q $成之焊接材料％復延伸至該絕緣保護層 3〇二依序二I】處’係於電性連接塾3〇3之凹陷部 序形成表面處理層33及焊接材料34。 [第三實施例] 叫參閱第4A至4C圖’係詳細說明本發 接結構之料基板及其半導體封裝結構與製法 =㈣面示意圖；與前述實施例之不同處在於該介二 層中復包括有線路。 如第4A圖所示，首先提供一係如第2八圖所示之結 構其中之基板本體3〇表面具有介電層3〇2及設於其中 之複數電性連接塾303與線路306，該些電性連接塾3〇3 及線路306之上表面係未高於該介電層302之上表面，較 佳為齊平該介電層302之上表面，以顯露該些電性連接墊 303及線路306之上表面；然後’形成絕緣保護層“於 該基板本體30表面之該線路3〇6區域’並覆蓋該路 306之上表面。 _ 110478 15 1357141 丄如第4B圖所示 成凹陷部305。 於該些電性連接墊303之上表面形 如第4C及4C，圖所示，於該電性連接塾之凹陷部3〇5 中電錢形成焊接材料34，其中該烊接材料以係為錫 (Sn)、錯⑽）、銀（Ag)、銅（Cu)、辞（Zn)及錢⑻）所組成 群組之其中一者；第4C’圖相較於第4C圖之不同處，係 於該電性連接塾303之凹陷部3〇5上依序形成表面處理層 33及焊接材料34’該表面處理層33係為錄/金（Ni/Au)、 鎳/鈀/金（Ni/Pd/Au)、銀（Ag)及金（Au)之其中一者。 本發明復提供一種具電性連接結構之封裝基板，如第 4C圖所示’係包括：基板本體3〇 ,其至少一表面具有介 電層302及設於其中之複數電性連接墊3〇3與線路細， 該些電性連接墊303之上表面具有凹陷部3〇5且未高於該 介電層3G2 ’該些線路3〇6之上表面係未高於該介電層 302;焊接材料34,係設於該些電性連接墊3〇3之凹陷部 305中；以及絕緣保護層31，係設於該基板本體3〇表面 之線路區域並覆蓋該些線路3〇6之上表面。 依上述之結構，復包括表面處理層33，如第4C，圖所 不，係設於該電性連接墊303之凹陷部3〇5與該焊接材料 34之間，該表面處理層33係為鎳/金（Ni/Au)、鎳/鈀/金 (Ni/Pd/Au)、銀（Ag)及金（au)之其中一者。 請參閱第4D圖，本發明復提供一種半導體封裝結 構，係包括：封裝基板30，係於基板本體3〇之至少一表 面設有介電層302’且於該介電層3〇2中設有複數電性連 110478 16 1357141 :接墊303與線路306，該些電性連接墊3〇3之上表面具 凹陷部=05且未高於該介電層3〇2，該些線路3〇6之^表 面係未高於該介電層302,且該些電性連接墊3〇3之凹p 部中設有焊择材料34，又該介電層3〇2上之線路‘ 域設有絕緣保護層31，以覆蓋在該些線路3〇6上；半 •體晶片4’係具有一作用面牦’該作用面钴具有複數導 電凸塊4丨’並藉由該焊接材料34以對應電性連接該封裳 基板30之電性連接墊3〇3與半導體晶片4之導電凸塊 ♦ 41;以及底部填膠（underfiu)42，係設於該介電 及該半導體晶片4之間。 - 清蒼閱第4D’圖，復包括表面處理層33,係設於該電 性連接墊303之凹陷部305與該焊接材料34間該表面 處理層33係為錄/金（Ni/Au)、鍊金（Ni/pd/Au)、銀 (Ag)及金（Au)之其中一者。 本發明之具電性連接結構之封裝基板及其半導體封 φ裝結構，該電性連接塾303之上表面具有凹陷部3〇5，使 該半導體晶片4之導電凸塊41得對接在該凹陷部咖 中’俾以縮小封裝體高度；且該電性連接塾303之凹陷部 3〇5與焊接材料34之間具有較大的接觸面積，俾以增加 該電性連接塾303與谭接材料34之間的結合性，以避免 ，焊接材料34脫落；又該焊接材料34可不高於該絕緣保 護層31之開孔310，使該焊接材料34經迴焊製程而電性 該半導體晶片4之導電凸塊41得避免該谭接材料料 /皿机而導致短路，進而得縮小電性連接墊3⑽之間的間 Π 0478 17 1357141 距，以達細間距並增加輸出/輸入（Input/〇utput)接點數 之目的；此外，該焊接材料之高度共面性佳，而可免除習 知結構之應力分佈不均的情況，俾減少封裝體中晶片端之 凸塊承受來自基板絕緣保護層之應力，故本發明可提高產 品可靠度。 间 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及料下，對上述實施例進行修飾盘改 變。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。 【圖式簡單說明】 第1A及1G圖係為習知覆晶式封裝基板之製法示意 圖； ’ 第W圖係為本發明第—實施例之舰示意圖； 第2C’圖係為第2C圖的另—實施態樣剖視示意圖； 第2D’圖係為第2D圖的另一實施態樣剖視示意圖； 第2E’圖係為第2E圖的另—實施態樣剖視示意圖； 第2F，圖係為第2F圖的另—實施態樣剖視示意圖； 第3A至3E圖係為本發明之第二實施例之剖視示意 第3C’圖係為第3C圖的另—實施態樣剖視示意圖 第3D’圖係為第3D圖的另一實施態樣剖視示意圖 第3Γ圖係為第3E圖的另1施態樣剖視示意圖， 第4A至4D圖係為本發明之第三實施例之剖視示意 110478 18 1357141 圖； 第4C’圖係為第4C圖的另一實施態樣剖視示意圖 以及 第4D’圖係為第4D圖的另一實施態樣剖視示意圖 【主要元件符號說明】 -1 封裝基板 la 第一表面 lb 第二表面 • 10,30 基板本體 101,301 内層線路 1 02, 302 介電層 103,303 電性連接墊 104,304 導電盲孔 11,31 絕緣保護層 110, 310, 310, 開孔 12 導電層 * 13 阻層 130 開口 14 導電材料 14’ 導電元件 2, 4 半導體晶片 ’ 2a, 4a 作用面 21, 41 導電凸塊 23, 42 底部填膠 19 110478 1357141 305 306 33 凹陷砉p 線路 表面處理層 焊接材料 34DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the first embodiment of the electrically conductive connector package structure of the present invention, please refer to Figs. 2A to 2F, and the package substrate of the connection structure and its half-coating cross-section are not intended. As shown in FIG. 4A, a substrate body 30 having an inner layer tearing is provided. The substrate body 3 has a dielectric layer 3〇2 and a plurality of electrical connections 303 disposed in the center, and the electrical connection is provided. The upper surface of the pad 3〇3 is disposed on the upper surface of the dielectric layer 302, preferably opposite to the upper surface of the dielectric layer 3〇2, and the electrical connection pads 303 are corresponding to the conductive blind holes 3〇. 4 is electrically connected to the inner layer line 301; an insulating protective layer 31 is formed on the dielectric layer 3〇2 of the substrate body 3, and a plurality of openings 310 corresponding to the electrical connection pads 303 are formed in the insulating protective layer 31. The size of the opening 31 is smaller than the size of the electrical connection pad 303, and is defined as a Solder Mask Defined Pad (SMD Pad). As shown in FIG. 2B, the upper surface of the electrical connection pads 303 is subjected to a rice etching process to form a recess 305 on the upper surface of the electrical connection port 303. 110478 11 1357141 as shown in FIGS. 2C and 2C, a solder material 34 is formed in the recess 305 of each of the electrical connections ,3〇3, and the solder material % is flush with the upper surface of the dielectric layer 302, or It may be lower than the upper surface of the dielectric layer 302 (not shown, the solder material 34 is composed of tin (Sn), lead (pb), silver (Ag), steel ((5), = (Zn), and (5) One of the groups; the %, the figure = the difference from the 2C figure, the surface treatment layer 33 and the solder material ^ are sequentially formed on the recess T 305 of the electrical connection skeleton, and the surface layer 33 It is one of the recording/gold (Ni/Au), nickel winding/gold (8) state/ruth, silver (Ag) and gold (Au). As shown in Figures 2D and 2D', each of the electricity The rod bonding material 34 formed in the 305 of the connection pad 3 is higher than the upper surface of the dielectric layer and is not higher than the insulating protection layer 31; the second T is the same as the electrical connection 塾3. On the recessed portion 3〇5 of 3: the surface treatment layer 33 and the splicing material 34. Further, as shown in Figs. 2E and 2E', the solder material formed in the (four) portion 305 of each of the electrical connection pads 3〇3 Extending to the side of the insulating protective layer hole 310 And the surface of the periphery of the opening 31〇, · 2E, the difference between the figure and the '2E figure, the surface treatment layer 33 and the welding material are sequentially formed on the depressed portion of the electrical connection pad 3〇3 34 ^ 2 Ming Fu provides - a package substrate with an electrical connection structure, the package and the middle body 2 body 30 ' at least one surface thereof has a dielectric layer 302 and a plurality of electrical connections 设 3 〇 3 disposed in the The electrical connections 之上·the upper surface trap 305 and not higher than the dielectric layer soldering material 34 are in the recesses 3〇5 of each of the electrical connections 303; and the insulation 110478 12 1357141 The protective f 3 is pure on the dielectric layer 302 and the splicing material 34, and has a plurality of openings 3H) to correspondingly expose the soldering edges = the opening 310 of the protective layer 31. The size of the electrical connection pad 303. In the above structure, the welding material is said to have a higher degree of orientation than (as shown in FIG. 2D), flush (as shown in FIG. 2C), and upper surface of 302. In one of the first, the surface of the electric layer is not rounded; or the welding material 4 is extended to the side wall of the opening 310 of the insulating protective layer 31 and the opening 31 thereof The surface (as shown) 0, according to the above structure, includes a surface treatment layer 33 disposed between the recessed portion 3G5 of the electrical connection port 303 and the solder material 34 (eg, 2^''2£, Figure *); the surface treatment layer 33 is jin / full W / Au), recorded / Ji / gold (Ni / Pd / Au), silver (such as and gold (resolved one. See 2F and 2F, the present invention provides a semiconductor package accommodating structure, comprising: a package substrate 30, is provided on at least one surface of the substrate body 3 is provided with a dielectric layer 302, and in the dielectric layer 3 〇 2 a plurality of electrical connection pads 303 are disposed, and the upper surface of the electrical connection pads 3〇3 has a recess 305 and is not souther than the dielectric layer 302. The soldering material 34 is disposed on the recessed portion 3〇5. An insulating protective layer 31 is disposed on the dielectric layer 302 and the soldering material 34. The insulating protective layer 31 has a plurality of openings 31 〇 corresponding to the exposed solder material 34 ′ and the opening 31 〇 dimension of the insulating protective layer 31 . Less than the size of the electrical connection pad 303; the semiconductor wafer 4 has an active surface 4a having a plurality of conductive bumps 41' and by the solder Π 0478 13 . 4 is electrically connected to the electrical connection 塾 303 of the package substrate 3G and the conductive bump 41 of the semiconductor _ S y θ 4; and the underfill underfigure 11) 42 is disposed on the insulating protective layer 31 and the 4 between. According to the above structure, the surface treatment layer 33 is provided between the recessed portion 3〇5 of the electrical connection pad 303 and the solder material%, and the surface treatment layer 33 is recorded/gold (Ni/Au). One of the records/records/gold (8)/pd/(6), silver (Ag) and gold (au). Lu [Second Embodiment] Month, Reading Brothers 3A to 3E, is a schematic cross-sectional view showing a second embodiment of the package substrate and the manufacturing method of the present invention, which is different from the other embodiments. The size of the opening of the insulating protective layer is larger than the size of the electrical connecting pad. As shown in FIG. 3A, the structure shown in FIG. 2A is first provided, except that the opening 31〇 in the insulating protective layer 31 is larger than the size of the electrical connection pad 303. Non-insulated protective layer defined by the Non Solder Mask Defined Pad (NSMD Pad). As shown in Fig. 3B, a recessed portion 305 is formed on the upper surface of the electrical connection pads 303. As shown in FIGS. 3C and 3C', a solder material 34 is formed in the recess 305 of each of the electrical connection pads 3〇3, and the solder material is flush with the upper surface of the dielectric layer 302, or Lower than the upper surface of the dielectric layer 3〇2 (not shown); 3C, the difference from the 3C figure, the surface treatment layer is sequentially formed on the recess 305 of the electrical connection pad 303. Made of 110478 14 1357141 ., welding material 3 4. In addition, in the 3D and 3D, the smear-recessed portion 305 is not higher than the insulating protection 3 bonding material 3:3 is higher than the dielectric layer 302. The electrical connection "〇3图/目 is different from the different treatment layer 33 and the welding material 34 of the 3D drawing. The concave & portion 3°5 sequentially forms a surface depression: Γ〇Γφ3ΕΛ3Ε, as shown in the figure, The electrical connection 塾303 of 31 Imi q $ into the solder material % is extended to the insulating protective layer 3 〇 2 sequentially 2 I] at the recessed portion of the electrical connection 塾 3 〇 3 to form the surface treatment layer 33 And the welding material 34. [Third Embodiment] Referring to Figures 4A to 4C, a detailed description of the material substrate of the present invention and its semiconductor package structure and manufacturing method = (four) plane view; the difference from the foregoing embodiment lies in The second layer includes a circuit. As shown in FIG. 4A, a structure as shown in FIG. 2 is first provided, wherein the substrate body 3 has a dielectric layer 3〇2 and a plurality of electrodes disposed therein. The connection 塾303 and the line 306, the upper surface of the electrical connection 塾3〇3 and the line 306 is not higher than the upper surface of the dielectric layer 302, Preferably, the upper surface of the dielectric layer 302 is flushed to expose the upper surface of the electrical connection pads 303 and the line 306; and then the insulating protective layer is formed on the surface of the substrate body 30. And covering the upper surface of the road 306. _ 110478 15 1357141 As shown in Fig. 4B, a recess 305 is formed. The surface of the electrical connection pads 303 is shaped like the 4C and 4C, and the electric money is formed in the recessed portion 3〇5 of the electrical connection to form the solder material 34, wherein the splicing material is One of the groups consisting of tin (Sn), wrong (10), silver (Ag), copper (Cu), vocabulary (Zn), and money (8); the 4C' map is different from the 4C diagram, The surface treatment layer 33 and the solder material 34' are sequentially formed on the recessed portion 3〇5 of the electrical connection port 303. The surface treatment layer 33 is recorded/gold (Ni/Au), nickel/palladium/gold (Ni One of /Pd/Au), silver (Ag) and gold (Au). The present invention provides a package substrate having an electrical connection structure, as shown in FIG. 4C, which includes a substrate body 3 having at least one surface having a dielectric layer 302 and a plurality of electrical connection pads 3 disposed therein. 3 and the line is thin, the upper surface of the electrical connection pad 303 has a recess 3 〇 5 and is not higher than the dielectric layer 3G2 'the upper surface of the line 3 〇 6 is not higher than the dielectric layer 302; The soldering material 34 is disposed in the recess 305 of the electrical connection pads 3〇3; and the insulating protective layer 31 is disposed on the line region of the surface of the substrate body 3 and covers the lines 〇6 surface. According to the above structure, the surface treatment layer 33 is further provided, as shown in FIG. 4C, which is disposed between the recessed portion 3〇5 of the electrical connection pad 303 and the solder material 34, and the surface treatment layer 33 is One of nickel/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au), silver (Ag), and gold (au). Referring to FIG. 4D, the present invention further provides a semiconductor package structure, comprising: a package substrate 30, wherein a dielectric layer 302' is disposed on at least one surface of the substrate body 3, and is disposed in the dielectric layer 3? There is a plurality of electrical connections 110478 16 1357141: pads 303 and lines 306, the upper surface of the electrical connection pads 3〇3 has a recessed portion=05 and is not higher than the dielectric layer 3〇2, the lines 3〇 The surface of the circuit is not higher than the dielectric layer 302, and the solder material 34 is disposed in the concave p portion of the electrical connection pads 3〇3, and the line on the dielectric layer 3〇2 is set. An insulating protective layer 31 is provided to cover the lines 3〇6; the half body wafer 4' has an active surface 牦' the active surface cobalt has a plurality of conductive bumps 4丨' and is formed by the solder material 34 Corresponding to the electrical connection pads 3 〇 3 electrically connected to the sealing substrate 30 and the conductive bumps ♦ 41 of the semiconductor wafer 4; and an underfill 42 disposed between the dielectric and the semiconductor wafer 4 . - The 4D' image of the Qing Cang, including the surface treatment layer 33, is disposed between the recess 305 of the electrical connection pad 303 and the solder material 34. The surface treatment layer 33 is recorded/gold (Ni/Au). One of chain gold (Ni/pd/Au), silver (Ag) and gold (Au). The package substrate with the electrical connection structure and the semiconductor package structure of the present invention have a recessed portion 3〇5 on the upper surface of the electrical connection layer 303, so that the conductive bumps 41 of the semiconductor wafer 4 are butted in the recess In the ministry, the height of the package is reduced; and the recessed portion 3〇5 of the electrical connection 303 has a large contact area with the solder material 34, so as to increase the electrical connection 塾303 and the tantalum material. The bonding between the 34 to avoid the soldering material 34 falling off; the soldering material 34 may not be higher than the opening 310 of the insulating protective layer 31, so that the soldering material 34 is electrically reflowed to electrically the semiconductor wafer 4 The conductive bumps 41 are prevented from causing a short circuit by the material of the tandem material, thereby reducing the distance between the electrical connection pads 3 (10) by 0478 17 1357141 to achieve fine pitch and increase the output/input (Input/〇utput The purpose of the number of contacts; in addition, the solder material has a high degree of coplanarity, and the stress distribution of the conventional structure is eliminated, and the bump of the wafer end in the package is reduced from the substrate insulating protective layer. Stress, so the invention Improve the reliability of the product. The above embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1G are schematic diagrams of a conventional flip-chip package substrate; 'the W diagram is a schematic diagram of the ship of the first embodiment of the present invention; and the 2C' diagram is the 2C diagram. FIG. 2D' is a schematic cross-sectional view showing another embodiment of FIG. 2D; FIG. 2E' is a cross-sectional view of another embodiment of FIG. 2E; Figure 2 is a cross-sectional view showing another embodiment of the second embodiment; Figs. 3A to 3E are cross-sectional views showing a second embodiment of the present invention, and the third embodiment is a third embodiment of the third embodiment. 3D' is a cross-sectional view of another embodiment of FIG. 3D. FIG. 3 is a cross-sectional view of another embodiment of FIG. 3E, and FIGS. 4A to 4D are the third embodiment of the present invention. FIG. 4C is a cross-sectional view showing another embodiment of FIG. 4C and FIG. 4D' is a cross-sectional view showing another embodiment of FIG. 4D. Component symbol description] -1 package substrate la first surface lb second surface • 10,30 substrate body 101, 301 inner layer line 1 02, 302 dielectric layer 103, 303 electrical connection pad 104, 304 conductive blind hole 11, 31 insulating protective layer 110, 310, 310, opening 12 conductive layer * 13 resist layer 130 opening 14 conductive material 14' conductive element 2, 4 semiconductor Wafer ' 2a, 4a active surface 21, 41 conductive bump 23, 42 underfill 19 110478 1357141 305 306 33 recessed 砉p line surface treatment layer solder material 34