CN104766837A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN104766837A
CN104766837A CN201410009411.7A CN201410009411A CN104766837A CN 104766837 A CN104766837 A CN 104766837A CN 201410009411 A CN201410009411 A CN 201410009411A CN 104766837 A CN104766837 A CN 104766837A
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CN
China
Prior art keywords
electric connection
connection pad
semiconductor package
conductive pole
chip
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CN201410009411.7A
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English (en)
Inventor
江政嘉
江东昇
王隆源
童世豪
黄淑惠
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN104766837A publication Critical patent/CN104766837A/zh
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  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种半导体封装件及其制法，该半导体封装件包括：具有相对的第一表面及第二表面、多个第一电性连接垫及多个第二电性连接垫的封装基板，而该第一电性连接垫及第二电性连接垫形成于该第一表面上；具有相对的作用面与非作用面的芯片，用于以其作用面覆晶接置于该第一电性连接垫上；形成于该第二电性连接垫上的导电柱；以及形成于该第一表面上，并包覆该芯片及该导电柱，且具有外露该导电柱的顶面的开孔的第一封装胶体。本发明能提高封装件的密度及防止芯片及互连结构受到水气入侵的影响。

Description

半导体封装件及其制法
技术领域
本发明提供一种半导体封装件及其制法，尤指一种具有导电柱的半导体封装件及其制法。
背景技术
近年来，由于各种电子产品在尺寸上是日益要求轻、薄及小，因此可节省基板平面面积并可同时兼顾处理性能的堆栈式封装件（package on package，PoP）愈来愈受到重视。
现有的堆栈式封装件是使用焊球来作为底层封装基板与上层电子组件之间的电性连接用途的互连结构(interconnection)，然而，为了避免回焊时的桥接问题，作为互连结构的焊球之间的间距通常大于300微米，因此互连结构占用过大的基板面积，从而局限了封装件的输入/输出(I/O)的电性连接密度。
此外，由于作为互连结构的焊球互连结构需要较底封装件上的芯片为高的高度，因此也使现有堆栈式封装件的高度无法减低，从而令使用现有堆栈式封装件的电子装置的厚度无法更进一步降低。
此外，现有堆栈式封装件的底层封装基板与上层电子组件之间并未形成封装胶体，故连接在底层封装基板上的芯片及互连结构无法受到封装胶体的保护，从而容易遭到水气入侵。
因此，如何克服现有堆栈式封装件互连结构的输入/输出(I/O)密度无法进一步提高及封装件厚度无法进一步降低的问题，以及如何解决现有堆栈式封装件的底层封装基板上的芯片及互连结构未受到封装胶体的保护的问题，实为本领域技术人员的一大课题。
发明内容
有鉴于上述现有技术的缺失，本发明提供一种半导体封装件及其制法，能提高封装件的密度及防止芯片及互连结构受到水气入侵的影响。
本发明的半导体封装件包括：具有相对的第一表面及第二表面、多个第一电性连接垫及多个第二电性连接垫的封装基板，而该第一电性连接垫及第二电性连接垫形成于该第一表面上；具有相对的作用面与非作用面的芯片，用于以其作用面覆晶接置于该第一电性连接垫上；形成于该第二电性连接垫上的导电柱；以及形成于该第一表面上，并包覆该芯片及该导电柱，且具有外露该导电柱的顶面的开孔的第一封装胶体。
本发明另提供一种半导体封装件的制法，包括：提供一封装基板，该封装基板具有相对的第一表面及第二表面、多个第一电性连接垫及第二电性连接垫，而该第一电性连接垫及第二电性连接垫形成于该第一表面上；将导电柱在各该第二电性连接垫上形成；以覆晶方式将具有相对的作用面与非作用面的芯片的作用面接置在该第一电性连接垫上；在该第一表面上形成第一封装胶体，以包覆该芯片及该导电柱；以及从该第一封装胶体的顶面移除部分厚度的该第一封装胶体及其内的该导电柱，使该第一封装胶体的顶面及该导电柱的顶面齐平于该芯片的非作用面。
本发明另提供另一种半导体封装件的制法，包括：提供一封装基板，该封装基板具有相对的第一表面及第二表面、多个第一电性连接垫及第二电性连接垫，而该第一电性连接垫及第二电性连接垫形成于该第一表面上；在各该第二电性连接垫上形成导电柱；将具有相对的作用面与非作用面的芯片的作用面以覆晶方式接置在该第一电性连接垫上；在该第一表面上形成第一封装胶体，以包覆该芯片及该导电柱；以及在该第一封装胶体的顶面形成开孔以露出该导电柱的顶面。
本发明的半导体封装件可藉由使用导电柱作为堆栈式封装件的互连结构并使封装胶体的顶面及导电柱的顶面齐平于芯片的非作用面，而避免以现有的焊球来作为堆栈式封装件的互连结构所造成的密度无法进一步提高及厚度无法进一步降低的问题，并节省基板平面面积，另外，本发明的半导体封装件可藉由在底层封装基板与上层电子组件之间形成封装胶体而保护芯片及互连结构不受水气入侵的影响。
附图说明
图1A至图1G为本发明的半导体封装件的制法的剖视图。
图1F＇与图1G＇分别为图1F与图1G的另一实施例的剖视图。
图1D＂及图1G＂分别为图1D及图1G的又一实施例的剖视图。
主要组件符号说明
10     封装基板
10a    第一表面
10b    第二表面
20     芯片
20a    作用面
20b    非作用面
30     电子组件
40     第二封装胶体
100    第一电性连接垫
102    第二电性连接垫
104    导电柱
106    底胶
108    第一封装胶体
108a   开孔
110    表面处理层
112    绝缘保护层
112a   绝缘保护层开孔
114    导电通孔
116    第三电性连接垫
118    防焊层
118a   开口
120    焊球
200    铜柱
202    焊料
300    导电组件。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。本发明也可藉由其它不同的具体实施例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不悖离本发明的精神下进行各种修饰与变更。
首先请参照图1A至图1G，该等图为本发明的半导体封装件的制法的剖视图，其中，该半导体封装件的制法的各步骤将参照各图而于以下详细说明。
请参照图1A，首先，提供一封装基板10，而封装基板10具有相对的第一表面10a及第二表面10b、多个第一电性连接垫100及第二电性连接垫102，而第一电性连接垫100及第二电性连接垫102形成于该第一表面10a上。在本实施例的另一范例中，封装基板10还包括导电通孔114及第三电性连接垫116，其中，第三电性连接垫116形成于第二表面10b上，并且导电通孔114位于第二电性连接垫102及第三电性连接垫116之间且贯穿封装基板10，以使第二电性连接垫102及第三电性连接垫116电性连接。此外，第二表面10b上可形成有防焊层118，且防焊层118具有开口118a以露出第三电性连接垫116。
请参照图1B，其次，在各第二电性连接垫102上形成导电柱104，其材料为铜，但本发明不限于此。
请参照图1C，此外，将具有相对的作用面20a与非作用面20b的芯片20的作用面20a以覆晶方式接置在第一电性连接垫100上；此时，该导电柱104的顶面可高于该非作用面20b，但不以此为限，详细而言，在本实施例的一范例中，芯片20藉由在作用面20a上的铜柱200上的焊料202而以例如为回焊的方式来使焊料202电性连接第一电性连接垫100，从而令芯片20覆晶接置于第一电性连接垫100上。另外，可在覆晶接置芯片20后，于芯片20与封装基板10之间形成底胶106，以包覆第一电性连接垫100、焊料202及铜柱200。
请参照图1D，而后，在第一表面20a上形成第一封装胶体108，以包覆芯片20及导电柱104。
请参照图1E，随后，从第一封装胶体108的顶面移除部分厚度的第一封装胶体108及其内的导电柱104至一预定厚度，使第一封装胶体108的顶面、导电柱104的顶面及芯片20的非作用面20b为互相齐平，且移除部分厚度的该第一封装胶体108还可包括移除部分厚度的该芯片20。而移除的方法可为刷磨或研磨，但本发明不限于此，并且移除导电柱104和芯片20的何者为视导电柱104和芯片20的何者的顶面高于该预定厚度而定。另外，本发明可在此步骤中于第一封装胶体108上形成绝缘保护层，且该绝缘保护层具有绝缘保护层开孔，以露出导电柱104的顶面(未图标此情况)。
请参照图1F，之后，再从导电柱104的顶面移除部分厚度的导电柱104，以使导电柱104的顶面低于芯片20的非作用面20b，而移除的方法可为蚀刻，但本发明不限于此。另外，在本实施例中，可在导电柱104的顶面上形成表面处理层110，且可在开口118a中将焊球120形成或接置在第三电性连接垫116上。
请参照图1G，最后，在导电柱104上接置电子组件30，而电子组件30藉由其上的多个导电组件300电性连接导电柱104，并且于第一封装胶体108上形成第二封装胶体40，以包覆电子组件30。
请参照图1F＇及图1G＇，该等图分别为图1F及图1G的另一实施例的剖视图，而本实施例与图1F及图1G的差异在于本实施例的导电柱104的顶面与芯片20的非作用面20b齐平。
图1F＇及图1G＇的制法先在导电柱104的顶面上形成表面处理层110，再于芯片20的非作用面20b及第一封装胶体108上形成绝缘保护层112，并在绝缘保护层112中形成绝缘保护层开孔112a，以露出导电柱104，或者，可先于芯片20的非作用面20b及第一封装胶体108上形成绝缘保护层112，并在绝缘保护层112中形成绝缘保护层开孔112a，以露出导电柱104，再于导电柱104的顶面上形成表面处理层110。之后，再如以上图1G所述的内容地在导电柱104上接置电子组件30，以及在绝缘保护层112上形成包覆电子组件30的第二封装胶体40，从而形成如图1G＇的半导体封装件。
请参照图1D＂及图1G＂，该等图分别为图1D及图1G的又一实施例的剖视图，而本实施例与图1D及图1G的差异在于本实施例的导电柱104及第一封装胶体108的顶面高于芯片20的非作用面20b，且图1D＂的第一封装胶体108的顶面具有露出导电柱104的顶面的开孔108a。
详而言之，图1D＂及图1G＂的制法中，导电柱104的顶面高于芯片20的非作用面20b，而在如图1D所述的形成第一封装胶体108之后，再于第一封装胶体108的顶面形成开孔108a以露出导电柱104的顶面。之后，可在导电柱104的顶面上形成表面处理层110。最后，再如以上图1G所述的内容地在导电柱104上接置电子组件30，以及在第一封装胶体108上形成包覆电子组件30的第二封装胶体40，从而形成如图1G＂的半导体封装件。另外，本实施例也可于第一封装胶体108上形成绝缘保护层，且该绝缘保护层具有绝缘保护层开孔，以露出导电柱104的顶面(未图标此情况)，此时第二封装胶体40形成在该绝缘保护层上。
本发明的半导体封装件的剖视图如图1G所示，其中，该半导体封装件包括封装基板10、芯片20、导电柱104及第一封装胶体108，而为了清楚了解本发明起见，该半导体封装件的结构及各组件将于以下详细说明。
如上所述的封装基板10具有相对的第一表面10a及第二表面10b、多个第一电性连接垫100及多个第二电性连接垫102，而第一电性连接垫100及第二电性连接垫102形成于第一表面10a上，而本实施例的一范例中，第一电性连接垫100及第二电性连接垫102可嵌埋于第一表面10a并外露于第一表面10a(未图标此情况)。而本实施例的另一范例中，封装基板10还包括导电通孔114及第三电性连接垫116，其中，第三电性连接垫116形成于第二表面10b上，在此范例中，第三电性连接垫116可嵌埋于第二表面10b并外露于第二表面10b(未图标此情况)，并且导电通孔114位于第二电性连接垫102及第三电性连接垫116之间，且贯穿封装基板10，以使第二电性连接垫102及第三电性连接垫116电性连接。此外，第二表面10b上可形成有防焊层118，且防焊层118具有开口118a以露出第三电性连接垫116，再者，可在开口118a中将焊球120形成或接置在第三电性连接垫116上。
如上所述的芯片20具有相对的作用面20a与非作用面20b，且以其作用面20a覆晶接置于第一电性连接垫100上，详细而言，在本实施例的一范例中，芯片20的作用面20a上具有铜柱200，而铜柱200上形成有焊料202，因此，芯片20藉由例如为回焊的方式而使焊料202电性连接第一电性连接垫100，从而令芯片20覆晶接置于第一电性连接垫100上。
如上所述的导电柱104，其材料为铜，但本发明不限于此，而导电柱104形成于第二电性连接垫102上，且导电柱104的顶面低于芯片20的非作用面20b，而在此实施例中，导电柱104的顶面上可形成有表面处理层110。
如上所述的第一封装胶体108形成于第一表面10a上，并包覆芯片20及导电柱104，且具有外露导电柱104的顶面的开孔108a，而在导电柱104的顶面上形成有表面处理层110的范例中，该开孔108a外露表面处理层110。另外，在本实施例的一范例中，芯片20与封装基板10之间可形成有底胶（underfill）106，以包覆第一电性连接垫100、焊料202及铜柱200。
在本发明的实施例中，该半导体封装件还包括电子组件30、多个导电组件300及第二封装胶体40，其中，电子组件30可为半导体芯片或封装结构，但本发明不限于此，而导电组件300形成或接置在电子组件30上，并且电子组件30藉由其上的多个导电组件300电性连接导电柱104，而第二封装胶体40形成于第一封装胶体108上，以包覆电子组件30。
另外，本发明可于第一封装胶体108上形成绝缘保护层，且该绝缘保护层具有绝缘保护层开孔，以露出导电柱104的顶面(未图标此情况)，此时第二封装胶体40形成在该绝缘保护层上。
本发明的半导体封装件的另一实施例的剖视图为如图1G＇所示，其中，该半导体封装件与图1G中的半导体封装件的差异在于本实施例的导电柱104的顶面齐平于芯片20的非作用面20b。在此情况下，本实施例的一范例可在芯片20及第一封装胶体108上形成有绝缘保护层112，且绝缘保护层112具有绝缘保护层开孔112a，以露出导电柱104，另外，第二封装胶体40则形成于绝缘保护层112上，以包覆电子组件30，而绝缘保护层112可例如为防焊材料所形成的层，但本发明不限于此。并且，在此实施例中，导电柱104的顶面上可形成有表面处理层110。
本发明的半导体封装件的另一实施例的剖视图为如图1G＂所示，其中，该半导体封装件与图1G中的半导体封装件的差异在于本实施例的导电柱104的顶面及第一封装胶体108的顶面高于芯片20的非作用面20b。在此实施例中，导电柱104的顶面上可形成有表面处理层110，且表面处理层110的顶面齐平或低于第一封装胶体108的顶面。另外，本实施例也可于第一封装胶体108上形成绝缘保护层，且该绝缘保护层具有绝缘保护层开孔，以露出导电柱104的顶面(未图标此情况)，此时第二封装胶体40形成在该绝缘保护层上。
综上所述，相较于先前技术，由于本发明藉由在底层封装基板与上层电子组件之间形成封装胶体以保护芯片及互连结构不受水气入侵的影响。另外，由于本发明藉由将第一封装胶体与导电柱的部份厚度移除，或者，本发明藉由将第一封装胶体、导电柱及芯片的部份厚度移除，以使第一封装胶体的顶面及导电柱的顶面齐平于芯片的非作用面，从而使本发明的半导体封装件可具有更薄的厚度，此外，由于本发明使用了导电柱来作为封装基板与电子组件之间的互连结构，从而可使本发明的互连结构较先前技术中以焊球所作成的互连结构具有更低的高度并具有更小的间距，从而使半导体封装件可具有较先前技术中的半导体封装件更薄的厚度及更高密度的输入/输出(I/O)。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (26)

1.一种半导体封装件，包括：
封装基板，其具有相对的第一表面及第二表面、多个第一电性连接垫及多个第二电性连接垫，而该第一电性连接垫及第二电性连接垫形成于该第一表面上；
具有相对的作用面与非作用面的芯片，用于以其作用面覆晶接置于该第一电性连接垫上；
导电柱，其形成于该第二电性连接垫上；以及
第一封装胶体，其形成于该第一表面上，并包覆该芯片及该导电柱，且具有外露该导电柱的顶面的开孔。
2.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括电子组件及其上的多个导电组件，该电子组件藉由该导电组件电性连接该导电柱。
3.根据权利要求2所述的半导体封装件，其特征在于，该电子组件为半导体芯片或封装结构。
4.根据权利要求2所述的半导体封装件，其特征在于，该半导体封装件还包括第二封装胶体，其形成于该第一封装胶体上，以包覆该电子组件。
5.根据权利要求1所述的半导体封装件，其特征在于，该导电柱的材料为铜。
6.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括导电通孔及第三电性连接垫，该第三电性连接垫形成于该第二表面上，而该导电通孔位于该第二电性连接垫及该第三电性连接垫之间且贯穿该封装基板，以电性连接该第二电性连接垫及该第三电性连接垫。
7.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括表面处理层，其形成在该导电柱的顶面上。
8.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括绝缘保护层，其形成在该芯片及该第一封装胶体上方，并具有绝缘保护层开孔，以露出该导电柱。
9.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括底胶，其形成于该芯片与封装基板之间。
10.一种半导体封装件的制法，其包括：
提供一封装基板，该封装基板具有相对的第一表面及第二表面、多个第一电性连接垫及第二电性连接垫，而该第一电性连接垫及第二电性连接垫形成于该第一表面上；
在各该第二电性连接垫上形成导电柱；
将具有相对的作用面与非作用面的芯片的作用面以覆晶方式接置在该第一电性连接垫上；
在该第一表面上形成第一封装胶体，以包覆该芯片及该导电柱；以及
从该第一封装胶体的顶面移除部分厚度的该第一封装胶体及其内的该导电柱，使该第一封装胶体的顶面及该导电柱的顶面齐平于该芯片的非作用面。
11.根据权利要求10所述的半导体封装件的制法，其特征在于，于使该第一封装胶体的顶面及该导电柱的顶面齐平于该芯片的非作用面之后，该制法还包括：
从该导电柱的顶面移除部分厚度的该导电柱；
在该导电柱上接置电子组件，而该电子组件藉由其上的多个导电组件电性连接该导电柱；以及
于该第一封装胶体上形成第二封装胶体，以包覆该电子组件。
12.根据权利要求11所述的半导体封装件的制法，其特征在于，在接置该电子组件之前，还包括将表面处理层形成在该导电柱的顶面上。
13.根据权利要求10所述的半导体封装件的制法，其特征在于，于使该第一封装胶体的顶面及该导电柱的顶面齐平于该芯片的非作用面之后，还包括在该芯片及该第一封装胶体上形成绝缘保护层，而该绝缘保护层具有绝缘保护层开孔，以露出该导电柱。
14.根据权利要求11所述的半导体封装件的制法，其特征在于，该电子组件为半导体芯片或封装结构。
15.根据权利要求10所述的半导体封装件的制法，其特征在于，该导电柱的材料为铜。
16.根据权利要求10所述的半导体封装件的制法，其特征在于，该封装基板还包含有导电通孔及第三电性连接垫，该第三电性连接垫形成于该第二表面上，而该导电通孔位于该第二电性连接垫及该第三电性连接垫之间且贯穿该封装基板，以电性连接该第二电性连接垫及该第三电性连接垫。
17.根据权利要求10所述的半导体封装件的制法，其特征在于，在形成该第一封装胶体之前，还包括于该第一芯片与封装基板之间形成底胶。
18.根据权利要求10所述的半导体封装件的制法，其特征在于，移除部分厚度的该第一封装胶体还包括移除部分厚度的该芯片。
19.一种半导体封装件的制法，包括：
提供一封装基板，该封装基板具有相对的第一表面及第二表面、多个第一电性连接垫及第二电性连接垫，而该第一电性连接垫及第二电性连接垫形成于该第一表面上；
在各该第二电性连接垫上形成导电柱；
将具有相对的作用面与非作用面的芯片的作用面以覆晶方式接置在该第一电性连接垫上；
在该第一表面上形成第一封装胶体，以包覆该芯片及该导电柱；以及
在该第一封装胶体的顶面形成开孔以露出该导电柱的顶面。
20.根据权利要求19所述的半导体封装件的制法，其特征在于，于该第一封装胶体的顶面形成该开孔之后，还包括：
在该导电柱上接置电子组件，而该电子组件藉由其上的多个导电组件电性连接该导电柱；以及
于该第一封装胶体上形成第二封装胶体，以包覆该电子组件。
21.根据权利要求20所述的半导体封装件的制法，其特征在于，在接置该电子组件之前，还包括将表面处理层形成在该导电柱的顶面上。
22.根据权利要求20所述的半导体封装件的制法，其特征在于，该电子组件为半导体芯片或封装结构。
23.根据权利要求19所述的半导体封装件的制法，其特征在于，该导电柱的材料为铜。
24.根据权利要求19所述的半导体封装件的制法，其特征在于，该封装基板还包含有导电通孔及第三电性连接垫，该第三电性连接垫形成于该第二表面上，而该导电通孔位于该第二电性连接垫及该第三电性连接垫之间且贯穿该封装基板，以电性连接该第二电性连接垫及该第三电性连接垫。
25.根据权利要求19所述的半导体封装件的制法，其特征在于，在形成该第一封装胶体之前，还包括于该第一芯片与封装基板之间形成底胶。
26.根据权利要求20所述的半导体封装件的制法，其特征在于，在接置该电子组件之前，还包括于该第一封装胶体上形成绝缘保护层，而该绝缘保护层具有绝缘保护层开孔，以露出该导电柱。
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