TWI556379B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI556379B
TWI556379B TW103100019A TW103100019A TWI556379B TW I556379 B TWI556379 B TW I556379B TW 103100019 A TW103100019 A TW 103100019A TW 103100019 A TW103100019 A TW 103100019A TW I556379 B TWI556379 B TW I556379B
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Taiwan
Prior art keywords
electrical connection
encapsulant
conductive
connection pad
semiconductor package
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TW103100019A
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English (en)
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TW201528453A (zh
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江政嘉
江東昇
王隆源
童世豪
黃淑惠
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103100019A priority Critical patent/TWI556379B/zh
Priority to CN201410009411.7A priority patent/CN104766837A/zh
Priority to US14/255,326 priority patent/US9646921B2/en
Publication of TW201528453A publication Critical patent/TW201528453A/zh
Application granted granted Critical
Publication of TWI556379B publication Critical patent/TWI556379B/zh
Priority to US15/478,508 priority patent/US10163662B2/en

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Description

半導體封裝件及其製法
本發明提供一種半導體封裝件及其製法，尤指一種具有導電柱之半導體封裝件及其製法。
近年來，由於各種電子產品在尺寸上是日益要求輕、薄及小，因此可節省基板平面面積並可同時兼顧處理性能之堆疊式封裝件(package on package，PoP)愈來愈受到重視。
習知的堆疊式封裝件係使用銲球來作為底層封裝基板與上層電子元件之間的電性連接用途之互連結構(interconnection)，然而，為了避免迴銲時的橋接問題，作為互連結構之銲球之間的間距係通常大於300微米，因此互連結構佔用過大的基板面積，從而侷限了封裝件之輸入/輸出(I/O)的電性連接密度。
此外，由於作為互連結構之銲球互連結構係需要較底封裝件上之晶片為高的高度，因此亦使習知堆疊式封裝件的高度無法減低，從而令使用習知堆疊式封裝件之電子裝置的厚度無法更進一步降低。
再者，習知堆疊式封裝件的底層封裝基板與上層電子元件之間並未形成封裝膠體，故連接在底層封裝基板上的晶片及互連結 構無法受到封裝膠體的保護，從而容易遭到水氣入侵。
因此，如何克服習知堆疊式封裝件互連結構的輸入/輸出(I/O)密度無法進一步提高及封裝件厚度無法進一步降低的問題，以及如何解決習知堆疊式封裝件之底層封裝基板上的晶片及互連結構未受到封裝膠體之保護的問題，實為本領域技術人員的一大課題。
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：具有相對之第一表面及第二表面、複數第一電性連接墊及複數第二電性連接墊的封裝基板，而該第一電性連接墊及第二電性連接墊係形成於該第一表面上；具有相對之作用面與非作用面的晶片，係以其作用面覆晶接置於該第一電性連接墊上；形成於該第二電性連接墊上的導電柱；以及形成於該第一表面上，並包覆該晶片及該導電柱，且具有外露該導電柱之頂面的開孔的第一封裝膠體。
本發明另提供一種半導體封裝件之製法，係包括：提供一封裝基板，該封裝基板係具有相對之第一表面及第二表面、複數第一電性連接墊及第二電性連接墊，而該第一電性連接墊及第二電性連接墊係形成於該第一表面上；將導電柱在各該第二電性連接墊上形成；以覆晶方式將具有相對之作用面與非作用面的晶片之作用面接置在該第一電性連接墊上；在該第一表面上形成第一封裝膠體，以包覆該晶片及該導電柱；以及從該第一封裝膠體之頂面移除部分厚度之該第一封裝膠體及其內之該導電柱，使該第一封裝膠體的頂面及該導電柱的頂面係齊平於該晶片之非作用面。
本發明另提供另一種半導體封裝件之製法，係包括：提供一 封裝基板，該封裝基板係具有相對之第一表面及第二表面、複數第一電性連接墊及第二電性連接墊，而該第一電性連接墊及第二電性連接墊係形成於該第一表面上；在各該第二電性連接墊上形成導電柱；將具有相對之作用面與非作用面的晶片之作用面以覆晶方式接置在該第一電性連接墊上；在該第一表面上形成第一封裝膠體，以包覆該晶片及該導電柱；以及在該第一封裝膠體之頂面形成開孔以露出該導電柱之頂面。
本發明之半導體封裝件可藉由使用導電柱作為堆疊式封裝件之互連結構並使封裝膠體的頂面及導電柱的頂面齊平於晶片之非作用面，而避免以習知之銲球來作為堆疊式封裝件的互連結構所造成之密度無法進一步提高及厚度無法進一步降低的問題，並節省基板平面面積，另外，本發明之半導體封裝件可藉由在底層封裝基板與上層電子元件之間形成封裝膠體而保護晶片及互連結構不受水氣入侵的影響。
10‧‧‧封裝基板
10a‧‧‧第一表面
10b‧‧‧第二表面
100‧‧‧第一電性連接墊
102‧‧‧第二電性連接墊
104‧‧‧導電柱
106‧‧‧底膠
108‧‧‧第一封裝膠體
108a‧‧‧開孔
110‧‧‧表面處理層
112‧‧‧絕緣保護層
112a‧‧‧絕緣保護層開孔
114‧‧‧導電通孔
116‧‧‧第三電性連接墊
118‧‧‧防焊層
118a‧‧‧開口
120‧‧‧銲球
20‧‧‧晶片
20a‧‧‧作用面
20b‧‧‧非作用面
200‧‧‧銅柱
202‧‧‧銲料
30‧‧‧電子元件
300‧‧‧導電元件
40‧‧‧第二封裝膠體
第1A圖至第1G圖係本發明之半導體封裝件之製法的剖視圖；第1F’與1G’圖分別係第1F與1G圖的另一實施態樣之剖視圖；以及第1D”及1G”圖分別係第1D及1G圖的又一實施態樣的剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。本發明亦可藉由其它不同的具體實施例加以施行或 應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。
首先請參照第1A圖至第1G圖，該等圖係本發明之半導體封裝件之製法的剖視圖，其中，該半導體封裝件之製法的各步驟將參照各圖而於以下詳細說明。
請參照第1A圖，首先，提供一封裝基板10，而封裝基板10係具有相對之第一表面10a及第二表面10b、複數第一電性連接墊100及第二電性連接墊102，而第一電性連接墊100及第二電性連接墊102係形成於該第一表面10a上。在本實施例之另一範例中，封裝基板10復包括導電通孔114及第三電性連接墊116，其中，第三電性連接墊116係形成於第二表面10b上，並且導電通孔114係位於第二電性連接墊102及第三電性連接墊116之間且貫穿封裝基板10，以使第二電性連接墊102及第三電性連接墊116電性連接。此外，第二表面10b上可形成有防焊層118，且防焊層118係具有開口118a以露出第三電性連接墊116。
請參照第1B圖，其次，在各第二電性連接墊102上形成導電柱104，其材料係為銅，但本發明不限於此。
請參照第1C圖，再者，將具有相對之作用面20a與非作用面20b的晶片20之作用面20a以覆晶方式接置在第一電性連接墊100上；此時，該導電柱104之頂面可高於該非作用面20b，但不以此為限，詳細而言，在本實施例之一範例中，晶片20係藉由在作用面20a上之銅柱200上的銲料202而以例如為迴銲的方式來使銲料202電性連接第一電性連接墊100，從而令晶片20覆晶接置於第一電性連接墊100上。另外，可在覆晶接置晶片20後，於晶片 20與封裝基板10之間形成底膠106，以包覆第一電性連接墊100、銲料202及銅柱200。
請參照第1D圖，而後，在第一表面20a上形成第一封裝膠體108，以包覆晶片20及導電柱104。
請參照第1E圖，隨後，從第一封裝膠體108之頂面移除部分厚度之第一封裝膠體108及其內之導電柱104至一預定厚度，使第一封裝膠體108的頂面、導電柱104的頂面及晶片20之非作用面20b係互相齊平，且移除部分厚度之該第一封裝膠體108復可包括移除部分厚度之該晶片20。而移除之方法可為刷磨或研磨，但本發明不限於此，並且移除導電柱104和晶片20之何者係視導電柱104和晶片20之何者的頂面高於該預定厚度而定。另外，本發明可在此步驟中於第一封裝膠體108上形成絕緣保護層，且該絕緣保護層係具有絕緣保護層開孔，以露出導電柱104之頂面(未圖示此情況)。
請參照第1F圖，之後，再從導電柱104之頂面移除部分厚度的導電柱104，以使導電柱104之頂面低於晶片20之非作用面20b，而移除之方法可為蝕刻，但本發明不限於此。另外，在本實施例中，可在導電柱104之頂面上形成表面處理層110，且可在開口118a中將銲球120形成或接置在第三電性連接墊116上。
請參照第1G圖，最後，在導電柱104上接置電子元件30，而電子元件30係藉由其上的複數導電元件300電性連接導電柱104，並且於第一封裝膠體108上形成第二封裝膠體40，以包覆電子元件30。
請參照第1F’及1G’圖，該等圖分別係第1F及1G圖的另 一實施態樣的剖視圖，而本實施態樣與第1F及1G圖之差異係在於本實施態樣之導電柱104之頂面係與晶片20之非作用面20b齊平。
第1F’及1G’圖之製法係先在導電柱104之頂面上形成表面處理層110，再於晶片20之非作用面20b及第一封裝膠體108上形成絕緣保護層112，並在絕緣保護層112中形成絕緣保護層開孔112a，以露出導電柱104，或者，可先於晶片20之非作用面20b及第一封裝膠體108上形成絕緣保護層112，並在絕緣保護層112中形成絕緣保護層開孔112a，以露出導電柱104，再於導電柱104之頂面上形成表面處理層110。之後，再如以上第1G圖所述之內容地在導電柱104上接置電子元件30，以及在絕緣保護層112上形成包覆電子元件30的第二封裝膠體40，從而形成如第1G’圖的半導體封裝件。
請參照第1D”及1G”圖，該等圖分別係第1D及1G圖的又一實施態樣的剖視圖，而本實施態樣與第1D及1G圖之差異係在於本實施態樣之導電柱104及第一封裝膠體108的頂面係高於晶片20之非作用面20b，且第1D”圖的第一封裝膠體108之頂面係具有露出導電柱104之頂面的開孔108a。
詳而言之，第1D”及1G”圖之製法中，導電柱104的頂面係高於晶片20之非作用面20b，而在如第1D圖所述之形成第一封裝膠體108之後，再於第一封裝膠體108之頂面形成開孔108a以露出導電柱104的頂面。之後，可在導電柱104之頂面上形成表面處理層110。最後，再如以上第1G圖所述之內容地在導電柱104上接置電子元件30，以及在第一封裝膠體108上形成包覆電 子元件30的第二封裝膠體40，從而形成如第1G”圖的半導體封裝件。另外，本實施態樣亦可於第一封裝膠體108上形成絕緣保護層，且該絕緣保護層係具有絕緣保護層開孔，以露出導電柱104之頂面(未圖示此情況)，此時第二封裝膠體40係形成在該絕緣保護層上。
本發明之半導體封裝件的剖視圖係如第1G圖所示，其中，該半導體封裝件係包括封裝基板10、晶片20、導電柱104及第一封裝膠體108，而為了清楚了解本發明起見，該半導體封裝件之結構及各組件將於以下詳細說明。
如上所述之封裝基板10係具有相對之第一表面10a及第二表面10b、複數第一電性連接墊100及複數第二電性連接墊102，而第一電性連接墊100及第二電性連接墊102係形成於第一表面10a上，而本實施例之一範例中，第一電性連接墊100及第二電性連接墊102可嵌埋於第一表面10a並外露於第一表面10a(未圖示此情況)。而本實施例之另一範例中，封裝基板10復包括導電通孔114及第三電性連接墊116，其中，第三電性連接墊116係形成於第二表面10b上，在此範例中，第三電性連接墊116可嵌埋於第二表面10b並外露於第二表面10b(未圖示此情況)，並且導電通孔114係位於第二電性連接墊102及第三電性連接墊116之間，且貫穿封裝基板10，以使第二電性連接墊102及第三電性連接墊116電性連接。此外，第二表面10b上可形成有防焊層118，且防焊層118係具有開口118a以露出第三電性連接墊116，再者，可在開口118a中將銲球120形成或接置在第三電性連接墊116上。
如上所述之晶片20係具有相對之作用面20a與非作用面 20b，且係以其作用面20a覆晶接置於第一電性連接墊100上，詳細而言，在本實施例之一範例中，晶片20之作用面20a上係具有銅柱200，而銅柱200上形成有銲料202，因此，晶片20係藉由例如為迴銲的方式而使銲料202電性連接第一電性連接墊100，從而令晶片20覆晶接置於第一電性連接墊100上。
如上所述之導電柱104，其材料係為銅，但本發明不限於此，而導電柱104係形成於第二電性連接墊102上，且導電柱104之頂面係低於晶片20之非作用面20b，而在此實施例中，導電柱104之頂面上可形成有表面處理層110。
如上所述之第一封裝膠體108係形成於第一表面10a上，並包覆晶片20及導電柱104，且具有外露導電柱104之頂面的開孔108a，而在導電柱104之頂面上形成有表面處理層110的範例中，該開孔108a係外露表面處理層110。另外，在本實施例之一範例中，晶片20與封裝基板10之間可形成有底膠(underfill)106，以包覆第一電性連接墊100、銲料202及銅柱200。
在本發明之實施例中，該半導體封裝件復包括電子元件30、複數導電元件300及第二封裝膠體40，其中，電子元件30可為半導體晶片或封裝結構，但本發明不限於此，而導電元件300係形成或接置在電子元件30上，並且電子元件30係藉由其上的複數導電元件300電性連接導電柱104，而第二封裝膠體40係形成於第一封裝膠體108上，以包覆電子元件30。
另外，本發明可於第一封裝膠體108上形成絕緣保護層，且該絕緣保護層係具有絕緣保護層開孔，以露出導電柱104之頂面(未圖示此情況)，此時第二封裝膠體40係形成在該絕緣保護層上。
本發明之半導體封裝件的另一實施態樣的剖視圖係如第1G’圖所示，其中，該半導體封裝件與第1G圖中之半導體封裝件的差異係在於本實施態樣之導電柱104之頂面係齊平於晶片20之非作用面20b。在此情況下，本實施例之一範例可在晶片20及第一封裝膠體108上形成有絕緣保護層112，且絕緣保護層112具有絕緣保護層開孔112a，以露出導電柱104，另外，第二封裝膠體40則係形成於絕緣保護層112上，以包覆電子元件30，而絕緣保護層112可例如為防焊材料所形成的層，但本發明不限於此。並且，在此實施例中，導電柱104之頂面上可形成有表面處理層110。
本發明之半導體封裝件的另一實施態樣的剖視圖係如第1G”圖所示，其中，該半導體封裝件與第1G圖中之半導體封裝件的差異係在於本實施態樣之導電柱104的頂面及第一封裝膠體108的頂面係高於晶片20之非作用面20b。在此實施例中，導電柱104之頂面上可形成有表面處理層110，且表面處理層110之頂面係齊平或低於第一封裝膠體108之頂面。另外，本實施態樣亦可於第一封裝膠體108上形成絕緣保護層，且該絕緣保護層係具有絕緣保護層開孔，以露出導電柱104之頂面(未圖示此情況)，此時第二封裝膠體40係形成在該絕緣保護層上。
綜上所述，相較於先前技術，由於本發明係藉由在底層封裝基板與上層電子元件之間形成封裝膠體以保護晶片及互連結構不受水氣入侵的影響。另外，由於本發明係藉由將第一封裝膠體與導電柱之部份厚度移除，或者，本發明係藉由將第一封裝膠體、導電柱及晶片之部份厚度移除，以使第一封裝膠體的頂面及導電 柱的頂面係齊平於晶片之非作用面，從而使本發明之半導體封裝件可具有更薄的厚度，此外，由於本發明使用了導電柱來作為封裝基板與電子元件之間的互連結構，從而可使本發明之互連結構較先前技術中以銲球所作成的互連結構具有更低的高度並具有更小的間距，從而使半導體封裝件可具有較先前技術中之半導體封裝件更薄的厚度及更高密度的輸入/輸出(I/O)。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10‧‧‧封裝基板
10a‧‧‧第一表面
10b‧‧‧第二表面
100‧‧‧第一電性連接墊
102‧‧‧第二電性連接墊
104‧‧‧導電柱
106‧‧‧底膠
108‧‧‧第一封裝膠體
114‧‧‧導電通孔
116‧‧‧第三電性連接墊
118‧‧‧防焊層
118a‧‧‧開口
20‧‧‧晶片
20a‧‧‧作用面
20b‧‧‧非作用面
200‧‧‧銅柱
202‧‧‧銲料

Claims (26)

  1. 一種半導體封裝件，係包括：封裝基板，係具有相對之第一表面及第二表面、複數第一電性連接墊及複數第二電性連接墊，而該第一電性連接墊及第二電性連接墊係形成於該第一表面上；具有相對之作用面與非作用面的晶片，係以其作用面覆晶接置於該第一電性連接墊上；導電柱，係形成於該第二電性連接墊上；以及第一封裝膠體，係形成於該第一表面上，並包覆該晶片及該導電柱，使該第一封裝膠體的表面及該晶片之非作用面齊平，且外露該導電柱之頂面。
  2. 如申請專利範圍第1項所述之半導體封裝件，復包括電子元件及其上之複數導電元件，該電子元件係藉由該導電元件電性連接該導電柱。
  3. 如申請專利範圍第2項所述之半導體封裝件，其中，該電子元件係為半導體晶片或封裝結構。
  4. 如申請專利範圍第2項所述之半導體封裝件，復包括第二封裝膠體，係形成於該第一封裝膠體上，以包覆該電子元件。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電柱之材料係為銅。
  6. 如申請專利範圍第1項所述之半導體封裝件，復包括導電通孔及第三電性連接墊，該第三電性連接墊係形成於該第二表面上，而該導電通孔係位於該第二電性連接墊及該第三電性連接墊之間且貫穿該封裝基板，以電性連接該第二電性連接墊及該 第三電性連接墊。
  7. 如申請專利範圍第1項所述之半導體封裝件，復包括表面處理層，係形成在該導電柱之頂面上。
  8. 如申請專利範圍第1項所述之半導體封裝件，復包括絕緣保護層，係形成在該晶片及該第一封裝膠體上方，並具有絕緣保護層開孔，以露出該導電柱。
  9. 如申請專利範圍第1項所述之半導體封裝件，復包括底膠，係形成於該晶片與封裝基板之間。
  10. 一種半導體封裝件之製法，係包括：提供一封裝基板，該封裝基板係具有相對之第一表面及第二表面、複數第一電性連接墊及第二電性連接墊，而該第一電性連接墊及第二電性連接墊係形成於該第一表面上；在各該第二電性連接墊上形成導電柱；將具有相對之作用面與非作用面的晶片之作用面以覆晶方式接置在該第一電性連接墊上；在該第一表面上形成第一封裝膠體，以包覆該晶片及該導電柱；以及從該第一封裝膠體之頂面移除部分厚度之該第一封裝膠體及其內之該導電柱，使該第一封裝膠體的頂面及該導電柱的頂面係齊平於該晶片之非作用面。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，於使該第一封裝膠體的頂面及該導電柱的頂面係齊平於該晶片之非作用面之後，復包括：從該導電柱之頂面移除部分厚度之該導電柱； 在該導電柱上接置電子元件，而該電子元件藉由其上的複數導電元件電性連接該導電柱；以及於該第一封裝膠體上形成第二封裝膠體，以包覆該電子元件。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，在接置該電子元件之前，復包括將表面處理層形成在該導電柱之頂面上。
  13. 如申請專利範圍第10項所述之半導體封裝件之製法，於使該第一封裝膠體的頂面及該導電柱的頂面係齊平於該晶片之非作用面之後，復包括在該晶片及該第一封裝膠體上形成絕緣保護層，而該絕緣保護層係具有絕緣保護層開孔，以露出該導電柱。
  14. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該電子元件係為半導體晶片或封裝結構。
  15. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該導電柱之材料係為銅。
  16. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該封裝基板復包含有導電通孔及第三電性連接墊，該第三電性連接墊係形成於該第二表面上，而該導電通孔係位於該第二電性連接墊及該第三電性連接墊之間且貫穿該封裝基板，以電性連接該第二電性連接墊及該第三電性連接墊。
  17. 如申請專利範圍第10項所述之半導體封裝件之製法，在形成該第一封裝膠體之前，復包括於該第一晶片與封裝基板之間形成底膠。
  18. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，移除部分厚度之該第一封裝膠體復包括移除部分厚度之該晶片。
  19. 一種半導體封裝件之製法，係包括：提供一封裝基板，該封裝基板係具有相對之第一表面及第二表面、複數第一電性連接墊及第二電性連接墊，而該第一電性連接墊及第二電性連接墊係形成於該第一表面上；在各該第二電性連接墊上形成導電柱；將具有相對之作用面與非作用面的晶片之作用面以覆晶方式接置在該第一電性連接墊上；在該第一表面上形成第一封裝膠體，以包覆該晶片及該導電柱；以及在該第一封裝膠體之頂面形成開孔以露出該導電柱之頂面。
  20. 如申請專利範圍第19項所述之半導體封裝件之製法，於該第一封裝膠體之頂面形成該開孔之後，復包括：在該導電柱上接置電子元件，而該電子元件藉由其上的複數導電元件電性連接該導電柱；以及於該第一封裝膠體上形成第二封裝膠體，以包覆該電子元件。
  21. 如申請專利範圍第20項所述之半導體封裝件之製法，在接置該電子元件之前，復包括將表面處理層形成在該導電柱之頂面上。
  22. 如申請專利範圍第20項所述之半導體封裝件之製法，其中， 該電子元件係為半導體晶片或封裝結構。
  23. 如申請專利範圍第19項所述之半導體封裝件之製法，其中，該導電柱之材料係為銅。
  24. 如申請專利範圍第19項所述之半導體封裝件之製法，其中，該封裝基板復包含有導電通孔及第三電性連接墊，該第三電性連接墊係形成於該第二表面上，而該導電通孔係位於該第二電性連接墊及該第三電性連接墊之間且貫穿該封裝基板，以電性連接該第二電性連接墊及該第三電性連接墊。
  25. 如申請專利範圍第19項所述之半導體封裝件之製法，在形成該第一封裝膠體之前，復包括於該第一晶片與封裝基板之間形成底膠。
  26. 如申請專利範圍第20項所述之半導體封裝件之製法，在接置該電子元件之前，復包括於該第一封裝膠體上形成絕緣保護層，而該絕緣保護層係具有絕緣保護層開孔，以露出該導電柱。
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