TWI753623B - 半導體封裝件及製造方法 - Google Patents
半導體封裝件及製造方法 Download PDFInfo
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- TWI753623B TWI753623B TW109137013A TW109137013A TWI753623B TW I753623 B TWI753623 B TW I753623B TW 109137013 A TW109137013 A TW 109137013A TW 109137013 A TW109137013 A TW 109137013A TW I753623 B TWI753623 B TW I753623B
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
Abstract
一種封裝件包括不具有任何主動裝置的中介層結構。中介層結構包括:內連裝置;介電膜,環繞內連裝置;以及第一金屬化圖案,接合至內連裝置。所述封裝件更包括:第一裝置晶粒,接合至第一金屬化圖案的與內連裝置相對的側;以及第二裝置晶粒,接合至第一金屬化圖案的與第一裝置晶粒相同的側。內連裝置將第一裝置晶粒電性連接至第二裝置晶粒。
Description
本發明實施例是有關於一種半導體封裝件及製造方法。
由於各種電子組件(例如,電晶體、二極體、電阻器、電容器等)的積集密度持續提高,半導體工業經歷了快速發展。在很大程度上,積集密度提高起因於最小特徵尺寸(minimum feature size)的重複減小,此使得更多組件能夠被整合至給定面積中。隨著對縮小電子裝置的需求的增長,對更小且更具創造性的半導體晶粒封裝技術的需求已經浮現。此種封裝系統的實例是疊層封裝(Package-on-Package,PoP)技術。在PoP裝置中,頂部半導體封裝件堆疊於底部半導體封裝件頂上,以提供高積集度及高組件密度。PoP技術一般而言能夠生產功能得到增強且在印刷電路板(printed circuit board,PCB)上佔用面積小的半導體裝置。
本發明實施例提供一種封裝件,包括:中介層結構、第一裝置
晶粒以及第二裝置晶粒。中介層結構不具有任何主動裝置。中介層結構包括:內連裝置;介電膜,環繞內連裝置;以及第一金屬化圖案,接合至內連裝置。第一裝置晶粒接合至第一金屬化圖案的與內連裝置相對的側。第二裝置晶粒接合至第一金屬化圖案的與第一裝置晶粒相同的側。內連裝置將第一裝置晶粒電性連接至第二裝置晶粒。
本發明實施例提供一種封裝件,包括:中介層、第一裝置晶粒、第二裝置晶粒以及芯體基底。中介層不具有主動裝置。中介層包括:內連裝置、被動裝置、介電膜以及第一金屬化圖案。內連裝置包括:半導體基底;以及第一內連結構,位於半導體基底上。介電膜隱埋內連裝置及被動裝置。第一金屬化圖案位於介電膜、內連裝置及被動裝置之上。內連裝置藉由第一焊接區接合至第一金屬化圖案的第一表面,且被動裝置藉由第二焊接區接合至第一金屬化圖案的第一表面。第一裝置晶粒藉由第三焊接區直接接合至第一金屬化圖案的第二表面。第一金屬化圖案的第一表面與第一金屬化圖案的第二表面相對。第二裝置晶粒藉由第四焊接區直接接合至第一金屬化圖案的第二表面。第一內連結構中的電性佈線在第一裝置晶粒與第二裝置晶粒之間對訊號進行電性路由。芯體基底直接接合至中介層的與第一裝置晶粒及第二裝置晶粒相對的側。
本發明實施例提供一種方法,包括:將內連裝置接合至第一金屬化圖案的第一表面,內連裝置不具有任何主動裝置;將被動裝置接合至第一金屬化圖案的第一表面,被動裝置不具有任何主動裝置;將內連裝置及被動裝置隱埋於介電膜中;將第一裝置晶粒接合至第一金屬化圖案的第二表面,第二表面與第一表面相對;以及將第二裝置晶粒接合至第一金屬
化圖案的第二表面,其中內連裝置在第一裝置晶粒與第二裝置晶粒之間對訊號進行電性路由。
50:內連裝置
52:被動裝置
54:裝置晶粒
54A:邏輯晶粒
54B:記憶體晶粒
54C:多功能晶粒
60、82:基底
62、90:內連結構
64:電性佈線
66、94:鈍化膜
68、92:墊
70:金屬柱
71、99、116、142、154:導電連接件
72:焊接區
84:主動裝置
88:導通孔
91:電性佈線
100:載體基底
102:釋放層
104:晶種層
106、112、124、128、132、138:介電層
108:開口
110:預焊接區
114、126、130、134:金屬化圖案
114A:導電柱
114B:導電墊
118、156:底部填充膠
120、150:通孔
122:介電膜
136:內連結構
140:凸塊下金屬(UBM)
144:芯體基底
146、148:金屬包覆層
152:芯體基底
200:中介層結構
250:半導體封裝件
結合附圖閱讀以下詳細說明,會最佳地理解本揭露的各個態樣。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1示出根據一些實施例的內連裝置的剖視圖。
圖2、圖3、圖4、圖5A、圖5B、圖6、圖7、圖8、圖9、圖10及圖11示出根據一些實施例的製造含有內連裝置的中介層結構的中間步驟的剖視圖。
圖12A、圖12B、圖13A、圖13B、圖14A、圖14B及圖16示出根據一些實施例的製造含有中介層結構的封裝件的中間步驟的各種視圖。
圖15示出根據一些實施例的裝置晶粒的剖視圖。
以下揭露提供用於實施本發明的不同特徵的許多不同實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其
中第一特徵與第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外,本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的,而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「位於...之下(beneath)」、「位於...下方(below)」、「下部的(lower)」、「位於...上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向),且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
在本揭露中,闡述封裝件及封裝件的形成的各個態樣。各種實施例可使用異質整合來提供具有裝置晶粒、內連裝置及被動裝置的封裝件。三維(three-dimensional,3D)封裝件包括具有內部內連裝置的中介層結構。內連裝置提供直接接合至中介層結構的裝置晶粒(例如,系統晶片(system on chip,SoC)、其他功能晶粒、混合記憶體立方體(hybrid memory cube,HBM)、其他記憶體晶粒、多功能晶粒等)之間的電性內連。中介層結構可更包括被動裝置(例如,整合式被動裝置(integrated passive device,
IPD))。在各種實施例中,中介層結構藉由芯體基底將裝置晶粒電性連接至另一組件(例如,母板(motherboard)等)。藉由將裝置晶粒直接接合至中介層結構,可減小對昂貴裝置晶粒進行單獨封裝件的良率損失。此外,藉由將被動裝置整合於中介層結構內,可降低功率/插入損耗及/或提高電路速度,進而增強封裝件效能。亦可藉由將被動裝置晶粒放置於更靠近裝置晶粒的位置內來獲益。根據一些實施例,示出形成封裝件的中間階段。論述一些實施例的一些變化形式。在所有的各種視圖及例示性實施例中,使用相同的參考編號是指使用相同製程形成的相同元件。
圖1示出根據一些實施例的內連裝置50的剖視圖。內連裝置50將在後續處理中被併入至中介層結構200(參見圖11)中,以形成半導體封裝件250(參見圖14A及圖14B)。內連裝置50在直接接合至半導體封裝件250中的中介層結構200的裝置之間(例如在邏輯晶粒54A與記憶體晶粒54B(參見圖14A及圖14B)之間)提供電性連接。內連裝置50可使用適用的製造製程來形成。內連裝置50可不具有主動裝置及/或不具有被動裝置。舉例而言,內連裝置50可不具有任何電晶體、二極體及/或類似裝置。此外,內連裝置50亦可不具有任何電容器、電阻器、電感器及/或類似裝置或可具有電容器、電阻器、電感器及/或類似裝置。在一些實施例中,內連裝置50可具有介於約10微米與約300微米之間的厚度。在一些實施例中,內連裝置50可具有介於約1公釐乘1公釐與約10公釐乘100公釐之間的橫向尺寸。
仍參照圖1,內連裝置50可包括形成於基底60上的內連結構62。基底60可為例如玻璃基底、陶瓷基底、半導體基底等。在一些實施例中,基底60可為矽晶圓或絕緣體上半導體(semiconductor-on-insulator,SOI)基底的主動層等。基底60可包含半導體材料(例如經摻雜的或未經摻雜的矽)或者可包含其他半導體材料,例如:鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或其組合。亦可使用其他基底,例如多層式基底或梯度基底(gradient substrate)。在一些實施例中,可在單個基底60上形成多個內連裝置50,且將所述多個內連裝置50單體化以形成各別的內連裝置50,例如圖1中所示的各別的內連裝置50。基底60可被稱為具有前側或前表面(例如,在圖1中面朝上的側)以及後側或後表面(例如,在圖1中面朝下的側)。在其中基底60包含矽的實施例中,內連裝置50亦可被稱為矽匯流排(silicon bus)或矽橋(silicon bridge)。
在一些實施例中,內連裝置50包括一或多層電性佈線64(例如,導電線及/或導通孔),所述一或多層電性佈線64位於形成於基底60之上的內連結構62中。電性佈線64可由介電材料(例如,低介電常數介電材料)中的一或多層導電線形成,其中導通孔內連導電線層。舉例而言,電性佈線64可包括一至三層導電線。在其他實施例中,電性佈線64可包括不同層數的導電線。
導通孔可延伸穿過介電質,以在各層導電線之間提供垂直連接。電性佈線64可藉由任何合適的製程(例如沈積、鑲嵌、雙鑲嵌等)來形成。
在一些實施例中,電性佈線64使用鑲嵌製程來形成,其中利用微影技術對相應的介電層進行圖案化及蝕刻,以形成與金屬化層及/或通孔的期望的圖案對應的溝槽。可沈積可選的擴散阻障層及/或可選的黏著層,且可使用導電材料填充溝槽。適合於阻障層的材料包括鈦、氮化鈦、氧化鈦、鉭、氮化鉭、氧化鈦或其他替代材料,且適合於導電材料的材料包括銅、銀、金、鎢、鋁、其組合等。在實施例中,可藉由沈積銅或銅合金的晶種層並藉由電鍍填充溝槽以形成金屬化層。可使用化學機械平坦化(chemical mechanical planarization,CMP)製程等自相應的介電層的表面移除過多的導電材料,且將所述表面平坦化以用於後續處理。
在一些實施例中,使用鑲嵌或雙鑲嵌製程可形成具有較小節距的電性佈線64(例如,「精細節距佈線(fine-pitch routing)」),此可增大電性佈線64的密度且亦可改善內連裝置50內的導電及連接可靠性。舉例而言,電性佈線64可具有介於約0.1微米至約5微米的範圍內的節距(例如,相鄰的導電線之間的間距)。在一些情形中,在高速(例如,大於約2吉位元/秒(Gbit/second))運作期間,電性訊號可在導電組件的表面附近傳導。精細節距佈線可具有較其他類型的佈線小的表面粗糙度,且因此可降低較高速訊
號所經受的電阻,且亦可降低高速運作期間的訊號損耗(例如,插入損耗)。此可改善高速運作的效能,例如串行器/解串器(Serializer/Deserializer,「SerDes」)電路或可以較高速度運作的其他電路的效能。由此,當內連結構50被整合於中介層裝置200中時,內連結構50可在接合至中介層結構200的裝置晶粒(參見圖14A及圖14B)之間提供高速訊號佈線。
在一些實施例中,內連裝置50更包括進行外部連接的墊68,例如鋁墊。墊68可形成於內連結構62上且電性連接至電性佈線64。在一些實施例中,在內連結構62及墊68的部分上形成有一或多個鈍化膜66。開口穿過鈍化膜66延伸至墊68,且導電連接件71延伸穿過鈍化膜66中的開口以接觸墊68。
在一些實施例中,導電連接件71包括上面設置有焊接區72的金屬墊或金屬柱(例如銅柱)70。在一些實施例中,金屬柱70可具有實質上垂直的側壁。作為另外一種選擇,可省略金屬柱70,且焊接區72可直接設置於墊68上。焊接區72可有助於測試內連裝置50。
在一些實施例中,導電連接件71可包含導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合。在一些實施例中,在金屬柱70的頂上形成有金屬頂蓋層(metal cap layer)。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合,且可藉由鍍覆製程形成。在一些實施例中,導電連接件71使用鍍覆製程來形成。
圖2至圖11示出根據一些實施例的形成含有內連裝置50的中介層結構200的製程期間的中間步驟的剖視圖。在圖2中,提供載體基底100。載體基底100可為玻璃載體基底、陶瓷載體基底、晶圓(例如,矽晶圓)等。如圖2中所示,可在載體基底100之上形成釋放層102。釋放層102可由聚合物系材料形成,所述聚合物系材料可與載體基底100一起自將在後續步驟中形成的上覆結構被移除。在一些實施例中,釋放層102是當受熱時會失去其黏著性質的環氧系熱釋放材料,例如光熱轉換(light-to-heat-conversion,LTHC)釋放塗層。在其他實施例中,釋放層102可為紫外(UV)膠,當暴露至紫外(ultra-violet,UV)光時會失去其黏著性質。釋放層102可以液體形態被點膠並固化,可為疊層至第一載體基底100上的疊層膜(laminate film)或可為類似材料。釋放層102的頂表面可被整平且可具有高的平面程度。
仍參照圖2,在釋放層102上形成晶種層104。在一些實施例中,晶種層104是金屬層,可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中,晶種層104包括鈦層及位於所述鈦層之上的銅層。晶種層104可使用例如物理氣相沈積(physical vapor deposition,PVD)等來形成。
在圖3中,可在晶種層104上形成可選的介電層106。介電層106的底表面可接觸晶種層104的頂表面。在一些實施例中,介電層106由例如聚苯並噁唑(polybenzoxazole,PBO)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)等
聚合物形成。在其他實施例中,介電層106由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)等;或者類似材料。介電層106可藉由任何可接受的沈積製程(例如旋轉塗佈(spin coating)、化學氣相沈積(chemical vapor deposition,CVD)、疊層、類似製程或其組合)來形成。
接著,將介電層106圖案化以形成暴露出部分晶種層104的開口108。所述圖案化可藉由可接受的製程來形成,舉例來說,當介電層106是感光性材料時藉由將介電層106暴露至光來進行,或者是藉由使用例如非等向性蝕刻(anisotropic etch)進行蝕刻來進行。若介電層106是感光性材料,則可在曝光之後對介電層106進行顯影。在形成開口108之後,可使用固化製程來使介電層106硬化。另外,可使用另一方法(例如蝕刻、雷射鑽孔(laser drilling)等)將介電層106圖案化。
在圖4中,在開口108中形成可選的預焊接區(pre-solder region)110。在一些實施例中,預焊接區110可包含Sn-Ag、Sn-Cu、Sn-Ag-Cu、其組合等。預焊接區110可使用晶種層104的外露部分並藉由在開口108中進行電鍍來形成。另外,預焊接區110可藉由落球製程(ball drop process)、安裝製程或使用拾取及放置工具的類似製程來形成。在此種實施例中,可省略晶種層104。
在圖5A中,在介電層106及預焊接區110之上形成介
電層112及金屬化圖案114。金屬化圖案114可包括位於介電層112內的導電柱114A及位於介電層112上方的導電墊114B。在一些實施例中,金屬化圖案114亦包括電性連接至導電墊的重佈線走線(redistribution line,RDL)。在此種實施例中,金屬化圖案114的RDL在介電層112的頂表面上對電性訊號、功率訊號或接地訊號重新佈線。
在一些實施例中,介電層112由例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)等聚合物形成。在其他實施例中,介電層112由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻雜硼的磷矽酸鹽玻璃(BPSG)等;或者類似材料。介電層112可藉由任何可接受的沈積製程(例如旋轉塗佈、CVD、疊層、類似製程或其組合)來形成。介電層112的材料可相同於或不同於介電層106的材料。
在形成介電層112之後,接著將介電層112圖案化以形成暴露出部分預焊接區110的開口。所述圖案化可藉由可接受的製程來形成,舉例來說,當介電層112是感光性材料時藉由將介電層112暴露至光來進行,或者藉由使用例如非等向性蝕刻進行蝕刻來進行。若介電層112是感光性材料,則可在曝光之後對介電層112進行顯影。在形成開口之後,可使用固化製程來使介電層112硬化。另外,可使用另一方法(例如蝕刻、雷射鑽孔等)將介電層112圖案化。
接著,形成金屬化圖案114。作為形成金屬化圖案114的實例,在介電層112之上形成晶種層(未示出)。晶種層可進一步形成於介電層112中的開口的側壁及底表面上。在一些實施例中,晶種層是金屬層,可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中,晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如PVD等形成。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案114。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的外露部分上形成導電材料。所述導電材料可藉由鍍覆(例如電鍍或無電鍍覆)等來形成。導電材料可包括金屬,如銅、鈦、鎢、鋁等。移除光阻以及未形成有導電材料於其上的部分晶種層。所述光阻可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除。一旦光阻被移除,則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的外露部分。晶種層的剩餘部分與導電材料形成為金屬化圖案114。
圖5B示出其中省略介電層106及預焊接區110的替代實施例。在此種實施例中,可直接在晶種層104上形成介電層112及金屬化圖案114。可如以上針對圖5A所述般形成金屬化圖案114。另外,可在釋放層102上直接形成介電層106,且在對介電層112進行沈積及圖案化之後,可在介電層112之上及介電層112內沈積晶種層104。在此種實施例中,晶種層104充當形成金屬化
圖案114的晶種層,且不需要單獨的晶種層。
在圖6中,藉由導電連接件71將一或多個內連裝置50(參見例如圖1)接合至金屬化圖案114。舉例而言,可使用覆晶接合製程(flip chip bonding process)將導電連接件71的焊接區接合至金屬化圖案114。可使用回焊製程將導電連接件71的焊接區黏著至金屬化圖案114。儘管圖6將導電連接件71示出為僅包括焊接區,然而在其他實施例中,導電連接件71可具有不同的配置。舉例而言,導電連接件71可包括設置於導電柱上的焊接區(參見例如圖1及圖14B所示導電柱70上的焊接區72)。內連裝置50可用於在隨後接合至中介層結構200的裝置晶粒(參見圖14A及圖14B)之間提供電性連接。
圖6中亦示出,亦可藉由導電連接件116將被動裝置52接合至金屬化圖案114。舉例而言,導電連接件116可包括焊接區,焊接區被使用覆晶接合製程接合至金屬化圖案114。可使用回焊製程將導電連接件116的焊接區黏著至金屬化圖案114。
被動裝置52可相似於內連裝置50。舉例而言,被動裝置52可包括基底(例如,相似於基底60)、形成於基底上的內連結構(例如,相似於內連結構62)以及導電連接件116(例如,相似於導電連接件71)。導電連接件116可提供與被動裝置52的內連結構中的電性佈線的電性連接。可將被動裝置52的內連結構中的電性佈線圖案化以提供一或多個被動電路元件,例如一或多個電容器、電阻器、電感器、類似元件或其組合。被動裝置52可
不具有任何主動裝置(例如,電晶體)。
儘管在圖6中僅示出一個內連裝置50及一個被動裝置52,然而可將任何數目的內連裝置50及/或被動裝置52接合至金屬化圖案114。此外,被動裝置52是可選的且可依據封裝件配置而省略被動裝置52。舉例而言,在其他實施例中,可使用額外的內連裝置50代替被動裝置52。
仍參照圖6,可沈積底部填充膠118以圍繞導電連接件71及116。可在貼合內連裝置50及被動裝置52之後藉由毛細流動製程(capillary flow process)形成底部填充膠118,或者可在貼合內連裝置50及被動裝置52之前藉由適合的沈積方法形成底部填充膠118。底部填充膠118可設置於內連裝置50與金屬化圖案114/介電層112之間。底部填充膠118可進一步設置於被動裝置52與金屬化圖案114/介電層112之間。儘管圖6示出內連裝置50與被動裝置52中的每一者之間的底部填充膠118的單獨部分,然而在其他實施例中,底部填充膠118可在內連裝置50及被動裝置52之下連續地延伸。
在圖7中,在金屬化圖案114之上形成通孔120。作為形成通孔120的實例,在金屬化圖案114上形成光阻並將所述光阻圖案化。光阻可隱埋內連裝置50及被動裝置52。可藉由旋轉塗佈等形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於通孔120。所述圖案化會形成穿過光阻的開口以暴露出金屬化圖案114。在光阻的開口中及在金屬化圖案114的外露部分上
形成導電材料。所述導電材料可藉由鍍覆(例如,電鍍或無電鍍覆)等來形成。導電材料可包括金屬,如銅、鈦、鎢、鋁等。接著移除光阻。所述光阻可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除。導電材料形成通孔120。在圖7中,通孔120延伸至高於內連裝置50的頂表面及被動裝置52的頂表面。亦可存在其他配置。
在圖8中,在內連裝置50、被動裝置52及通孔120之上形成介電膜122以圍繞內連裝置50、被動裝置52及通孔120。介電膜122可填充內連裝置50、被動裝置52及通孔120之間的間隙,且介電膜122可進一步隱埋內連裝置50、被動裝置52及通孔120。在一些實施例中,介電膜122由例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)等聚合物形成。在其他實施例中,介電膜122是底部填充膠,可包含或可不包含填充材料(例如,氧化矽)。在又一些其他實施例中,介電膜122由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻雜硼的磷矽酸鹽玻璃(BPSG)等;或者類似材料。介電膜122可藉由任何可接受的沈積製程(例如疊層、旋轉塗佈、CVD、類似製程或其組合)來形成。可選地,可在沈積之後將介電膜122固化。在其他實施例中,可使用模製化合物、環氧樹脂等代替介電膜122,可藉由壓縮模製、轉移模製、疊層等施加模製化合物、環氧樹脂等。
在圖9中,對介電膜122執行平坦化製程以暴露出通孔
120。平坦化製程亦可移除通孔120的材料。在平坦化製程之後,通孔120的頂表面與介電膜122的頂表面可共面。平坦化製程可為例如化學機械研磨(chemical-mechanical polish,CMP)、磨削製程(grinding process)等。在一些實施例中,舉例而言,在沈積介電膜122之後若已暴露出通孔120,則可省略平坦化。
在圖10中,在介電膜122、通孔120、內連裝置50及被動裝置52之上形成內連結構136。在所示出的實施例中,內連結構136包括介電層124、128、132及138以及金屬化圖案126、130及134(有時被稱為重佈線層或重佈線走線)。具體而言,在介電膜122之上形成介電層124;在介電層124及金屬化圖案126之上形成介電層128;在介電層128及金屬化圖案130之上形成介電層132;且在介電層132及金屬化圖案134之上形成介電層138。此外,金屬化圖案134的通孔部分延伸穿過介電層132;金屬化圖案130的通孔部分延伸穿過介電層128;且金屬化圖案126的通孔部分延伸穿過介電層124。
介電層124、128、132及138可使用與介電層112相似的材料及相似的製程來形成,且為簡明起見,省略對介電層124、128及132的進一步說明。
金屬化圖案126、130及134可使用與金屬化圖案114相似的材料及相似的製程來形成,且為簡明起見,省略對金屬化圖案126、130及134的進一步說明。金屬化圖案126、130及134可電性連接至通孔120,通孔120將金屬化圖案126、130及134
電性連接至金屬化圖案114、內連裝置50及被動裝置52。金屬化圖案126、130及134可提供導電線,導電線在完成的封裝件250(參見圖14A及圖14B)中提供訊號佈線、電源線及/或接地線。在一些實施例中,金屬化圖案126、130或134中的一或多者可為精細節距佈線提供精細節距導電線。舉例而言,金屬化圖案126、130或134中的一或多者的節距可介於20微米至100微米的範圍內。
應理解,第二內連結構136可包括任何數目的介電層及金屬化圖案。若欲形成更多的介電層及金屬化圖案,則可重複進行與以上論述的步驟及製程相似的步驟及製程。金屬化圖案可包括導電線及導通孔。導通孔可在形成金屬化圖案期間藉由在下伏介電層的開口中形成金屬化圖案的晶種層及導電材料來形成。導通孔可因此對各個導電線進行內連及電性耦合。
在圖11中,根據一些實施例,形成用於對第二內連結構136進行外部連接的凸塊下金屬(under-bump metallization,UBM)140及導電連接件142。在形成UBM 140的實例中,首先將介電層138圖案化以形成暴露出部分金屬化圖案134的開口。可使用可接受的製程來執行圖案化,舉例來說,當介電層138是感光性材料時藉由將介電層138暴露至光來進行,或者藉由使用例如非等向性蝕刻進行蝕刻來進行。若介電層138是感光性材料,則可在曝光之後對介電層138進行顯影。
UBM 140具有凸塊部分且具有通孔部分,凸塊部分位於
介電層138的主表面上且沿介電層138的主表面延伸,通孔部分延伸穿過介電層138以在實體上耦合及電性耦合金屬化圖案134。因此,UBM 140電性耦合至金屬化圖案134。UBM 140可由與金屬化圖案134相同的材料來形成,且可使用與金屬化圖案134相似的製程(例如,鍍覆)來形成。在一些實施例中,UBM 140具有與金屬化圖案134不同的尺寸(例如,寬度、厚度等)。
根據一些實施例,接著在UBM 140上形成導電連接件142。導電連接件142可為例如球柵陣列(ball grid array,BGA)連接件、焊料球、金屬柱、受控塌陷晶粒連接(controlled collapse chip connection,C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊等。導電連接件142可包含導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合。在一些實施例中,藉由以下方式形成導電連接件142:首先藉由蒸鍍(evaporation)、電鍍、印刷、焊料轉移(solder transfer)、植球(ball placement)等形成焊料層。一旦已在所述結構上形成焊料層,便可執行回焊,以將材料塑形成期望的凸塊形狀。在另一實施例中,導電連接件142包括藉由濺鍍、印刷、電鍍、無電鍍覆、CVD等形成的金屬柱(例如銅柱)。金屬柱可為無焊料的且具有實質上垂直的側壁。在一些實施例中,在金屬柱的頂上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合,且可藉由鍍覆製程形成。
在一些實施例中,導電連接件142可大於焊接區72(例如,具有較焊接區72大的節距)。因此,便形成了包含內連裝置50及被動裝置52的中介層結構200。在一些實施例中,整個中介層結構200可不具有主動裝置。
圖12A至圖14B示出將中介層結構200接合至芯體基底152以及將裝置晶粒接合至中介層結構200的中間步驟。因此,便形成了半導體封裝件250。
在圖12A及圖12B中,執行載體基底剝離(carrier substrate de-bonding)以將載體基底100自中介層結構200分離(或「剝離」)。根據一些實施例,所述剝離包括對釋放層102投射例如雷射光(laser light)或UV光等光,以使釋放層102在光的熱作用下分解且可移除載體基底100。
接著將所述結構翻轉並接合至芯體基底152。芯體基底152可為由金屬包覆的絕緣基材,例如由銅包覆的環氧樹脂浸漬玻璃布疊層、由銅包覆的聚醯亞胺浸漬玻璃布疊層等。舉例而言,芯體基底144可包括位於基材144的相對的表面上的金屬包覆層146及148。可將金屬包覆層146及148圖案化以在基材144的頂表面及底表面上提供電性佈線。金屬包覆層146及148的圖案化可使用任何合適的製程(例如濕式蝕刻、雷射蝕刻等)來執行。可使用例如覆晶接合製程將導電連接件142直接接合至金屬包覆層146。在一些實施例中,在芯體基底152的金屬包覆層146與中介層結構200的導電連接件142之間不形成中間層(例如,堆積
層)。
芯體基底144可更包括延伸穿過基材144的通孔150。作為形成通孔150的實例,穿過基材形成開口包括使用機械鑽孔或銑削製程。接下來,可使用金屬材料對開口進行鍍覆(例如,使用電化學鍍覆製程)。在一些實施例中,金屬材料可包括銅。對開口的鍍覆可形成通孔150,以用於提供自芯體基底144的一側至另一側的電性連接。在鍍覆之後,可可選地使用絕緣材料填充穿過基材的開口的剩餘部分。
對中介層結構200進行翻轉以暴露出晶種層104。圖12A示出其中介電層106及預焊接區110包括於中介層結構200中的實施例。圖12B示出其中省略介電層106及預焊接區110而使得晶種層104接觸介電層112及金屬化圖案114的替代實施例。
在圖13A及圖13B中,使用合適的製程(例如電漿蝕刻製程、濕式蝕刻製程等)移除晶種層104及介電層106(若存在)。在與圖12A所示實施例對應的圖13A中,移除介電層106以暴露出預焊接區110。在此實施例中,移除介電層106可使用蝕刻製程,蝕刻製程以較對預焊接區110進行蝕刻的速率快的速率選擇性地對介電層106進行蝕刻。在與圖12B所示實施例對應的圖13B中,移除晶種層104以暴露出金屬化圖案114。
在圖14A及圖14B中,藉由導電連接件99將裝置晶粒54A及54B接合至金屬化圖案114。舉例而言,導電連接件99可包括焊接區,焊接區被使用覆晶接合製程接合至金屬化圖案114。
可應用回焊製程將導電連接件99的焊接區黏著至金屬化圖案114。在一些實施例中,導電連接件99可具有與焊接區72相同的大小(例如,具有與焊接區72相同的節距)。在一些實施例中,導電連接件99可小於導電連接件142(例如,具有較導電連接件142小的節距)。圖14A示出其中內連裝置50的導電連接件71僅包括焊接區72的實施例。圖14B示出其中內連裝置的導電連接件71包括設置於導電柱70上的焊接區72的替代實施例。
裝置晶粒54A及54B可相似於內連裝置50。舉例而言,圖15示出裝置晶粒54(例如,裝置晶粒54A及54B)的詳細視圖。裝置晶粒54可包括基底82(例如,相似於基底60)、形成於基底82上的內連結構90(例如,相似於內連結構62)、墊92(例如,相似於墊68)、鈍化層94(例如,相似於鈍化層66)及導電連接件99(例如,相似於導電連接件71)。然而,與內連裝置50不同,裝置晶粒54包括位於基底82的頂表面上的主動裝置84(例如,電晶體)。主動裝置84形成於介電層86中且主動裝置84藉由導通孔88電性連接至電性佈線91。內連結構90中的電性佈線91可提供電路結構。舉例而言,裝置晶粒54可為邏輯晶粒(例如,中央處理單元(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)、系統晶片(SoC)、應用處理器(application processor,AP)、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、靜態隨機存取記憶體(static random access memory,SRAM)
晶粒等)、電源管理晶粒(例如,電源管理積體電路(power management integrated circuit,PMIC)晶粒)、射頻(radio frequency,RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system,MEMS)晶粒、訊號處理晶粒(例如,數位訊號處理(digital signal processing,DSP)晶粒)、前端晶粒(例如,類比前端(analog front-end,AFE)晶粒)、類似晶粒、多功能晶粒或其組合。
返回參照圖14A,將邏輯晶粒54A及記憶體晶粒54B覆晶接合至金屬化圖案114。內連裝置50電性連接至邏輯晶粒54A及記憶體晶粒54B二者,且內連裝置50在邏輯晶粒54A與記憶體晶粒54B之間提供精細節距的電性內連。在各種實施例中,內連裝置50可使得達成接合至中介層結構200的相鄰的裝置晶粒54之間的高速路由。此外,被動裝置52電性連接至邏輯晶粒54A及/或記憶體晶粒54B。藉由將被動裝置52放置於中介層結構200內,可減小被動裝置52與裝置晶粒54之間的距離,進而改善完成的封裝件中的電性效能。
儘管在圖14A及圖14B中僅示出一個邏輯晶粒54A及一個記憶體晶粒54B,然而可將任何數目的裝置晶粒54接合至金屬化圖案114。此外,亦可將其他類型的裝置晶粒54接合至金屬化圖案114。舉例而言,圖16示出接合至中介層結構200的晶粒54的俯視圖。晶粒54包括邏輯晶粒54A、記憶體晶粒54B、多功能晶粒54C等。在其他實施例中,亦可存在其他配置。一或多個
內連裝置50可在接合至中介層結構200的裝置晶粒54中的相鄰的裝置晶粒54之間提供電性內連。
返回參照圖14A及圖14B,可沈積底部填充膠156以圍繞導電連接件99。底部填充膠156可在貼合裝置晶粒54之後藉由毛細流動製程來形成,或者底部填充膠156可在貼合裝置晶粒54之前藉由合適的沈積方法來形成。底部填充膠156可設置於裝置晶粒54與中介層結構200之間。儘管圖14A及圖14B示出在每一裝置晶粒54之下的底部填充膠156的單獨部分,然而在其他實施例中,底部填充膠156可在多個裝置晶粒54之下連續地延伸。
圖14A及圖14B亦示出,在芯體基底152的金屬包覆層148上形成導電連接件154。導電連接件154可用於將完成的封裝件250接合至另一結構(例如封裝件基底、母板等)。導電連接件154可為例如BGA連接件、焊料球、金屬柱、C4凸塊、微凸塊、ENEPIG形成的凸塊等。導電連接件154可包含導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合。在一些實施例中,藉由以下方式形成導電連接件154:首先藉由蒸鍍、電鍍、印刷、焊料轉移、植球等形成焊料層。一旦已在所述結構上形成焊料層,便可執行回焊,以將材料塑形成期望的凸塊形狀。在另一實施例中,導電連接件154包括藉由濺鍍、印刷、電鍍、無電鍍覆、CVD等形成的金屬柱(例如銅柱)。金屬柱可為無焊料的且具有實質上垂直的側壁。在一些實施例中,在金屬柱的頂上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、
銦、鎳-鈀-金、鎳-金、類似材料或其組合,且可藉由鍍覆製程形成。在一些實施例中,導電連接件154可大於導電連接件142(例如,具有較導電連接件142大的節距)。因此,可根據各種實施例形成封裝件250。
亦可包括其他特徵及製程。舉例而言,可包括測試結構以幫助對三維(3D)封裝件或三維積體電路(three-dimensional integrated circuit,3DIC)裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或基底上形成的測試墊(test pad),以便能夠對3D封裝件或3DIC進行測試、使用探針及/或探針卡(probe card)等。可對中間結構以及最終結構執行驗證測試。另外,本文中所揭露的結構及方法可與包含對已知良好晶粒(known good die)進行中間驗證的測試方法接合使用以提高良率並降低成本。
封裝件250可含有內連裝置50,以提升接合至中介層結構的組件(例如,裝置晶粒54)之間的電性訊號的高速傳輸。包含內連裝置50可改善封裝件250的高速運作。藉由將裝置晶粒直接接合至中介層結構,可減少對昂貴裝置晶粒進行單獨封裝件的良率損失。此外,藉由將被動裝置整合於中介層結構內,可降低功率/插入損耗及/或提高電路速度,進而增強封裝件效能。亦可藉由將被動裝置晶粒放置於更靠近裝置晶粒的位置來獲益。
根據一些實施例,一種封裝件包括不具有任何主動裝置的中介層結構。所述中介層結構包括:內連裝置;介電膜,環繞所述內連裝置;以及第一金屬化圖案,接合至所述內連裝置。所
述封裝件更包括:第一裝置晶粒,接合至所述第一金屬化圖案的與所述內連裝置相對的側;以及第二裝置晶粒,接合至所述第一金屬化圖案的與所述第一裝置晶粒相同的側。所述內連裝置將所述第一裝置晶粒電性連接至所述第二裝置晶粒。在一些實施例中,所述中介層結構更包括被動裝置,所述被動裝置接合至所述第一金屬化圖案的與所述內連裝置相同的側,其中所述被動裝置電性連接至所述第一裝置晶粒或所述第二裝置晶粒。在一些實施例中,所述內連裝置被覆晶接合至所述第一金屬化圖案。在一些實施例中,所述內連裝置包括:半導體基底;以及第一內連結構,位於所述半導體基底上,其中所述第一內連結構包括在所述第一裝置晶粒與所述第二裝置晶粒之間對訊號進行電性路由的電性佈線。在一些實施例中,所述電性佈線的節距介於0.1微米至5微米的範圍內。在一些實施例中,所述中介層結構更包括:第二內連結構,位於所述介電膜的與所述第一金屬化圖案相對的側上;以及通孔,延伸穿過所述介電膜,其中所述通孔將所述第二內連結構電性連接至所述第一金屬化圖案。在一些實施例中,所述第一裝置晶粒及所述第二裝置晶粒各自直接接合至所述第一金屬化圖案。
根據一些實施例,一種封裝件包括不具有主動裝置的中介層,所述中介層包括:內連裝置,包括半導體基底以及第一內連結構,所述第一內連結構位於所述半導體基底上;被動裝置;介電膜,隱埋所述內連裝置及所述被動裝置;以及第一金屬化圖
案,位於所述介電膜、所述內連裝置及所述被動裝置之上,其中所述內連裝置藉由第一焊接區接合至所述第一金屬化圖案的第一表面,且所述被動裝置藉由第二焊接區接合至所述第一金屬化圖案的所述第一表面;第一裝置晶粒,藉由第三焊接區直接接合至所述第一金屬化圖案的第二表面,其中所述第一金屬化圖案的所述第一表面與所述第一金屬化圖案的所述第二表面相對;第二裝置晶粒,藉由第四焊接區直接接合至所述第一金屬化圖案的所述第二表面,其中所述第一內連結構中的電性佈線在所述第一裝置晶粒與所述第二裝置晶粒之間對訊號進行電性路由;以及芯體基底,直接接合至所述中介層的與所述第一裝置晶粒及所述第二裝置晶粒相對的側。在一些實施例中,所述被動裝置電性連接至所述第一裝置晶粒或所述第二裝置晶粒。在一些實施例中,所述中介層更包括:第二內連結構,位於所述介電膜的與所述第一金屬化圖案相對的側上;第一通孔,延伸穿過所述介電膜,其中所述第一通孔將所述第二內連結構電性連接至所述第一金屬化圖案;以及第五焊接區,位於所述第二內連結構的與所述第一通孔相對的側上。在一些實施例中,所述芯體基底包括:絕緣芯體材料;第一金屬包覆層,位於所述絕緣芯體材料的第一側上;第二金屬包覆層,位於所述絕緣芯體材料的與所述絕緣芯體材料的所述第一側相對的第二側上;以及第二通孔,延伸穿過所述絕緣芯體材料,其中所述第二通孔將所述第一金屬包覆層電性連接至所述第二金屬包覆層。在一些實施例中,所述中介層的第五焊接區直接
接合至所述第一金屬包覆層。在一些實施例中,所述封裝件更包括直接接觸所述第二金屬包覆層的第六焊接區。在一些實施例中,所述中介層更包括:第一底部填充膠,圍繞所述第一焊接區;以及第二底部填充膠,圍繞所述第二焊接區。在一些實施例中,所述第一底部填充膠與所述第二底部填充膠在實體上隔開。在一些實施例中,所述封裝件更包括:第三底部填充膠,圍繞所述第三焊接區;以及第四底部填充膠,圍繞所述第四焊接區。
根據一些實施例,一種方法包括:將內連裝置接合至第一金屬化圖案的第一表面,所述內連裝置不具有任何主動裝置;將被動裝置接合至所述第一金屬化圖案的所述第一表面,所述被動裝置不具有任何主動裝置;將所述內連裝置及所述被動裝置隱埋於介電膜中;將第一裝置晶粒接合至所述第一金屬化圖案的第二表面,所述第二表面與所述第一表面相對;以及將第二裝置晶粒接合至所述第一金屬化圖案的所述第二表面,其中所述內連裝置在所述第一裝置晶粒與所述第二裝置晶粒之間對訊號進行電性路由。在一些實施例中,所述方法更包括:在所述第一金屬化圖案上形成通孔;將所述通孔隱埋於所述介電膜中;以及在所述介電膜之上形成內連結構,其中所述通孔將所述第一金屬化圖案電性連接至所述內連結構。在一些實施例中,所述方法更包括:將芯體基底接合至所述內連結構的與所述介電膜相對的側。在一些實施例中,所述芯體基底包括:絕緣芯體材料;第一金屬包覆層,位於所述絕緣芯體材料的第一側上,其中所述內連結構直接接合
至所述第一金屬包覆層;第二金屬包覆層,位於所述絕緣芯體材料的與所述絕緣芯體材料的所述第一側相對的第二側上;以及第二通孔,延伸穿過所述絕緣芯體材料,其中所述第二通孔將所述第一金屬包覆層電性連接至所述第二金屬包覆層。
以上概述了若干實施例的特徵,以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應理解,他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到,該些等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
50:內連裝置
52:被動裝置
54A:邏輯晶粒
54B:記憶體晶粒
71、99、142、154:導電連接件
112:介電層
114:金屬化圖案
120、150:通孔
122:介電膜
136:內連結構
140:凸塊下金屬(UBM)
144:芯體基底
146、148:金屬包覆層
152:芯體基底
156:底部填充膠
200:中介層結構
250:半導體封裝
Claims (9)
- 一種封裝件,包括:中介層結構,不具有任何主動裝置,所述中介層結構包括:內連裝置;介電膜,環繞所述內連裝置;以及第一金屬化圖案,接合至所述內連裝置;第一裝置晶粒,接合至所述第一金屬化圖案的與所述內連裝置相對的側;以及第二裝置晶粒,接合至所述第一金屬化圖案的與所述第一裝置晶粒相同的側,其中所述內連裝置將所述第一裝置晶粒電性連接至所述第二裝置晶粒,其中所述中介層結構更包括被動裝置,所述被動裝置接合至所述第一金屬化圖案的與所述內連裝置相同的側,其中所述被動裝置電性連接至所述第一裝置晶粒或所述第二裝置晶粒。
- 如請求項1所述的封裝件,其中所述內連裝置被覆晶接合至所述第一金屬化圖案。
- 一種封裝件,包括:中介層,不具有主動裝置,所述中介層包括:內連裝置,包括:半導體基底;以及第一內連結構,位於所述半導體基底上;被動裝置; 介電膜,隱埋所述內連裝置及所述被動裝置;以及第一金屬化圖案,位於所述介電膜、所述內連裝置及所述被動裝置之上,其中所述內連裝置藉由第一焊接區接合至所述第一金屬化圖案的第一表面,且所述被動裝置藉由第二焊接區接合至所述第一金屬化圖案的所述第一表面;第一裝置晶粒,藉由第三焊接區直接接合至所述第一金屬化圖案的第二表面,其中所述第一金屬化圖案的所述第一表面與所述第一金屬化圖案的所述第二表面相對;第二裝置晶粒,藉由第四焊接區直接接合至所述第一金屬化圖案的所述第二表面,其中所述第一內連結構中的電性佈線在所述第一裝置晶粒與所述第二裝置晶粒之間對訊號進行電性路由;以及芯體基底,直接接合至所述中介層的與所述第一裝置晶粒及所述第二裝置晶粒相對的側。
- 如請求項3所述的封裝件,其中所述被動裝置電性連接至所述第一裝置晶粒或所述第二裝置晶粒。
- 如請求項3所述的封裝件,其中所述中介層更包括:第二內連結構,位於所述介電膜的與所述第一金屬化圖案相對的側上;第一通孔,延伸穿過所述介電膜,其中所述第一通孔將所述第二內連結構電性連接至所述第一金屬化圖案;以及第五焊接區,位於所述第二內連結構的與所述第一通孔相對 的側上。
- 如請求項3所述的封裝件,其中所述芯體基底包括:絕緣芯體材料;第一金屬包覆層,位於所述絕緣芯體材料的第一側上;第二金屬包覆層,位於所述絕緣芯體材料的與所述絕緣芯體材料的所述第一側相對的第二側上;以及第二通孔,延伸穿過所述絕緣芯體材料,其中所述第二通孔將所述第一金屬包覆層電性連接至所述第二金屬包覆層。
- 一種封裝件的製造方法,包括:將內連裝置接合至第一金屬化圖案的第一表面,所述內連裝置不具有任何主動裝置;將被動裝置接合至所述第一金屬化圖案的所述第一表面,所述被動裝置不具有任何主動裝置;將所述內連裝置及所述被動裝置隱埋於介電膜中;將第一裝置晶粒接合至所述第一金屬化圖案的第二表面,所述第二表面與所述第一表面相對;以及將第二裝置晶粒接合至所述第一金屬化圖案的所述第二表面,其中所述內連裝置在所述第一裝置晶粒與所述第二裝置晶粒之間對訊號進行電性路由,且所述被動裝置電性連接至所述第一裝置晶粒或所述第二裝置晶粒。
- 如請求項7所述的封裝件的製造方法,更包括:在所述第一金屬化圖案上形成通孔; 將所述通孔隱埋於所述介電膜中;以及在所述介電膜之上形成內連結構,其中所述通孔將所述第一金屬化圖案電性連接至所述內連結構。
- 如請求項8所述的封裝件的製造方法,更包括:將芯體基底接合至所述內連結構的與所述介電膜相對的側。
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