TW201814843A - 使用埋入式架橋矽穿通孔內連件的半導體封裝 - Google Patents

使用埋入式架橋矽穿通孔內連件的半導體封裝 Download PDF

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TW201814843A
TW201814843A TW105135626A TW105135626A TW201814843A TW 201814843 A TW201814843 A TW 201814843A TW 105135626 A TW105135626 A TW 105135626A TW 105135626 A TW105135626 A TW 105135626A TW 201814843 A TW201814843 A TW 201814843A
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施信益
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美光科技公司
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Abstract

本發明披露一種半導體封裝，包含：一樹脂成型封裝基板，包含樹脂成型核心、複數個貫穿樹脂成型核心的金屬插塞、前側重佈線層結構，以及背側重佈線層結構；一架橋矽穿通孔內連件，埋設於樹脂成型核心內，其中架橋矽穿通孔內連件包含一矽基底部、一整體構成在矽基底部上的重佈線層結構，以及複數個設於矽基底部中的穿矽通孔；一第一半導體晶片及一第二半導體晶片，設於前側重佈線層結構上，其中第一半導體晶片與第二半導體晶片位於共平面。

Description

使用埋入式架橋矽穿通孔內連件的半導體封裝
本發明係有關於半導體封裝技術領域，更特定言之，本發明係有關於一種2.5D晶圓級封裝，其使用樹脂成型封裝基板及埋入式架橋矽穿通孔內連件。
2.5D半導體封裝，諸如CoWoS (Chip-On-Wafer-On-Substrate)技術係本領域所已知的，CoWoS技術通常使用穿矽通孔(TSV)技術將多個晶片結合至單一裝置中。
此架構提供了更高密度的互連、降低整體互連長度以及減輕相關的電阻電容負載，從而於更小的形狀因子上提高性能及減少功耗。
以往，2.5D半導體封裝在矽穿通孔(through-silicon-via, TSV)矽中介層上並排放置多個晶片。晶片係透過微凸塊與矽中介層貼合，其中微凸塊的直徑約10 μm。矽中介層是透過C4凸塊與封裝基板貼合，其中C4凸塊的直徑約100 μm。
本發明係有關於一種2.5D半導體封裝，其使用樹脂成型封裝基板及埋入式架橋矽穿通孔內連件。
本發明一方面，提出一種半導體封裝，包含有：一樹脂成型封裝基板，其包含一樹脂成型核心、複數個金屬插塞，貫穿樹脂成型核心的一正面及一背面、一前側重佈線層結構，整體構成在樹脂成型核心的正面上，以及一背側重佈線層結構，整體構成在樹脂成型核心的背面上。
一架橋矽穿通孔內連件，埋設於樹脂成型核心內，其中架橋矽穿通孔內連件包含一矽基底部、一內埋的重佈線層結構，整體構成在矽基底部上，以及複數個穿矽通孔，設於矽基底部中。
一第一半導體晶片，設於前側重佈線層結構上；一第二半導體晶片，設於前側重佈線層結構上，其中第一半導體晶片與第二半導體晶片位於共平面。複數個錫球，設於背側重佈線層結構的一下表面上。
本發明另一方面，提出一種製作半導體封裝的方法，首先，提供一第一載板；然後，於第一載板上形成一模版層；再 於模版層中形成複數個導孔；接著，分別於複數個導孔中形成金屬插塞；隨後移除模版層，於第一載板上留下金屬插塞；然後，於第一載板上安裝一架橋矽穿通孔內連件。
之後，形成一成型模料，將金屬插塞與架橋矽穿通孔內連件包覆起來；接著，研磨成型模料與架橋矽穿通孔內連件，顯露出架橋矽穿通孔內連件的穿矽通孔以及埋設在成型模料中的金屬插塞。
隨後，於成型模料上形成一背側重佈線層結構；再於背側重佈線層結構上形成複數個錫球；然後移除該第一載板；接著，將一第二載板與複數個錫球貼合；之後，於成型模料上形成一前側重佈線層結構；接著，將一第一半導體晶片與一第二半導體晶片安置於前側重佈線層結構上；最後，移除第二載板。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
於下文中，係加以陳述本發明之具體實施方式，該些具體實施方式可參考相對應的圖式，俾使該些圖式構成實施方式之一部分。同時也藉由說明，揭露本發明可據以施行之方式。該等實施例已被清楚地描述足夠的細節，俾使該技術領域中具有通常技術者可據以實施本發明。其他實施例亦可被加以施行，且對於其結構上所做之改變仍屬本發明所涵蓋之範疇。
因此，下文的細節描述將不被視為一種限定，且本發明所涵蓋之範疇僅被所附之申請專利範圍以及其同意義的涵蓋範圍。本發明之一或多個實施例將參照附圖描述，其中，相同元件符號始終用以表示相同元件，且其中闡述的結構未必按比例所繪製。
本發明之一或多個實施例將參照附圖描述，其中，相同元件符號始終用以表示相同元件，且其中闡述的結構未必按比例所繪製。術語「晶片」、「半導體晶片」及「半導體晶粒」於整個說明書中可互換使用。
文中所使用的術語「晶圓」及「基板」包括任何具有暴露表面之結構，於該表面上根據本發明沉積一層，例如，形成諸如重佈線層的電路結構。術語「基板」被理解為包括半導體晶圓，但不限於此。術語「基板」亦可用以指加工過程中之半導體結構，且可包括已被製造在其上之其它層。
請參考第1圖至第3圖。第1圖至第3圖係根據本發明之實施例所繪示的製作架橋矽穿通孔內連件的示例性方法。
如第1圖所示，首先，提供一半導體基板(或晶圓)100。根據本發明一實施例，半導體基板100可包含基材，例如：矽、鍺、砷化鎵、磷化銦，或碳化矽，用於結構支撐。或者，半導體基板100可包含聚合物、氧化鈹或其它適合用於結構支撐的低成本剛性材料。半導體基板100具有相對的正面100a及背面100b。
然後，使用機械鑽孔、雷射鑽孔，或深反應離子蝕刻(DRIE)結合金屬電鍍或沉積法形成複數個金屬插塞110，其通過部分半導體基板100，金屬插塞110從正面100a延伸至部份半導體基板100，非完全的貫穿半導體基板100。
根據本發明一實施例，金屬插塞110可包含鋁、銅、錫、鎳、金、銀、鈦、鎢、多晶矽，或其它合適的導電材料，其可以藉由使用電解電鍍、無電解電鍍製程，或其它合適的沉積製程來形成。
如第2圖所示，用於佈線電子訊號的重佈線層(RDL)結構200形成於正面100a上。RDL結構200可包含至少一介電層202以及至少一金屬層204。
根據本發明一實施例，介電層202可包含例如聚亞醯胺(polyimide)等有機材料，或例如氮化矽、氧化矽，或其類似物等無機材料，但不限於此。
金屬層204可包含鋁、銅、鎢、鈦、氮化鈦，或其類似物。根據所示實施例，金屬層204可以包含複數個細間距佈線，接觸墊208從介電層202的頂表面顯露出來。連接件210(例如，微凸塊)可以形成在接觸墊208上。金屬層204的一部分可以電連接至金屬插塞110。
應理解的是，金屬層204和接觸墊208的層和佈局僅用於說明的目的。根據設計要求，在其他實施例中，可以在RDL結構200中形成更多層的金屬佈線。
隨後，如第3圖所示，對具有RDL結構200的半導體基板100進行一切割製程，並且透過晶圓切割製程，切割成個別的矽穿通孔內連件101。
請參考第4圖至第14圖。第4圖至第14圖係根據本發明之實施例所繪示的製作2.5D半導體封裝的示例性方法的剖面圖，其使用樹脂成型封裝基板及埋入式架橋矽穿通孔內連件。
如第4圖所示，首先，提供一載板300。載板300可為一可被撕除的基材。載板300可包含玻璃、矽、陶瓷、金屬或任何合適的支撐材料。可以在載板300的頂表面上提供介電層或鈍化層。鈍化層可以包括諸如聚亞醯胺（PI）等有機材料或諸如氮化矽、氧化矽，或其類似物等無機材料，但不限於此。
隨後，在載板300上塗覆一模版層500。例如，模版層500可以是一光阻，諸如，I-line光阻或定向自組裝(DSA)材料，但不限於此。
藉由例如微影製程在模版層500中形成導孔501。每個導孔501延伸通過模版層500的整個厚度。根據本發明一實施例，導孔501可具有相同的通孔直徑或尺寸。根據本發明其他實施例，導孔501可具有不同的通孔直徑。
如第5圖所示，在形成導孔501之後，分別於導孔501中形成金屬插塞510。根據本發明一實施例，導孔501係被金屬完全填滿，金屬例如銅、鎢、鋁、鈦、氮化鈦或其類似物，從而形成金屬插塞510。金屬插塞510可以藉由沉積、網版印刷或任何合適的方法形成。
可選擇地，可以進行一化學機械拋光(CMP)製程以去除導孔501外面的多餘金屬。根據本發明一實施例，金屬插塞510可以具有與模版層500的厚度一樣的高度。根據本發明一實施例，金屬插塞510可以具有相同的通孔直徑或尺寸。根據本發明其他實施例，金屬插塞510可以具有不同的通孔直徑。
根據本發明一實施例，金屬插塞510可作為前側RDL結構和背側RDL結構(例如用於傳遞電源或接地訊號)、散熱件或應力調節件(虛設金屬插塞)之間的互連。
如第6圖所示，在形成金屬插塞510之後，完全移除模版層500，留下完整的金屬插塞510。例如，當含有光阻時，模板層500可以透過電漿蝕刻或灰化製程去除。此時，柱狀金屬插塞510被顯露出來。這些柱狀金屬插塞510圍繞矽穿通孔內連件安裝區域601。
如第7圖所示，如第3圖所示的矽穿通孔內連件101被180度翻轉並且安裝在載板300內的矽穿通孔內連件安裝區域601上。連接件210可以與載板300直接接觸。金屬插塞510可以具有比金屬插塞110的直徑更大的直徑。
如第8圖所示，形成一成型模料550，將金屬插塞510、矽穿通孔內連件101及載板300的頂表面包覆起來。可對成型模料550進行一固化製程。成型模料550可包含環氧樹脂和矽石填料的混合物，但不限於此。成型模料550的層厚度比矽穿通孔內連件101的厚度厚。RDL結構200係埋設在成型模料550中(內埋的RDL結構)。
如第9圖所示，進行一研磨製程，移除成型模料550的上部，以顯露出金屬插塞510的頂表面及金屬插塞110的頂表面。此時，背面100b與成型模料550的表面550a共平面。
如第10圖所示，於成型模料550及金屬插塞510上形成一重佈線層(RDL)結構700。RDL結構700用作背側(或PCB側)RDL結構。RDL結構700可以包含至少一介電層712和至少一金屬層714。
根據本發明一實施例，介電層712可包含例如聚亞醯胺(polyimide)等有機材料，或例如氮化矽、氧化矽，或其類似物等無機材料，但不限於此。
金屬層714可包含鋁、銅、鎢、鈦、氮化鈦，或其類似物。根據所示實施例，金屬層714可以包含複數個佈線，接觸墊718從介電層712的頂表面顯露出來。
應理解的是，金屬層714和接觸墊718的層和佈局僅用於說明的目的。根據設計要求，在其他實施例中，可以在RDL結構700中形成更多層的金屬佈線。
隨後，在接觸墊718上形成錫球810，例如球型格柵陣列(ball grid array, BGA)錫球。應理解的是，防焊層802可以形成在RDL結構700上。在形成錫球810之前，可以在接觸墊718上形成凸塊下金屬(UBM)層(未明確示於圖中)。
接著，如第11圖所示，移除載板300，暴露出金屬插塞510的另一端和連接件210的頂表面。然後，將中間晶圓級產品接合到載板320，其中錫球810與載板320直接接觸。載板320可包括玻璃、矽、陶瓷、金屬或任何合適的支撐材料。可以在載板320上提供一黏著劑層(未明確示於圖中)，並且錫球810可以通過黏著劑層黏附至載板320。
如第12圖所示，於成型模料550、金屬插塞510及連接件210上形成一重佈線層(RDL)結構900，完成具有樹脂成型核心(成型模料550)的樹脂成型封裝基板10。RDL結構900用作前側(或晶片側)RDL結構。RDL結構900可以包含至少一介電層912和至少一金屬層914。
根據本發明一實施例，介電層912可包含例如聚亞醯胺(polyimide)等有機材料，或例如氮化矽、氧化矽，或其類似物等無機材料，但不限於此。
金屬層914可包含鋁、銅、鎢、鈦、氮化鈦，或其類似物。根據所示實施例，金屬層914可以包含複數個佈線，接觸墊918從介電層914的頂表面顯露出來。
應理解的是，金屬層914和接觸墊918的層和佈局僅用於說明的目的。根據設計要求，在其他實施例中，可以在RDL結構900中形成更多層的金屬佈線。
如第13圖所示，將半導體晶片11與半導體晶片12設置在RDL結構900上。半導體晶片11與半導體晶片12可為覆晶晶片。半導體晶片11與半導體晶片12分別透過接觸墊918和金屬凸塊111及121電連接至RDL結構900。
根據本發明一實施例，金屬凸塊111及121具有一凸塊間距P1 ，其與半導體晶片11與半導體晶片12的輸出/輸入墊間距相同。例如，凸塊間距P1 可以小於100微米。錫球810具有一錫球間距P2 ，其與一印刷電路板(PCB)或主機板上的球墊間距相同。
可選擇地，另一種成型模料可以透過轉移成型施加到半導體晶片11和半導體晶片12上，但不限於此。 隨後，可以移除載板320。
如第14圖所示，可進行一切割製程，將晶圓級封裝1切割成個別的2.5D半導體封裝1a。根據本發明一實施例，省略了安裝在半導體晶片和封裝基板之間的常規中介層元件。
本發明一方面，提出一種半導體封裝1a，包含有：一樹脂成型封裝基板10，其包含一樹脂成型核心(即成型模料550)、複數個金屬插塞510，貫穿樹脂成型核心550的一正面及一背面、一前側重佈線層結構900，整體構成在樹脂成型核心550的正面上，以及一背側重佈線層結構700，整體構成在樹脂成型核心550的背面上。在前側RDL結構900和樹脂成型核心550之間或在背側RDL結構700和樹脂成型核心550之間沒有形成間隙。
一架橋矽穿通孔內連件101，埋設於樹脂成型核心550內，其中架橋矽穿通孔內連件101包含一矽基底部100、一內埋的重佈線層結構200，整體構成在矽基底部100上，以及複數個穿矽通孔110，設於矽基底部100中。
複數個連接件210，埋設於樹脂成型核心550內，其中複數個連接件210介於架橋矽穿通孔內連件101的重佈線層結構200與前側重佈線層結構900之間。
一第一半導體晶片11，設於前側重佈線層結構900上；一第二半導體晶片12，設於前側重佈線層結構900上，其中第一半導體晶片11與第二半導體晶片12位於共平面。複數個錫球810，設於背側重佈線層結構700的一下表面上。
根據本發明一實施例，第一半導體晶片11與第二半導體晶片12係經由前側重佈線層結構900與複數個金屬插塞510電連接至背側重佈線層結構700。根據本發明一實施例，電源訊號或接地訊號係經由複數個金屬插塞510傳遞，因為金屬插塞510的較大直徑能夠提供較低的電阻和改善的訊號完整性。
根據本發明一實施例，第一半導體晶片11與第二半導體晶片12係透過前側重佈線層結構900、或以其他方式經由前側重佈線層結構900、複數個連接件210及重佈線層結構200彼此電連接。因此，矽穿通孔內連件101 用作第一半導體晶片11和第二半導體晶片12之間的訊號傳輸橋，並且可以被稱為架橋矽穿通孔內連件。
根據本發明一實施例，第一半導體晶片11與第二半導體晶片12係透過前側重佈線層結構900、複數個連接件210、重佈線層結構200及金屬插塞110與重佈線層結構700互相電連接。例如，可以透過此路徑傳遞諸如高頻訊號等的數位訊號。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100‧‧‧半導體基板
110‧‧‧金屬插塞
100a‧‧‧正面
100b‧‧‧背面
200‧‧‧重佈線層(RDL)結構
202‧‧‧介電層
204‧‧‧金屬層
208‧‧‧接觸墊
210‧‧‧連接件
101‧‧‧矽穿通孔內連件
300‧‧‧載板
500‧‧‧模版層
501‧‧‧導孔
510‧‧‧金屬插塞
t‧‧‧厚度
601‧‧‧矽穿通孔內連件安裝區域
550‧‧‧成型模料
550a‧‧‧表面
700‧‧‧重佈線層(RDL)結構
712‧‧‧介電層
714‧‧‧金屬層
718‧‧‧接觸墊
810‧‧‧錫球
802‧‧‧防焊層
320‧‧‧載板
900‧‧‧重佈線層(RDL)結構
10‧‧‧樹脂成型封裝基板
912‧‧‧介電層
914‧‧‧金屬層
918‧‧‧接觸墊
11‧‧‧半導體晶片
12‧‧‧半導體晶片
111‧‧‧金屬凸塊
121‧‧‧金屬凸塊
P1‧‧‧ 間距
P2‧‧‧ 間距
1‧‧‧晶圓級封裝
1a‧‧‧半導體封裝
附圖包括對本發明的實施例提供進一步的理解，及被併入且構成說明書中的一部份。圖示說明一些本發明的實施例，並與說明書一起用於解釋其原理。 第1圖至第3圖係根據本發明之實施例所繪示的製作架橋矽穿通孔內連件的示例性方法。 第4圖至第14圖係根據本發明之實施例所繪示的製作2.5D半導體封裝的示例性方法的剖面圖，其使用樹脂成型封裝基板及埋入式架橋矽穿通孔內連件。

Claims (16)

  1. 一種半導體封裝，包含有： 一樹脂成型封裝基板，包含一樹脂成型核心、複數個金屬插塞，貫穿該樹脂成型核心的一正面及一背面、一前側重佈線層結構，整體構成在該樹脂成型核心的該正面上，以及一背側重佈線層結構，整體構成在該樹脂成型核心的該背面上； 一架橋矽穿通孔內連件，埋設於該樹脂成型核心內，其中該架橋矽穿通孔內連件包含一矽基底部、一內埋的重佈線層結構，整體構成在該矽基底部上，以及複數個穿矽通孔，設於該矽基底部中，其中該複數個穿矽通孔電連接該背側重佈線層結構； 複數個連接件，埋設於該樹脂成型核心內，其中該複數個連接件介於該架橋矽穿通孔內連件的該重佈線層結構與該前側重佈線層結構之間； 一第一半導體晶片，設於該前側重佈線層結構上； 一第二半導體晶片，設於該前側重佈線層結構上，其中該第一半導體晶片與該第二半導體晶片位於共平面；以及 複數個錫球，設於該背側重佈線層結構的一下表面上。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該第一半導體晶片與該第二半導體晶片係分別透過複數個第一金屬凸塊與複數個第二金屬凸塊設置在該前側重佈線層結構上。
  3. 如申請專利範圍第2項所述的半導體封裝，其中該複數個第一金屬凸塊與該複數個第二金屬凸塊具有一凸塊間距，其與該第一半導體晶片與該第二半導體晶片的輸出/輸入墊間距相同。
  4. 如申請專利範圍第3項所述的半導體封裝，其中該凸塊間距小於100微米。
  5. 如申請專利範圍第3項所述的半導體封裝，其中該錫球具有一錫球間距，其與一印刷電路板或主機板上的球墊間距相同。
  6. 如申請專利範圍第1項所述的半導體封裝，其中該第一半導體晶片與該第二半導體晶片係經由該前側重佈線層結構與該複數個金屬插塞電連接至該背側重佈線層結構。
  7. 如申請專利範圍第6項所述的半導體封裝，其中電源訊號或接地訊號係經由該複數個金屬插塞傳遞。
  8. 如申請專利範圍第1項所述的半導體封裝，其中該第一半導體晶片與該第二半導體晶片係透過該前側重佈線層結構、該複數個連接件與該架橋矽穿通孔內連件的該重佈線層結構互相電連接。
  9. 如申請專利範圍第1項所述的半導體封裝，其中數位訊號係經由該前側重佈線層結構、該複數個連接件、該架橋矽穿通孔內連件的該重佈線層結構，及該架橋矽穿通孔內連件的該複數個穿矽通孔傳遞。
  10. 如申請專利範圍第1項所述的半導體封裝，其中該架橋矽穿通孔內連件係被一成型模料模封包覆。
  11. 一種製作半導體封裝的方法，包含有： 提供一第一載板； 於該第一載板上形成一模版層； 於該模版層中形成複數個導孔； 分別於該複數個導孔中形成金屬插塞； 移除該模版層，於該第一載板上留下該些金屬插塞； 於該第一載板上安裝一架橋矽穿通孔內連件； 形成一成型模料，將該些金屬插塞與該架橋矽穿通孔內連件包覆起來； 研磨該成型模料與該架橋矽穿通孔內連件，顯露出該架橋矽穿通孔內連件的穿矽通孔以及埋設在該成型模料中的該些金屬插塞； 於該成型模料上形成一背側重佈線層結構； 於該背側重佈線層結構上形成複數個錫球； 移除該第一載板； 將一第二載板與該複數個錫球貼合； 於該成型模料上形成一前側重佈線層結構； 將一第一半導體晶片與一第二半導體晶片安置於該前側重佈線層結構上；以及 移除該第二載板。
  12. 如申請專利範圍第11項所述的製作半導體封裝的方法，其中該模版層包含一光阻或一定向自組裝材料。
  13. 如申請專利範圍第11項所述的製作半導體封裝的方法，其中該架橋矽穿通孔內連件包含一矽基底部、一重佈線層結構，整體構成在該矽基底部上，以及複數個穿矽通孔，設於該矽基底部中。
  14. 如申請專利範圍第13項所述的製作半導體封裝的方法，其中複數個連接件，其中該複數個連接件介於該架橋矽穿通孔內連件的該重佈線層結構與該前側重佈線層結構之間。
  15. 如申請專利範圍第13項所述的製作半導體封裝的方法，其中該複數個連接件被該成型模料模封包覆。
  16. 如申請專利範圍第11項所述的製作半導體封裝的方法，其中該複數個導孔係被金屬完全填滿，如此形成該些金屬插塞。
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